1 /*
2 * QEMU Machine
3 *
4 * Copyright (C) 2014 Red Hat Inc
5 *
6 * Authors:
7 * Marcel Apfelbaum <marcel.a@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/accel.h"
15 #include "sysemu/replay.h"
16 #include "hw/boards.h"
17 #include "hw/loader.h"
18 #include "qapi/error.h"
19 #include "qapi/qapi-visit-machine.h"
20 #include "qemu/madvise.h"
21 #include "qom/object_interfaces.h"
22 #include "sysemu/cpus.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/reset.h"
25 #include "sysemu/runstate.h"
26 #include "sysemu/xen.h"
27 #include "sysemu/qtest.h"
28 #include "hw/pci/pci_bridge.h"
29 #include "hw/mem/nvdimm.h"
30 #include "migration/global_state.h"
31 #include "exec/confidential-guest-support.h"
32 #include "hw/virtio/virtio-pci.h"
33 #include "hw/virtio/virtio-net.h"
34 #include "hw/virtio/virtio-iommu.h"
35 #include "audio/audio.h"
36
37 GlobalProperty hw_compat_9_1[] = {};
38 const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1);
39
40 GlobalProperty hw_compat_9_0[] = {
41 {"arm-cpu", "backcompat-cntfrq", "true" },
42 { "scsi-hd", "migrate-emulated-scsi-request", "false" },
43 { "scsi-cd", "migrate-emulated-scsi-request", "false" },
44 {"vfio-pci", "skip-vsc-check", "false" },
45 { "virtio-pci", "x-pcie-pm-no-soft-reset", "off" },
46 {"sd-card", "spec_version", "2" },
47 };
48 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
49
50 GlobalProperty hw_compat_8_2[] = {
51 { "migration", "zero-page-detection", "legacy"},
52 { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" },
53 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" },
54 { "virtio-gpu-device", "x-scanout-vmstate-version", "1" },
55 };
56 const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2);
57
58 GlobalProperty hw_compat_8_1[] = {
59 { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" },
60 { "ramfb", "x-migrate", "off" },
61 { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" },
62 { "igb", "x-pcie-flr-init", "off" },
63 { TYPE_VIRTIO_NET, "host_uso", "off"},
64 { TYPE_VIRTIO_NET, "guest_uso4", "off"},
65 { TYPE_VIRTIO_NET, "guest_uso6", "off"},
66 };
67 const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1);
68
69 GlobalProperty hw_compat_8_0[] = {
70 { "migration", "multifd-flush-after-each-section", "on"},
71 { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" },
72 };
73 const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0);
74
75 GlobalProperty hw_compat_7_2[] = {
76 { "e1000e", "migrate-timadj", "off" },
77 { "virtio-mem", "x-early-migration", "false" },
78 { "migration", "x-preempt-pre-7-2", "true" },
79 { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" },
80 };
81 const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2);
82
83 GlobalProperty hw_compat_7_1[] = {
84 { "virtio-device", "queue_reset", "false" },
85 { "virtio-rng-pci", "vectors", "0" },
86 { "virtio-rng-pci-transitional", "vectors", "0" },
87 { "virtio-rng-pci-non-transitional", "vectors", "0" },
88 };
89 const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1);
90
91 GlobalProperty hw_compat_7_0[] = {
92 { "arm-gicv3-common", "force-8-bit-prio", "on" },
93 { "nvme-ns", "eui64-default", "on"},
94 };
95 const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);
96
97 GlobalProperty hw_compat_6_2[] = {
98 { "PIIX4_PM", "x-not-migrate-acpi-index", "on"},
99 };
100 const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2);
101
102 GlobalProperty hw_compat_6_1[] = {
103 { "vhost-user-vsock-device", "seqpacket", "off" },
104 { "nvme-ns", "shared", "off" },
105 };
106 const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1);
107
108 GlobalProperty hw_compat_6_0[] = {
109 { "gpex-pcihost", "allow-unmapped-accesses", "false" },
110 { "i8042", "extended-state", "false"},
111 { "nvme-ns", "eui64-default", "off"},
112 { "e1000", "init-vet", "off" },
113 { "e1000e", "init-vet", "off" },
114 { "vhost-vsock-device", "seqpacket", "off" },
115 };
116 const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0);
117
118 GlobalProperty hw_compat_5_2[] = {
119 { "ICH9-LPC", "smm-compat", "on"},
120 { "PIIX4_PM", "smm-compat", "on"},
121 { "virtio-blk-device", "report-discard-granularity", "off" },
122 { "virtio-net-pci-base", "vectors", "3"},
123 { "nvme", "msix-exclusive-bar", "on"},
124 };
125 const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2);
126
127 GlobalProperty hw_compat_5_1[] = {
128 { "vhost-scsi", "num_queues", "1"},
129 { "vhost-user-blk", "num-queues", "1"},
130 { "vhost-user-scsi", "num_queues", "1"},
131 { "virtio-blk-device", "num-queues", "1"},
132 { "virtio-scsi-device", "num_queues", "1"},
133 { "nvme", "use-intel-id", "on"},
134 { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */
135 { "pl011", "migrate-clk", "off" },
136 { "virtio-pci", "x-ats-page-aligned", "off"},
137 };
138 const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
139
140 GlobalProperty hw_compat_5_0[] = {
141 { "pci-host-bridge", "x-config-reg-migration-enabled", "off" },
142 { "virtio-balloon-device", "page-poison", "false" },
143 { "vmport", "x-read-set-eax", "off" },
144 { "vmport", "x-signal-unsupported-cmd", "off" },
145 { "vmport", "x-report-vmx-type", "off" },
146 { "vmport", "x-cmds-v2", "off" },
147 { "virtio-device", "x-disable-legacy-check", "true" },
148 };
149 const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0);
150
151 GlobalProperty hw_compat_4_2[] = {
152 { "virtio-blk-device", "queue-size", "128"},
153 { "virtio-scsi-device", "virtqueue_size", "128"},
154 { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" },
155 { "virtio-blk-device", "seg-max-adjust", "off"},
156 { "virtio-scsi-device", "seg_max_adjust", "off"},
157 { "vhost-blk-device", "seg_max_adjust", "off"},
158 { "usb-host", "suppress-remote-wake", "off" },
159 { "usb-redir", "suppress-remote-wake", "off" },
160 { "qxl", "revision", "4" },
161 { "qxl-vga", "revision", "4" },
162 { "fw_cfg", "acpi-mr-restore", "false" },
163 { "virtio-device", "use-disabled-flag", "false" },
164 };
165 const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2);
166
167 GlobalProperty hw_compat_4_1[] = {
168 { "virtio-pci", "x-pcie-flr-init", "off" },
169 };
170 const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1);
171
172 GlobalProperty hw_compat_4_0[] = {
173 { "VGA", "edid", "false" },
174 { "secondary-vga", "edid", "false" },
175 { "bochs-display", "edid", "false" },
176 { "virtio-vga", "edid", "false" },
177 { "virtio-gpu-device", "edid", "false" },
178 { "virtio-device", "use-started", "false" },
179 { "virtio-balloon-device", "qemu-4-0-config-size", "true" },
180 { "pl031", "migrate-tick-offset", "false" },
181 };
182 const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
183
184 GlobalProperty hw_compat_3_1[] = {
185 { "pcie-root-port", "x-speed", "2_5" },
186 { "pcie-root-port", "x-width", "1" },
187 { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" },
188 { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" },
189 { "tpm-crb", "ppi", "false" },
190 { "tpm-tis", "ppi", "false" },
191 { "usb-kbd", "serial", "42" },
192 { "usb-mouse", "serial", "42" },
193 { "usb-tablet", "serial", "42" },
194 { "virtio-blk-device", "discard", "false" },
195 { "virtio-blk-device", "write-zeroes", "false" },
196 { "virtio-balloon-device", "qemu-4-0-config-size", "false" },
197 { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */
198 };
199 const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1);
200
201 GlobalProperty hw_compat_3_0[] = {};
202 const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0);
203
204 GlobalProperty hw_compat_2_12[] = {
205 { "hda-audio", "use-timer", "false" },
206 { "cirrus-vga", "global-vmstate", "true" },
207 { "VGA", "global-vmstate", "true" },
208 { "vmware-svga", "global-vmstate", "true" },
209 { "qxl-vga", "global-vmstate", "true" },
210 };
211 const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12);
212
213 GlobalProperty hw_compat_2_11[] = {
214 { "hpet", "hpet-offset-saved", "false" },
215 { "virtio-blk-pci", "vectors", "2" },
216 { "vhost-user-blk-pci", "vectors", "2" },
217 { "e1000", "migrate_tso_props", "off" },
218 };
219 const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11);
220
221 GlobalProperty hw_compat_2_10[] = {
222 { "virtio-mouse-device", "wheel-axis", "false" },
223 { "virtio-tablet-device", "wheel-axis", "false" },
224 };
225 const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10);
226
227 GlobalProperty hw_compat_2_9[] = {
228 { "pci-bridge", "shpc", "off" },
229 { "intel-iommu", "pt", "off" },
230 { "virtio-net-device", "x-mtu-bypass-backend", "off" },
231 { "pcie-root-port", "x-migrate-msix", "false" },
232 };
233 const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9);
234
235 GlobalProperty hw_compat_2_8[] = {
236 { "fw_cfg_mem", "x-file-slots", "0x10" },
237 { "fw_cfg_io", "x-file-slots", "0x10" },
238 { "pflash_cfi01", "old-multiple-chip-handling", "on" },
239 { "pci-bridge", "shpc", "on" },
240 { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" },
241 { "virtio-pci", "x-pcie-deverr-init", "off" },
242 { "virtio-pci", "x-pcie-lnkctl-init", "off" },
243 { "virtio-pci", "x-pcie-pm-init", "off" },
244 { "cirrus-vga", "vgamem_mb", "8" },
245 { "isa-cirrus-vga", "vgamem_mb", "8" },
246 };
247 const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8);
248
249 GlobalProperty hw_compat_2_7[] = {
250 { "virtio-pci", "page-per-vq", "on" },
251 { "virtio-serial-device", "emergency-write", "off" },
252 { "ioapic", "version", "0x11" },
253 { "intel-iommu", "x-buggy-eim", "true" },
254 { "virtio-pci", "x-ignore-backend-features", "on" },
255 };
256 const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7);
257
258 GlobalProperty hw_compat_2_6[] = {
259 { "virtio-mmio", "format_transport_address", "off" },
260 /* Optional because not all virtio-pci devices support legacy mode */
261 { "virtio-pci", "disable-modern", "on", .optional = true },
262 { "virtio-pci", "disable-legacy", "off", .optional = true },
263 };
264 const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6);
265
266 GlobalProperty hw_compat_2_5[] = {
267 { "isa-fdc", "fallback", "144" },
268 { "pvscsi", "x-old-pci-configuration", "on" },
269 { "pvscsi", "x-disable-pcie", "on" },
270 { "vmxnet3", "x-old-msi-offsets", "on" },
271 { "vmxnet3", "x-disable-pcie", "on" },
272 };
273 const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5);
274
275 GlobalProperty hw_compat_2_4[] = {
276 { "e1000", "extra_mac_registers", "off" },
277 { "virtio-pci", "x-disable-pcie", "on" },
278 { "virtio-pci", "migrate-extra", "off" },
279 { "fw_cfg_mem", "dma_enabled", "off" },
280 { "fw_cfg_io", "dma_enabled", "off" }
281 };
282 const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4);
283
284 GlobalProperty hw_compat_2_3[] = {
285 { "virtio-blk-pci", "any_layout", "off" },
286 { "virtio-balloon-pci", "any_layout", "off" },
287 { "virtio-serial-pci", "any_layout", "off" },
288 { "virtio-9p-pci", "any_layout", "off" },
289 { "virtio-rng-pci", "any_layout", "off" },
290 { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" },
291 { "migration", "send-configuration", "off" },
292 { "migration", "send-section-footer", "off" },
293 { "migration", "store-global-state", "off" },
294 };
295 const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3);
296
297 GlobalProperty hw_compat_2_2[] = {};
298 const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2);
299
300 GlobalProperty hw_compat_2_1[] = {
301 { "intel-hda", "old_msi_addr", "on" },
302 { "VGA", "qemu-extended-regs", "off" },
303 { "secondary-vga", "qemu-extended-regs", "off" },
304 { "virtio-scsi-pci", "any_layout", "off" },
305 { "usb-mouse", "usb_version", "1" },
306 { "usb-kbd", "usb_version", "1" },
307 { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" },
308 };
309 const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1);
310
311 MachineState *current_machine;
312
machine_get_kernel(Object * obj,Error ** errp)313 static char *machine_get_kernel(Object *obj, Error **errp)
314 {
315 MachineState *ms = MACHINE(obj);
316
317 return g_strdup(ms->kernel_filename);
318 }
319
machine_set_kernel(Object * obj,const char * value,Error ** errp)320 static void machine_set_kernel(Object *obj, const char *value, Error **errp)
321 {
322 MachineState *ms = MACHINE(obj);
323
324 g_free(ms->kernel_filename);
325 ms->kernel_filename = g_strdup(value);
326 }
327
machine_get_initrd(Object * obj,Error ** errp)328 static char *machine_get_initrd(Object *obj, Error **errp)
329 {
330 MachineState *ms = MACHINE(obj);
331
332 return g_strdup(ms->initrd_filename);
333 }
334
machine_set_initrd(Object * obj,const char * value,Error ** errp)335 static void machine_set_initrd(Object *obj, const char *value, Error **errp)
336 {
337 MachineState *ms = MACHINE(obj);
338
339 g_free(ms->initrd_filename);
340 ms->initrd_filename = g_strdup(value);
341 }
342
machine_get_append(Object * obj,Error ** errp)343 static char *machine_get_append(Object *obj, Error **errp)
344 {
345 MachineState *ms = MACHINE(obj);
346
347 return g_strdup(ms->kernel_cmdline);
348 }
349
machine_set_append(Object * obj,const char * value,Error ** errp)350 static void machine_set_append(Object *obj, const char *value, Error **errp)
351 {
352 MachineState *ms = MACHINE(obj);
353
354 g_free(ms->kernel_cmdline);
355 ms->kernel_cmdline = g_strdup(value);
356 }
357
machine_get_dtb(Object * obj,Error ** errp)358 static char *machine_get_dtb(Object *obj, Error **errp)
359 {
360 MachineState *ms = MACHINE(obj);
361
362 return g_strdup(ms->dtb);
363 }
364
machine_set_dtb(Object * obj,const char * value,Error ** errp)365 static void machine_set_dtb(Object *obj, const char *value, Error **errp)
366 {
367 MachineState *ms = MACHINE(obj);
368
369 g_free(ms->dtb);
370 ms->dtb = g_strdup(value);
371 }
372
machine_get_dumpdtb(Object * obj,Error ** errp)373 static char *machine_get_dumpdtb(Object *obj, Error **errp)
374 {
375 MachineState *ms = MACHINE(obj);
376
377 return g_strdup(ms->dumpdtb);
378 }
379
machine_set_dumpdtb(Object * obj,const char * value,Error ** errp)380 static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp)
381 {
382 MachineState *ms = MACHINE(obj);
383
384 g_free(ms->dumpdtb);
385 ms->dumpdtb = g_strdup(value);
386 }
387
machine_get_phandle_start(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)388 static void machine_get_phandle_start(Object *obj, Visitor *v,
389 const char *name, void *opaque,
390 Error **errp)
391 {
392 MachineState *ms = MACHINE(obj);
393 int64_t value = ms->phandle_start;
394
395 visit_type_int(v, name, &value, errp);
396 }
397
machine_set_phandle_start(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)398 static void machine_set_phandle_start(Object *obj, Visitor *v,
399 const char *name, void *opaque,
400 Error **errp)
401 {
402 MachineState *ms = MACHINE(obj);
403 int64_t value;
404
405 if (!visit_type_int(v, name, &value, errp)) {
406 return;
407 }
408
409 ms->phandle_start = value;
410 }
411
machine_get_dt_compatible(Object * obj,Error ** errp)412 static char *machine_get_dt_compatible(Object *obj, Error **errp)
413 {
414 MachineState *ms = MACHINE(obj);
415
416 return g_strdup(ms->dt_compatible);
417 }
418
machine_set_dt_compatible(Object * obj,const char * value,Error ** errp)419 static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp)
420 {
421 MachineState *ms = MACHINE(obj);
422
423 g_free(ms->dt_compatible);
424 ms->dt_compatible = g_strdup(value);
425 }
426
machine_get_dump_guest_core(Object * obj,Error ** errp)427 static bool machine_get_dump_guest_core(Object *obj, Error **errp)
428 {
429 MachineState *ms = MACHINE(obj);
430
431 return ms->dump_guest_core;
432 }
433
machine_set_dump_guest_core(Object * obj,bool value,Error ** errp)434 static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp)
435 {
436 MachineState *ms = MACHINE(obj);
437
438 if (!value && QEMU_MADV_DONTDUMP == QEMU_MADV_INVALID) {
439 error_setg(errp, "Dumping guest memory cannot be disabled on this host");
440 return;
441 }
442 ms->dump_guest_core = value;
443 }
444
machine_get_mem_merge(Object * obj,Error ** errp)445 static bool machine_get_mem_merge(Object *obj, Error **errp)
446 {
447 MachineState *ms = MACHINE(obj);
448
449 return ms->mem_merge;
450 }
451
machine_set_mem_merge(Object * obj,bool value,Error ** errp)452 static void machine_set_mem_merge(Object *obj, bool value, Error **errp)
453 {
454 MachineState *ms = MACHINE(obj);
455
456 if (value && QEMU_MADV_MERGEABLE == QEMU_MADV_INVALID) {
457 error_setg(errp, "Memory merging is not supported on this host");
458 return;
459 }
460 ms->mem_merge = value;
461 }
462
machine_get_usb(Object * obj,Error ** errp)463 static bool machine_get_usb(Object *obj, Error **errp)
464 {
465 MachineState *ms = MACHINE(obj);
466
467 return ms->usb;
468 }
469
machine_set_usb(Object * obj,bool value,Error ** errp)470 static void machine_set_usb(Object *obj, bool value, Error **errp)
471 {
472 MachineState *ms = MACHINE(obj);
473
474 ms->usb = value;
475 ms->usb_disabled = !value;
476 }
477
machine_get_graphics(Object * obj,Error ** errp)478 static bool machine_get_graphics(Object *obj, Error **errp)
479 {
480 MachineState *ms = MACHINE(obj);
481
482 return ms->enable_graphics;
483 }
484
machine_set_graphics(Object * obj,bool value,Error ** errp)485 static void machine_set_graphics(Object *obj, bool value, Error **errp)
486 {
487 MachineState *ms = MACHINE(obj);
488
489 ms->enable_graphics = value;
490 }
491
machine_get_firmware(Object * obj,Error ** errp)492 static char *machine_get_firmware(Object *obj, Error **errp)
493 {
494 MachineState *ms = MACHINE(obj);
495
496 return g_strdup(ms->firmware);
497 }
498
machine_set_firmware(Object * obj,const char * value,Error ** errp)499 static void machine_set_firmware(Object *obj, const char *value, Error **errp)
500 {
501 MachineState *ms = MACHINE(obj);
502
503 g_free(ms->firmware);
504 ms->firmware = g_strdup(value);
505 }
506
machine_set_suppress_vmdesc(Object * obj,bool value,Error ** errp)507 static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp)
508 {
509 MachineState *ms = MACHINE(obj);
510
511 ms->suppress_vmdesc = value;
512 }
513
machine_get_suppress_vmdesc(Object * obj,Error ** errp)514 static bool machine_get_suppress_vmdesc(Object *obj, Error **errp)
515 {
516 MachineState *ms = MACHINE(obj);
517
518 return ms->suppress_vmdesc;
519 }
520
machine_get_memory_encryption(Object * obj,Error ** errp)521 static char *machine_get_memory_encryption(Object *obj, Error **errp)
522 {
523 MachineState *ms = MACHINE(obj);
524
525 if (ms->cgs) {
526 return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs)));
527 }
528
529 return NULL;
530 }
531
machine_set_memory_encryption(Object * obj,const char * value,Error ** errp)532 static void machine_set_memory_encryption(Object *obj, const char *value,
533 Error **errp)
534 {
535 Object *cgs =
536 object_resolve_path_component(object_get_objects_root(), value);
537
538 if (!cgs) {
539 error_setg(errp, "No such memory encryption object '%s'", value);
540 return;
541 }
542
543 object_property_set_link(obj, "confidential-guest-support", cgs, errp);
544 }
545
machine_check_confidential_guest_support(const Object * obj,const char * name,Object * new_target,Error ** errp)546 static void machine_check_confidential_guest_support(const Object *obj,
547 const char *name,
548 Object *new_target,
549 Error **errp)
550 {
551 /*
552 * So far the only constraint is that the target has the
553 * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked
554 * by the QOM core
555 */
556 }
557
machine_get_nvdimm(Object * obj,Error ** errp)558 static bool machine_get_nvdimm(Object *obj, Error **errp)
559 {
560 MachineState *ms = MACHINE(obj);
561
562 return ms->nvdimms_state->is_enabled;
563 }
564
machine_set_nvdimm(Object * obj,bool value,Error ** errp)565 static void machine_set_nvdimm(Object *obj, bool value, Error **errp)
566 {
567 MachineState *ms = MACHINE(obj);
568
569 ms->nvdimms_state->is_enabled = value;
570 }
571
machine_get_hmat(Object * obj,Error ** errp)572 static bool machine_get_hmat(Object *obj, Error **errp)
573 {
574 MachineState *ms = MACHINE(obj);
575
576 return ms->numa_state->hmat_enabled;
577 }
578
machine_set_hmat(Object * obj,bool value,Error ** errp)579 static void machine_set_hmat(Object *obj, bool value, Error **errp)
580 {
581 MachineState *ms = MACHINE(obj);
582
583 ms->numa_state->hmat_enabled = value;
584 }
585
machine_get_mem(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)586 static void machine_get_mem(Object *obj, Visitor *v, const char *name,
587 void *opaque, Error **errp)
588 {
589 MachineState *ms = MACHINE(obj);
590 MemorySizeConfiguration mem = {
591 .has_size = true,
592 .size = ms->ram_size,
593 .has_max_size = !!ms->ram_slots,
594 .max_size = ms->maxram_size,
595 .has_slots = !!ms->ram_slots,
596 .slots = ms->ram_slots,
597 };
598 MemorySizeConfiguration *p_mem = &mem;
599
600 visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort);
601 }
602
machine_set_mem(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)603 static void machine_set_mem(Object *obj, Visitor *v, const char *name,
604 void *opaque, Error **errp)
605 {
606 ERRP_GUARD();
607 MachineState *ms = MACHINE(obj);
608 MachineClass *mc = MACHINE_GET_CLASS(obj);
609 MemorySizeConfiguration *mem;
610
611 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) {
612 return;
613 }
614
615 if (!mem->has_size) {
616 mem->has_size = true;
617 mem->size = mc->default_ram_size;
618 }
619 mem->size = QEMU_ALIGN_UP(mem->size, 8192);
620 if (mc->fixup_ram_size) {
621 mem->size = mc->fixup_ram_size(mem->size);
622 }
623 if ((ram_addr_t)mem->size != mem->size) {
624 error_setg(errp, "ram size too large");
625 goto out_free;
626 }
627
628 if (mem->has_max_size) {
629 if (mem->max_size < mem->size) {
630 error_setg(errp, "invalid value of maxmem: "
631 "maximum memory size (0x%" PRIx64 ") must be at least "
632 "the initial memory size (0x%" PRIx64 ")",
633 mem->max_size, mem->size);
634 goto out_free;
635 }
636 if (mem->has_slots && mem->slots && mem->max_size == mem->size) {
637 error_setg(errp, "invalid value of maxmem: "
638 "memory slots were specified but maximum memory size "
639 "(0x%" PRIx64 ") is equal to the initial memory size "
640 "(0x%" PRIx64 ")", mem->max_size, mem->size);
641 goto out_free;
642 }
643 ms->maxram_size = mem->max_size;
644 } else {
645 if (mem->has_slots) {
646 error_setg(errp, "slots specified but no max-size");
647 goto out_free;
648 }
649 ms->maxram_size = mem->size;
650 }
651 ms->ram_size = mem->size;
652 ms->ram_slots = mem->has_slots ? mem->slots : 0;
653 out_free:
654 qapi_free_MemorySizeConfiguration(mem);
655 }
656
machine_get_nvdimm_persistence(Object * obj,Error ** errp)657 static char *machine_get_nvdimm_persistence(Object *obj, Error **errp)
658 {
659 MachineState *ms = MACHINE(obj);
660
661 return g_strdup(ms->nvdimms_state->persistence_string);
662 }
663
machine_set_nvdimm_persistence(Object * obj,const char * value,Error ** errp)664 static void machine_set_nvdimm_persistence(Object *obj, const char *value,
665 Error **errp)
666 {
667 MachineState *ms = MACHINE(obj);
668 NVDIMMState *nvdimms_state = ms->nvdimms_state;
669
670 if (strcmp(value, "cpu") == 0) {
671 nvdimms_state->persistence = 3;
672 } else if (strcmp(value, "mem-ctrl") == 0) {
673 nvdimms_state->persistence = 2;
674 } else {
675 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
676 value);
677 return;
678 }
679
680 g_free(nvdimms_state->persistence_string);
681 nvdimms_state->persistence_string = g_strdup(value);
682 }
683
machine_class_allow_dynamic_sysbus_dev(MachineClass * mc,const char * type)684 void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
685 {
686 QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
687 }
688
device_is_dynamic_sysbus(MachineClass * mc,DeviceState * dev)689 bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
690 {
691 Object *obj = OBJECT(dev);
692
693 if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
694 return false;
695 }
696
697 return device_type_is_dynamic_sysbus(mc, object_get_typename(obj));
698 }
699
device_type_is_dynamic_sysbus(MachineClass * mc,const char * type)700 bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type)
701 {
702 bool allowed = false;
703 strList *wl;
704 ObjectClass *klass = object_class_by_name(type);
705
706 for (wl = mc->allowed_dynamic_sysbus_devices;
707 !allowed && wl;
708 wl = wl->next) {
709 allowed |= !!object_class_dynamic_cast(klass, wl->value);
710 }
711
712 return allowed;
713 }
714
machine_get_audiodev(Object * obj,Error ** errp)715 static char *machine_get_audiodev(Object *obj, Error **errp)
716 {
717 MachineState *ms = MACHINE(obj);
718
719 return g_strdup(ms->audiodev);
720 }
721
machine_set_audiodev(Object * obj,const char * value,Error ** errp)722 static void machine_set_audiodev(Object *obj, const char *value,
723 Error **errp)
724 {
725 MachineState *ms = MACHINE(obj);
726
727 if (!audio_state_by_name(value, errp)) {
728 return;
729 }
730
731 g_free(ms->audiodev);
732 ms->audiodev = g_strdup(value);
733 }
734
machine_query_hotpluggable_cpus(MachineState * machine)735 HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine)
736 {
737 int i;
738 HotpluggableCPUList *head = NULL;
739 MachineClass *mc = MACHINE_GET_CLASS(machine);
740
741 /* force board to initialize possible_cpus if it hasn't been done yet */
742 mc->possible_cpu_arch_ids(machine);
743
744 for (i = 0; i < machine->possible_cpus->len; i++) {
745 CPUState *cpu;
746 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
747
748 cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type);
749 cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count;
750 cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props,
751 sizeof(*cpu_item->props));
752
753 cpu = machine->possible_cpus->cpus[i].cpu;
754 if (cpu) {
755 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu));
756 }
757 QAPI_LIST_PREPEND(head, cpu_item);
758 }
759 return head;
760 }
761
762 /**
763 * machine_set_cpu_numa_node:
764 * @machine: machine object to modify
765 * @props: specifies which cpu objects to assign to
766 * numa node specified by @props.node_id
767 * @errp: if an error occurs, a pointer to an area to store the error
768 *
769 * Associate NUMA node specified by @props.node_id with cpu slots that
770 * match socket/core/thread-ids specified by @props. It's recommended to use
771 * query-hotpluggable-cpus.props values to specify affected cpu slots,
772 * which would lead to exact 1:1 mapping of cpu slots to NUMA node.
773 *
774 * However for CLI convenience it's possible to pass in subset of properties,
775 * which would affect all cpu slots that match it.
776 * Ex for pc machine:
777 * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \
778 * -numa cpu,node-id=0,socket_id=0 \
779 * -numa cpu,node-id=1,socket_id=1
780 * will assign all child cores of socket 0 to node 0 and
781 * of socket 1 to node 1.
782 *
783 * On attempt of reassigning (already assigned) cpu slot to another NUMA node,
784 * return error.
785 * Empty subset is disallowed and function will return with error in this case.
786 */
machine_set_cpu_numa_node(MachineState * machine,const CpuInstanceProperties * props,Error ** errp)787 void machine_set_cpu_numa_node(MachineState *machine,
788 const CpuInstanceProperties *props, Error **errp)
789 {
790 MachineClass *mc = MACHINE_GET_CLASS(machine);
791 NodeInfo *numa_info = machine->numa_state->nodes;
792 bool match = false;
793 int i;
794
795 if (!mc->possible_cpu_arch_ids) {
796 error_setg(errp, "mapping of CPUs to NUMA node is not supported");
797 return;
798 }
799
800 /* disabling node mapping is not supported, forbid it */
801 assert(props->has_node_id);
802
803 /* force board to initialize possible_cpus if it hasn't been done yet */
804 mc->possible_cpu_arch_ids(machine);
805
806 for (i = 0; i < machine->possible_cpus->len; i++) {
807 CPUArchId *slot = &machine->possible_cpus->cpus[i];
808
809 /* reject unsupported by board properties */
810 if (props->has_thread_id && !slot->props.has_thread_id) {
811 error_setg(errp, "thread-id is not supported");
812 return;
813 }
814
815 if (props->has_core_id && !slot->props.has_core_id) {
816 error_setg(errp, "core-id is not supported");
817 return;
818 }
819
820 if (props->has_module_id && !slot->props.has_module_id) {
821 error_setg(errp, "module-id is not supported");
822 return;
823 }
824
825 if (props->has_cluster_id && !slot->props.has_cluster_id) {
826 error_setg(errp, "cluster-id is not supported");
827 return;
828 }
829
830 if (props->has_socket_id && !slot->props.has_socket_id) {
831 error_setg(errp, "socket-id is not supported");
832 return;
833 }
834
835 if (props->has_die_id && !slot->props.has_die_id) {
836 error_setg(errp, "die-id is not supported");
837 return;
838 }
839
840 /* skip slots with explicit mismatch */
841 if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
842 continue;
843 }
844
845 if (props->has_core_id && props->core_id != slot->props.core_id) {
846 continue;
847 }
848
849 if (props->has_module_id &&
850 props->module_id != slot->props.module_id) {
851 continue;
852 }
853
854 if (props->has_cluster_id &&
855 props->cluster_id != slot->props.cluster_id) {
856 continue;
857 }
858
859 if (props->has_die_id && props->die_id != slot->props.die_id) {
860 continue;
861 }
862
863 if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
864 continue;
865 }
866
867 /* reject assignment if slot is already assigned, for compatibility
868 * of legacy cpu_index mapping with SPAPR core based mapping do not
869 * error out if cpu thread and matched core have the same node-id */
870 if (slot->props.has_node_id &&
871 slot->props.node_id != props->node_id) {
872 error_setg(errp, "CPU is already assigned to node-id: %" PRId64,
873 slot->props.node_id);
874 return;
875 }
876
877 /* assign slot to node as it's matched '-numa cpu' key */
878 match = true;
879 slot->props.node_id = props->node_id;
880 slot->props.has_node_id = props->has_node_id;
881
882 if (machine->numa_state->hmat_enabled) {
883 if ((numa_info[props->node_id].initiator < MAX_NODES) &&
884 (props->node_id != numa_info[props->node_id].initiator)) {
885 error_setg(errp, "The initiator of CPU NUMA node %" PRId64
886 " should be itself (got %" PRIu16 ")",
887 props->node_id, numa_info[props->node_id].initiator);
888 return;
889 }
890 numa_info[props->node_id].has_cpu = true;
891 numa_info[props->node_id].initiator = props->node_id;
892 }
893 }
894
895 if (!match) {
896 error_setg(errp, "no match found");
897 }
898 }
899
machine_get_smp(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)900 static void machine_get_smp(Object *obj, Visitor *v, const char *name,
901 void *opaque, Error **errp)
902 {
903 MachineState *ms = MACHINE(obj);
904 SMPConfiguration *config = &(SMPConfiguration){
905 .has_cpus = true, .cpus = ms->smp.cpus,
906 .has_drawers = true, .drawers = ms->smp.drawers,
907 .has_books = true, .books = ms->smp.books,
908 .has_sockets = true, .sockets = ms->smp.sockets,
909 .has_dies = true, .dies = ms->smp.dies,
910 .has_clusters = true, .clusters = ms->smp.clusters,
911 .has_modules = true, .modules = ms->smp.modules,
912 .has_cores = true, .cores = ms->smp.cores,
913 .has_threads = true, .threads = ms->smp.threads,
914 .has_maxcpus = true, .maxcpus = ms->smp.max_cpus,
915 };
916
917 if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) {
918 return;
919 }
920 }
921
machine_set_smp(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)922 static void machine_set_smp(Object *obj, Visitor *v, const char *name,
923 void *opaque, Error **errp)
924 {
925 MachineState *ms = MACHINE(obj);
926 g_autoptr(SMPConfiguration) config = NULL;
927
928 if (!visit_type_SMPConfiguration(v, name, &config, errp)) {
929 return;
930 }
931
932 machine_parse_smp_config(ms, config, errp);
933 }
934
machine_get_boot(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)935 static void machine_get_boot(Object *obj, Visitor *v, const char *name,
936 void *opaque, Error **errp)
937 {
938 MachineState *ms = MACHINE(obj);
939 BootConfiguration *config = &ms->boot_config;
940 visit_type_BootConfiguration(v, name, &config, &error_abort);
941 }
942
machine_free_boot_config(MachineState * ms)943 static void machine_free_boot_config(MachineState *ms)
944 {
945 g_free(ms->boot_config.order);
946 g_free(ms->boot_config.once);
947 g_free(ms->boot_config.splash);
948 }
949
machine_copy_boot_config(MachineState * ms,BootConfiguration * config)950 static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config)
951 {
952 MachineClass *machine_class = MACHINE_GET_CLASS(ms);
953
954 machine_free_boot_config(ms);
955 ms->boot_config = *config;
956 if (!config->order) {
957 ms->boot_config.order = g_strdup(machine_class->default_boot_order);
958 }
959 }
960
machine_set_boot(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)961 static void machine_set_boot(Object *obj, Visitor *v, const char *name,
962 void *opaque, Error **errp)
963 {
964 ERRP_GUARD();
965 MachineState *ms = MACHINE(obj);
966 BootConfiguration *config = NULL;
967
968 if (!visit_type_BootConfiguration(v, name, &config, errp)) {
969 return;
970 }
971 if (config->order) {
972 validate_bootdevices(config->order, errp);
973 if (*errp) {
974 goto out_free;
975 }
976 }
977 if (config->once) {
978 validate_bootdevices(config->once, errp);
979 if (*errp) {
980 goto out_free;
981 }
982 }
983
984 machine_copy_boot_config(ms, config);
985 /* Strings live in ms->boot_config. */
986 free(config);
987 return;
988
989 out_free:
990 qapi_free_BootConfiguration(config);
991 }
992
machine_add_audiodev_property(MachineClass * mc)993 void machine_add_audiodev_property(MachineClass *mc)
994 {
995 ObjectClass *oc = OBJECT_CLASS(mc);
996
997 object_class_property_add_str(oc, "audiodev",
998 machine_get_audiodev,
999 machine_set_audiodev);
1000 object_class_property_set_description(oc, "audiodev",
1001 "Audiodev to use for default machine devices");
1002 }
1003
machine_class_init(ObjectClass * oc,void * data)1004 static void machine_class_init(ObjectClass *oc, void *data)
1005 {
1006 MachineClass *mc = MACHINE_CLASS(oc);
1007
1008 /* Default 128 MB as guest ram size */
1009 mc->default_ram_size = 128 * MiB;
1010 mc->rom_file_has_mr = true;
1011 /*
1012 * SMBIOS 3.1.0 7.18.5 Memory Device — Extended Size
1013 * use max possible value that could be encoded into
1014 * 'Extended Size' field (2047Tb).
1015 */
1016 mc->smbios_memory_device_size = 2047 * TiB;
1017
1018 /* numa node memory size aligned on 8MB by default.
1019 * On Linux, each node's border has to be 8MB aligned
1020 */
1021 mc->numa_mem_align_shift = 23;
1022
1023 object_class_property_add_str(oc, "kernel",
1024 machine_get_kernel, machine_set_kernel);
1025 object_class_property_set_description(oc, "kernel",
1026 "Linux kernel image file");
1027
1028 object_class_property_add_str(oc, "initrd",
1029 machine_get_initrd, machine_set_initrd);
1030 object_class_property_set_description(oc, "initrd",
1031 "Linux initial ramdisk file");
1032
1033 object_class_property_add_str(oc, "append",
1034 machine_get_append, machine_set_append);
1035 object_class_property_set_description(oc, "append",
1036 "Linux kernel command line");
1037
1038 object_class_property_add_str(oc, "dtb",
1039 machine_get_dtb, machine_set_dtb);
1040 object_class_property_set_description(oc, "dtb",
1041 "Linux kernel device tree file");
1042
1043 object_class_property_add_str(oc, "dumpdtb",
1044 machine_get_dumpdtb, machine_set_dumpdtb);
1045 object_class_property_set_description(oc, "dumpdtb",
1046 "Dump current dtb to a file and quit");
1047
1048 object_class_property_add(oc, "boot", "BootConfiguration",
1049 machine_get_boot, machine_set_boot,
1050 NULL, NULL);
1051 object_class_property_set_description(oc, "boot",
1052 "Boot configuration");
1053
1054 object_class_property_add(oc, "smp", "SMPConfiguration",
1055 machine_get_smp, machine_set_smp,
1056 NULL, NULL);
1057 object_class_property_set_description(oc, "smp",
1058 "CPU topology");
1059
1060 object_class_property_add(oc, "phandle-start", "int",
1061 machine_get_phandle_start, machine_set_phandle_start,
1062 NULL, NULL);
1063 object_class_property_set_description(oc, "phandle-start",
1064 "The first phandle ID we may generate dynamically");
1065
1066 object_class_property_add_str(oc, "dt-compatible",
1067 machine_get_dt_compatible, machine_set_dt_compatible);
1068 object_class_property_set_description(oc, "dt-compatible",
1069 "Overrides the \"compatible\" property of the dt root node");
1070
1071 object_class_property_add_bool(oc, "dump-guest-core",
1072 machine_get_dump_guest_core, machine_set_dump_guest_core);
1073 object_class_property_set_description(oc, "dump-guest-core",
1074 "Include guest memory in a core dump");
1075
1076 object_class_property_add_bool(oc, "mem-merge",
1077 machine_get_mem_merge, machine_set_mem_merge);
1078 object_class_property_set_description(oc, "mem-merge",
1079 "Enable/disable memory merge support");
1080
1081 object_class_property_add_bool(oc, "usb",
1082 machine_get_usb, machine_set_usb);
1083 object_class_property_set_description(oc, "usb",
1084 "Set on/off to enable/disable usb");
1085
1086 object_class_property_add_bool(oc, "graphics",
1087 machine_get_graphics, machine_set_graphics);
1088 object_class_property_set_description(oc, "graphics",
1089 "Set on/off to enable/disable graphics emulation");
1090
1091 object_class_property_add_str(oc, "firmware",
1092 machine_get_firmware, machine_set_firmware);
1093 object_class_property_set_description(oc, "firmware",
1094 "Firmware image");
1095
1096 object_class_property_add_bool(oc, "suppress-vmdesc",
1097 machine_get_suppress_vmdesc, machine_set_suppress_vmdesc);
1098 object_class_property_set_description(oc, "suppress-vmdesc",
1099 "Set on to disable self-describing migration");
1100
1101 object_class_property_add_link(oc, "confidential-guest-support",
1102 TYPE_CONFIDENTIAL_GUEST_SUPPORT,
1103 offsetof(MachineState, cgs),
1104 machine_check_confidential_guest_support,
1105 OBJ_PROP_LINK_STRONG);
1106 object_class_property_set_description(oc, "confidential-guest-support",
1107 "Set confidential guest scheme to support");
1108
1109 /* For compatibility */
1110 object_class_property_add_str(oc, "memory-encryption",
1111 machine_get_memory_encryption, machine_set_memory_encryption);
1112 object_class_property_set_description(oc, "memory-encryption",
1113 "Set memory encryption object to use");
1114
1115 object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND,
1116 offsetof(MachineState, memdev), object_property_allow_set_link,
1117 OBJ_PROP_LINK_STRONG);
1118 object_class_property_set_description(oc, "memory-backend",
1119 "Set RAM backend"
1120 "Valid value is ID of hostmem based backend");
1121
1122 object_class_property_add(oc, "memory", "MemorySizeConfiguration",
1123 machine_get_mem, machine_set_mem,
1124 NULL, NULL);
1125 object_class_property_set_description(oc, "memory",
1126 "Memory size configuration");
1127 }
1128
machine_class_base_init(ObjectClass * oc,void * data)1129 static void machine_class_base_init(ObjectClass *oc, void *data)
1130 {
1131 MachineClass *mc = MACHINE_CLASS(oc);
1132 mc->max_cpus = mc->max_cpus ?: 1;
1133 mc->min_cpus = mc->min_cpus ?: 1;
1134 mc->default_cpus = mc->default_cpus ?: 1;
1135
1136 if (!object_class_is_abstract(oc)) {
1137 const char *cname = object_class_get_name(oc);
1138 assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX));
1139 mc->name = g_strndup(cname,
1140 strlen(cname) - strlen(TYPE_MACHINE_SUFFIX));
1141 mc->compat_props = g_ptr_array_new();
1142 }
1143 }
1144
machine_initfn(Object * obj)1145 static void machine_initfn(Object *obj)
1146 {
1147 MachineState *ms = MACHINE(obj);
1148 MachineClass *mc = MACHINE_GET_CLASS(obj);
1149
1150 container_get(obj, "/peripheral");
1151 container_get(obj, "/peripheral-anon");
1152
1153 ms->dump_guest_core = true;
1154 ms->mem_merge = (QEMU_MADV_MERGEABLE != QEMU_MADV_INVALID);
1155 ms->enable_graphics = true;
1156 ms->kernel_cmdline = g_strdup("");
1157 ms->ram_size = mc->default_ram_size;
1158 ms->maxram_size = mc->default_ram_size;
1159
1160 if (mc->nvdimm_supported) {
1161 ms->nvdimms_state = g_new0(NVDIMMState, 1);
1162 object_property_add_bool(obj, "nvdimm",
1163 machine_get_nvdimm, machine_set_nvdimm);
1164 object_property_set_description(obj, "nvdimm",
1165 "Set on/off to enable/disable "
1166 "NVDIMM instantiation");
1167
1168 object_property_add_str(obj, "nvdimm-persistence",
1169 machine_get_nvdimm_persistence,
1170 machine_set_nvdimm_persistence);
1171 object_property_set_description(obj, "nvdimm-persistence",
1172 "Set NVDIMM persistence"
1173 "Valid values are cpu, mem-ctrl");
1174 }
1175
1176 if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) {
1177 ms->numa_state = g_new0(NumaState, 1);
1178 object_property_add_bool(obj, "hmat",
1179 machine_get_hmat, machine_set_hmat);
1180 object_property_set_description(obj, "hmat",
1181 "Set on/off to enable/disable "
1182 "ACPI Heterogeneous Memory Attribute "
1183 "Table (HMAT)");
1184 }
1185
1186 /* default to mc->default_cpus */
1187 ms->smp.cpus = mc->default_cpus;
1188 ms->smp.max_cpus = mc->default_cpus;
1189 ms->smp.drawers = 1;
1190 ms->smp.books = 1;
1191 ms->smp.sockets = 1;
1192 ms->smp.dies = 1;
1193 ms->smp.clusters = 1;
1194 ms->smp.modules = 1;
1195 ms->smp.cores = 1;
1196 ms->smp.threads = 1;
1197
1198 machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
1199 }
1200
machine_finalize(Object * obj)1201 static void machine_finalize(Object *obj)
1202 {
1203 MachineState *ms = MACHINE(obj);
1204
1205 machine_free_boot_config(ms);
1206 g_free(ms->kernel_filename);
1207 g_free(ms->initrd_filename);
1208 g_free(ms->kernel_cmdline);
1209 g_free(ms->dtb);
1210 g_free(ms->dumpdtb);
1211 g_free(ms->dt_compatible);
1212 g_free(ms->firmware);
1213 g_free(ms->device_memory);
1214 g_free(ms->nvdimms_state);
1215 g_free(ms->numa_state);
1216 g_free(ms->audiodev);
1217 }
1218
machine_usb(MachineState * machine)1219 bool machine_usb(MachineState *machine)
1220 {
1221 return machine->usb;
1222 }
1223
machine_phandle_start(MachineState * machine)1224 int machine_phandle_start(MachineState *machine)
1225 {
1226 return machine->phandle_start;
1227 }
1228
machine_dump_guest_core(MachineState * machine)1229 bool machine_dump_guest_core(MachineState *machine)
1230 {
1231 return machine->dump_guest_core;
1232 }
1233
machine_mem_merge(MachineState * machine)1234 bool machine_mem_merge(MachineState *machine)
1235 {
1236 return machine->mem_merge;
1237 }
1238
machine_require_guest_memfd(MachineState * machine)1239 bool machine_require_guest_memfd(MachineState *machine)
1240 {
1241 return machine->cgs && machine->cgs->require_guest_memfd;
1242 }
1243
cpu_slot_to_string(const CPUArchId * cpu)1244 static char *cpu_slot_to_string(const CPUArchId *cpu)
1245 {
1246 GString *s = g_string_new(NULL);
1247 if (cpu->props.has_socket_id) {
1248 g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id);
1249 }
1250 if (cpu->props.has_die_id) {
1251 if (s->len) {
1252 g_string_append_printf(s, ", ");
1253 }
1254 g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
1255 }
1256 if (cpu->props.has_cluster_id) {
1257 if (s->len) {
1258 g_string_append_printf(s, ", ");
1259 }
1260 g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
1261 }
1262 if (cpu->props.has_module_id) {
1263 if (s->len) {
1264 g_string_append_printf(s, ", ");
1265 }
1266 g_string_append_printf(s, "module-id: %"PRId64, cpu->props.module_id);
1267 }
1268 if (cpu->props.has_core_id) {
1269 if (s->len) {
1270 g_string_append_printf(s, ", ");
1271 }
1272 g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id);
1273 }
1274 if (cpu->props.has_thread_id) {
1275 if (s->len) {
1276 g_string_append_printf(s, ", ");
1277 }
1278 g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id);
1279 }
1280 return g_string_free(s, false);
1281 }
1282
numa_validate_initiator(NumaState * numa_state)1283 static void numa_validate_initiator(NumaState *numa_state)
1284 {
1285 int i;
1286 NodeInfo *numa_info = numa_state->nodes;
1287
1288 for (i = 0; i < numa_state->num_nodes; i++) {
1289 if (numa_info[i].initiator == MAX_NODES) {
1290 continue;
1291 }
1292
1293 if (!numa_info[numa_info[i].initiator].present) {
1294 error_report("NUMA node %" PRIu16 " is missing, use "
1295 "'-numa node' option to declare it first",
1296 numa_info[i].initiator);
1297 exit(1);
1298 }
1299
1300 if (!numa_info[numa_info[i].initiator].has_cpu) {
1301 error_report("The initiator of NUMA node %d is invalid", i);
1302 exit(1);
1303 }
1304 }
1305 }
1306
machine_numa_finish_cpu_init(MachineState * machine)1307 static void machine_numa_finish_cpu_init(MachineState *machine)
1308 {
1309 int i;
1310 bool default_mapping;
1311 GString *s = g_string_new(NULL);
1312 MachineClass *mc = MACHINE_GET_CLASS(machine);
1313 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine);
1314
1315 assert(machine->numa_state->num_nodes);
1316 for (i = 0; i < possible_cpus->len; i++) {
1317 if (possible_cpus->cpus[i].props.has_node_id) {
1318 break;
1319 }
1320 }
1321 default_mapping = (i == possible_cpus->len);
1322
1323 for (i = 0; i < possible_cpus->len; i++) {
1324 const CPUArchId *cpu_slot = &possible_cpus->cpus[i];
1325
1326 if (!cpu_slot->props.has_node_id) {
1327 /* fetch default mapping from board and enable it */
1328 CpuInstanceProperties props = cpu_slot->props;
1329
1330 props.node_id = mc->get_default_cpu_node_id(machine, i);
1331 if (!default_mapping) {
1332 /* record slots with not set mapping,
1333 * TODO: make it hard error in future */
1334 char *cpu_str = cpu_slot_to_string(cpu_slot);
1335 g_string_append_printf(s, "%sCPU %d [%s]",
1336 s->len ? ", " : "", i, cpu_str);
1337 g_free(cpu_str);
1338
1339 /* non mapped cpus used to fallback to node 0 */
1340 props.node_id = 0;
1341 }
1342
1343 props.has_node_id = true;
1344 machine_set_cpu_numa_node(machine, &props, &error_fatal);
1345 }
1346 }
1347
1348 if (machine->numa_state->hmat_enabled) {
1349 numa_validate_initiator(machine->numa_state);
1350 }
1351
1352 if (s->len && !qtest_enabled()) {
1353 warn_report("CPU(s) not present in any NUMA nodes: %s",
1354 s->str);
1355 warn_report("All CPU(s) up to maxcpus should be described "
1356 "in NUMA config, ability to start up with partial NUMA "
1357 "mappings is obsoleted and will be removed in future");
1358 }
1359 g_string_free(s, true);
1360 }
1361
validate_cpu_cluster_to_numa_boundary(MachineState * ms)1362 static void validate_cpu_cluster_to_numa_boundary(MachineState *ms)
1363 {
1364 MachineClass *mc = MACHINE_GET_CLASS(ms);
1365 NumaState *state = ms->numa_state;
1366 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1367 const CPUArchId *cpus = possible_cpus->cpus;
1368 int i, j;
1369
1370 if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) {
1371 return;
1372 }
1373
1374 /*
1375 * The Linux scheduling domain can't be parsed when the multiple CPUs
1376 * in one cluster have been associated with different NUMA nodes. However,
1377 * it's fine to associate one NUMA node with CPUs in different clusters.
1378 */
1379 for (i = 0; i < possible_cpus->len; i++) {
1380 for (j = i + 1; j < possible_cpus->len; j++) {
1381 if (cpus[i].props.has_socket_id &&
1382 cpus[i].props.has_cluster_id &&
1383 cpus[i].props.has_node_id &&
1384 cpus[j].props.has_socket_id &&
1385 cpus[j].props.has_cluster_id &&
1386 cpus[j].props.has_node_id &&
1387 cpus[i].props.socket_id == cpus[j].props.socket_id &&
1388 cpus[i].props.cluster_id == cpus[j].props.cluster_id &&
1389 cpus[i].props.node_id != cpus[j].props.node_id) {
1390 warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64
1391 " have been associated with node-%" PRId64 " and node-%" PRId64
1392 " respectively. It can cause OSes like Linux to"
1393 " misbehave", i, j, cpus[i].props.socket_id,
1394 cpus[i].props.cluster_id, cpus[i].props.node_id,
1395 cpus[j].props.node_id);
1396 }
1397 }
1398 }
1399 }
1400
machine_consume_memdev(MachineState * machine,HostMemoryBackend * backend)1401 MemoryRegion *machine_consume_memdev(MachineState *machine,
1402 HostMemoryBackend *backend)
1403 {
1404 MemoryRegion *ret = host_memory_backend_get_memory(backend);
1405
1406 if (host_memory_backend_is_mapped(backend)) {
1407 error_report("memory backend %s can't be used multiple times.",
1408 object_get_canonical_path_component(OBJECT(backend)));
1409 exit(EXIT_FAILURE);
1410 }
1411 host_memory_backend_set_mapped(backend, true);
1412 vmstate_register_ram_global(ret);
1413 return ret;
1414 }
1415
create_default_memdev(MachineState * ms,const char * path,Error ** errp)1416 static bool create_default_memdev(MachineState *ms, const char *path, Error **errp)
1417 {
1418 Object *obj;
1419 MachineClass *mc = MACHINE_GET_CLASS(ms);
1420 bool r = false;
1421
1422 obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM);
1423 if (path) {
1424 if (!object_property_set_str(obj, "mem-path", path, errp)) {
1425 goto out;
1426 }
1427 }
1428 if (!object_property_set_int(obj, "size", ms->ram_size, errp)) {
1429 goto out;
1430 }
1431 object_property_add_child(object_get_objects_root(), mc->default_ram_id,
1432 obj);
1433 /* Ensure backend's memory region name is equal to mc->default_ram_id */
1434 if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id",
1435 false, errp)) {
1436 goto out;
1437 }
1438 if (!user_creatable_complete(USER_CREATABLE(obj), errp)) {
1439 goto out;
1440 }
1441 r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp);
1442
1443 out:
1444 object_unref(obj);
1445 return r;
1446 }
1447
machine_class_default_cpu_type(MachineClass * mc)1448 const char *machine_class_default_cpu_type(MachineClass *mc)
1449 {
1450 if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) {
1451 /* Only a single CPU type allowed: use it as default. */
1452 return mc->valid_cpu_types[0];
1453 }
1454 return mc->default_cpu_type;
1455 }
1456
is_cpu_type_supported(const MachineState * machine,Error ** errp)1457 static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
1458 {
1459 MachineClass *mc = MACHINE_GET_CLASS(machine);
1460 ObjectClass *oc = object_class_by_name(machine->cpu_type);
1461 CPUClass *cc;
1462 int i;
1463
1464 /*
1465 * Check if the user specified CPU type is supported when the valid
1466 * CPU types have been determined. Note that the user specified CPU
1467 * type is provided through '-cpu' option.
1468 */
1469 if (mc->valid_cpu_types) {
1470 assert(mc->valid_cpu_types[0] != NULL);
1471 for (i = 0; mc->valid_cpu_types[i]; i++) {
1472 if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) {
1473 break;
1474 }
1475 }
1476
1477 /* The user specified CPU type isn't valid */
1478 if (!mc->valid_cpu_types[i]) {
1479 g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
1480 error_setg(errp, "Invalid CPU model: %s", requested);
1481 if (!mc->valid_cpu_types[1]) {
1482 g_autofree char *model = cpu_model_from_type(
1483 mc->valid_cpu_types[0]);
1484 error_append_hint(errp, "The only valid type is: %s\n", model);
1485 } else {
1486 error_append_hint(errp, "The valid models are: ");
1487 for (i = 0; mc->valid_cpu_types[i]; i++) {
1488 g_autofree char *model = cpu_model_from_type(
1489 mc->valid_cpu_types[i]);
1490 error_append_hint(errp, "%s%s",
1491 model,
1492 mc->valid_cpu_types[i + 1] ? ", " : "");
1493 }
1494 error_append_hint(errp, "\n");
1495 }
1496
1497 return false;
1498 }
1499 }
1500
1501 /* Check if CPU type is deprecated and warn if so */
1502 cc = CPU_CLASS(oc);
1503 assert(cc != NULL);
1504 if (cc->deprecation_note) {
1505 warn_report("CPU model %s is deprecated -- %s",
1506 machine->cpu_type, cc->deprecation_note);
1507 }
1508
1509 return true;
1510 }
1511
machine_run_board_init(MachineState * machine,const char * mem_path,Error ** errp)1512 void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp)
1513 {
1514 ERRP_GUARD();
1515 MachineClass *machine_class = MACHINE_GET_CLASS(machine);
1516
1517 /* This checkpoint is required by replay to separate prior clock
1518 reading from the other reads, because timer polling functions query
1519 clock values from the log. */
1520 replay_checkpoint(CHECKPOINT_INIT);
1521
1522 if (!xen_enabled()) {
1523 /* On 32-bit hosts, QEMU is limited by virtual address space */
1524 if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) {
1525 error_setg(errp, "at most 2047 MB RAM can be simulated");
1526 return;
1527 }
1528 }
1529
1530 if (machine->memdev) {
1531 ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev),
1532 "size", &error_abort);
1533 if (backend_size != machine->ram_size) {
1534 error_setg(errp, "Machine memory size does not match the size of the memory backend");
1535 return;
1536 }
1537 } else if (machine_class->default_ram_id && machine->ram_size &&
1538 numa_uses_legacy_mem()) {
1539 if (object_property_find(object_get_objects_root(),
1540 machine_class->default_ram_id)) {
1541 error_setg(errp, "object's id '%s' is reserved for the default"
1542 " RAM backend, it can't be used for any other purposes",
1543 machine_class->default_ram_id);
1544 error_append_hint(errp,
1545 "Change the object's 'id' to something else or disable"
1546 " automatic creation of the default RAM backend by setting"
1547 " 'memory-backend=%s' with '-machine'.\n",
1548 machine_class->default_ram_id);
1549 return;
1550 }
1551 if (!create_default_memdev(current_machine, mem_path, errp)) {
1552 return;
1553 }
1554 }
1555
1556 if (machine->numa_state) {
1557 numa_complete_configuration(machine);
1558 if (machine->numa_state->num_nodes) {
1559 machine_numa_finish_cpu_init(machine);
1560 if (machine_class->cpu_cluster_has_numa_boundary) {
1561 validate_cpu_cluster_to_numa_boundary(machine);
1562 }
1563 }
1564 }
1565
1566 if (!machine->ram && machine->memdev) {
1567 machine->ram = machine_consume_memdev(machine, machine->memdev);
1568 }
1569
1570 /* Check if the CPU type is supported */
1571 if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) {
1572 return;
1573 }
1574
1575 if (machine->cgs) {
1576 /*
1577 * With confidential guests, the host can't see the real
1578 * contents of RAM, so there's no point in it trying to merge
1579 * areas.
1580 */
1581 machine_set_mem_merge(OBJECT(machine), false, &error_abort);
1582
1583 /*
1584 * Virtio devices can't count on directly accessing guest
1585 * memory, so they need iommu_platform=on to use normal DMA
1586 * mechanisms. That requires also disabling legacy virtio
1587 * support for those virtio pci devices which allow it.
1588 */
1589 object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy",
1590 "on", true);
1591 object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform",
1592 "on", false);
1593 }
1594
1595 accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator));
1596 machine_class->init(machine);
1597 phase_advance(PHASE_MACHINE_INITIALIZED);
1598 }
1599
1600 static NotifierList machine_init_done_notifiers =
1601 NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers);
1602
qemu_add_machine_init_done_notifier(Notifier * notify)1603 void qemu_add_machine_init_done_notifier(Notifier *notify)
1604 {
1605 notifier_list_add(&machine_init_done_notifiers, notify);
1606 if (phase_check(PHASE_MACHINE_READY)) {
1607 notify->notify(notify, NULL);
1608 }
1609 }
1610
qemu_remove_machine_init_done_notifier(Notifier * notify)1611 void qemu_remove_machine_init_done_notifier(Notifier *notify)
1612 {
1613 notifier_remove(notify);
1614 }
1615
qdev_machine_creation_done(void)1616 void qdev_machine_creation_done(void)
1617 {
1618 cpu_synchronize_all_post_init();
1619
1620 if (current_machine->boot_config.once) {
1621 qemu_boot_set(current_machine->boot_config.once, &error_fatal);
1622 qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order));
1623 }
1624
1625 /*
1626 * ok, initial machine setup is done, starting from now we can
1627 * only create hotpluggable devices
1628 */
1629 phase_advance(PHASE_MACHINE_READY);
1630 qdev_assert_realized_properly();
1631
1632 /* TODO: once all bus devices are qdevified, this should be done
1633 * when bus is created by qdev.c */
1634 /*
1635 * This is where we arrange for the sysbus to be reset when the
1636 * whole simulation is reset. In turn, resetting the sysbus will cause
1637 * all devices hanging off it (and all their child buses, recursively)
1638 * to be reset. Note that this will *not* reset any Device objects
1639 * which are not attached to some part of the qbus tree!
1640 */
1641 qemu_register_resettable(OBJECT(sysbus_get_default()));
1642
1643 notifier_list_notify(&machine_init_done_notifiers, NULL);
1644
1645 if (rom_check_and_register_reset() != 0) {
1646 exit(1);
1647 }
1648
1649 replay_start();
1650
1651 /* This checkpoint is required by replay to separate prior clock
1652 reading from the other reads, because timer polling functions query
1653 clock values from the log. */
1654 replay_checkpoint(CHECKPOINT_RESET);
1655 qemu_system_reset(SHUTDOWN_CAUSE_NONE);
1656 register_global_state();
1657 }
1658
1659 static const TypeInfo machine_info = {
1660 .name = TYPE_MACHINE,
1661 .parent = TYPE_OBJECT,
1662 .abstract = true,
1663 .class_size = sizeof(MachineClass),
1664 .class_init = machine_class_init,
1665 .class_base_init = machine_class_base_init,
1666 .instance_size = sizeof(MachineState),
1667 .instance_init = machine_initfn,
1668 .instance_finalize = machine_finalize,
1669 };
1670
machine_register_types(void)1671 static void machine_register_types(void)
1672 {
1673 type_register_static(&machine_info);
1674 }
1675
1676 type_init(machine_register_types)
1677