xref: /openbsd/sys/arch/alpha/include/logout.h (revision 13b1a670)
1 /* $OpenBSD: logout.h,v 1.3 2009/09/25 04:38:40 miod Exp $ */
2 /* $NetBSD: logout.h,v 1.6 2005/12/11 12:16:16 christos Exp $ */
3 
4 /*
5  * Copyright (c) 2009 Miodrag Vallat.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 /*
20  * Copyright (c) 1998 by Matthew Jacob
21  * NASA AMES Research Center.
22  * All rights reserved.
23  *
24  * Redistribution and use in source and binary forms, with or without
25  * modification, are permitted provided that the following conditions
26  * are met:
27  * 1. Redistributions of source code must retain the above copyright
28  *    notice immediately at the beginning of the file, without modification,
29  *    this list of conditions, and the following disclaimer.
30  * 2. Redistributions in binary form must reproduce the above copyright
31  *    notice, this list of conditions and the following disclaimer in the
32  *    documentation and/or other materials provided with the distribution.
33  * 3. The name of the author may not be used to endorse or promote products
34  *    derived from this software without specific prior written permission.
35  *
36  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
37  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
40  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
41  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
42  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
43  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
44  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
46  * SUCH DAMAGE.
47  */
48 
49 /*
50  * Various Alpha OSF/1 PAL Logout error definitions.
51  */
52 
53 /*
54  * Information gathered from: DEC documentation
55  */
56 
57 /*
58  * Avanti (AlphaStation 200 and 400) Specific PALcode Exception Logout
59  * Area Definitions
60  */
61 
62 /*
63  * Avanti Specific common logout frame header.
64  * *Almost* identical to the generic logout header listed in alpha_cpu.h.
65  */
66 
67 typedef struct {
68 	unsigned int	la_frame_size;		/* frame size */
69 	unsigned int	la_flags;		/* flags; see alpha_cpu.h */
70 	unsigned int	la_cpu_offset;		/* offset to CPU area */
71 	unsigned int	la_system_offset;	/* offset to system area */
72 	unsigned int	mcheck_code;		/* machine check code */
73 	unsigned int	:32;
74 } mc_hdr_avanti;
75 
76 /* Machine Check Codes */
77 
78 /* SCB 660 Fatal Machine Checks */
79 #define AVANTI_RETRY_TIMEOUT		0x201L
80 #define	AVANTI_DMA_DATA_PARITY		0x202L
81 #define AVANTI_IO_PARITY		0x203L
82 #define AVANTI_TARGET_ABORT		0x204L
83 #define AVANTI_NO_DEVICE		0x205L
84 #define AVANTI_CORRRECTABLE_MEMORY	0x206L	/* Should never occur */
85 #define AVANTI_UNCORRECTABLE_PCI_MEMORY	0x207L
86 #define AVANTI_INVALID_PT_LOOKUP	0x208L
87 #define AVANTI_MEMORY			0x209L
88 #define AVANTI_BCACHE_TAG_ADDR_PARITY	0x20AL
89 #define AVANTI_BCACHE_TAG_CTRL_PARITY	0x20BL
90 #define AVANTI_NONEXISTENT_MEMORY	0x20CL
91 #define AVANTI_IO_BUS			0x20DL
92 #define AVANTI_BCACHE_TAG_PARITY	 0x80L
93 #define AVANTI_BCACHE_TAG_CTRL_PARITY2   0x82L
94 
95 /* SCB 670 Processor Fatal Machine Checks */
96 #define AVANTI_HARD_ERROR		 0x84L
97 #define AVANTI_CORRECTABLE_ECC		 0x86L
98 #define AVANTI_NONCORRECTABLE_ECC	 0x88L
99 #define AVANTI_UNKNOWN_ERROR		 0x8AL
100 #define AVANTI_SOFT_ERROR		 0x8CL
101 #define AVANTI_BUGCHECK		 	 0x8EL
102 #define AVANTI_OS_BUGCHECK		 0x90L
103 #define AVANTI_DCACHE_FILL_PARITY 	 0x92L
104 #define AVANTI_ICACHE_FILL_PARITY	 0x94L
105 
106 typedef struct {
107 	/* Registers from the CPU */
108 	u_int64_t	paltemp[32];	/* PAL TEMP REGS.		*/
109 	u_int64_t	exc_addr;	/* Address of excepting ins.	*/
110 	u_int64_t	exc_sum;	/* Summary of arithmetic traps.	*/
111 	u_int64_t	exc_mask;	/* Exception mask.		*/
112 	u_int64_t	iccsr;
113 	u_int64_t	pal_base;	/* Base address for PALcode.	*/
114 	u_int64_t	hier;
115 	u_int64_t	hirr;
116 	u_int64_t	mm_csr;
117 	u_int64_t	dc_stat;
118 	u_int64_t	dc_addr;
119 	u_int64_t	abox_ctl;
120 	u_int64_t	biu_stat;	/* Bus Interface Unit Status.	*/
121 	u_int64_t	biu_addr;
122 	u_int64_t	biu_ctl;
123 	u_int64_t	fill_syndrome;
124 	u_int64_t	fill_addr;
125 	u_int64_t	va;
126 	u_int64_t	bc_tag;
127 
128 	/* Registers from the cache and memory controller (21071-CA) */
129 	u_int64_t	coma_gcr;	/* Error and Diag. Status.	*/
130 	u_int64_t	coma_edsr;
131 	u_int64_t	coma_ter;
132 	u_int64_t	coma_elar;
133 	u_int64_t	coma_ehar;
134 	u_int64_t	coma_ldlr;
135 	u_int64_t	coma_ldhr;
136 	u_int64_t	coma_base0;
137 	u_int64_t	coma_base1;
138 	u_int64_t	coma_base2;
139 	u_int64_t	coma_cnfg0;
140 	u_int64_t	coma_cnfg1;
141 	u_int64_t	coma_cnfg2;
142 
143 	/* Registers from the PCI bridge (21071-DA) */
144 	u_int64_t	epic_dcsr;	 /* Diag. Control and Status.	*/
145 	u_int64_t	epic_pear;
146 	u_int64_t	epic_sear;
147 	u_int64_t	epic_tbr1;
148 	u_int64_t	epic_tbr2;
149 	u_int64_t	epic_pbr1;
150 	u_int64_t	epic_pbr2;
151 	u_int64_t	epic_pmr1;
152 	u_int64_t	epic_pmr2;
153 	u_int64_t	epic_harx1;
154 	u_int64_t	epic_harx2;
155 	u_int64_t	epic_pmlt;
156 	u_int64_t	epic_tag0;
157 	u_int64_t	epic_tag1;
158 	u_int64_t	epic_tag2;
159 	u_int64_t	epic_tag3;
160 	u_int64_t	epic_tag4;
161 	u_int64_t	epic_tag5;
162 	u_int64_t	epic_tag6;
163 	u_int64_t	epic_tag7;
164 	u_int64_t	epic_data0;
165 	u_int64_t	epic_data1;
166 	u_int64_t	epic_data2;
167 	u_int64_t	epic_data3;
168 	u_int64_t	epic_data4;
169 	u_int64_t	epic_data5;
170 	u_int64_t	epic_data6;
171 	u_int64_t	epic_data7;
172 } mc_uc_avanti;
173 
174 /*
175  * Information gathered from: OSF/1 header files.
176  */
177 
178 
179 /*
180  * EV5 Specific OSF/1 Pal Code Exception Logout Area Definitions
181  * (inspired from OSF/1 Header files).
182  */
183 
184 /*
185  * EV5 Specific common logout frame header.
186  * *Almost* identical to the generic logout header listed in alpha_cpu.h.
187  */
188 
189 typedef struct {
190 	unsigned int	la_frame_size;		/* frame size */
191 	unsigned int	la_flags;		/* flags; see alpha_cpu.h */
192 	unsigned int	la_cpu_offset;		/* offset to CPU area */
193 	unsigned int	la_system_offset;	/* offset to system area */
194 	unsigned long	mcheck_code;		/* machine check code */
195 } mc_hdr_ev5;
196 
197 /* Machine Check Codes */
198 #define	EV5_CORRECTED		0x86L
199 #define	SYSTEM_CORRECTED	0x201L
200 
201 /*
202  * EV5 Specific Machine Check logout frame for uncorrectable errors.
203  * This is used to log uncorrectable errors such as double bit ECC errors.
204  *
205  * This typically resides in the CPU offset area of the logout frame.
206  */
207 
208 typedef struct {
209 	u_int64_t	shadow[8];	/* Shadow reg. 8-14, 25		*/
210 	u_int64_t	paltemp[24];	/* PAL TEMP REGS.		*/
211 	u_int64_t	exc_addr;	/* Address of excepting ins.	*/
212 	u_int64_t	exc_sum;	/* Summary of arithmetic traps.	*/
213 	u_int64_t	exc_mask;	/* Exception mask.		*/
214 	u_int64_t	pal_base;	/* Base address for PALcode.	*/
215 	u_int64_t	isr;		/* Interrupt Status Reg.	*/
216 	u_int64_t	icsr;		/* CURRENT SETUP OF EV5 IBOX	*/
217 	u_int64_t	ic_perr_stat;	/*
218 					 * I-CACHE Reg:
219 					 *	<13> IBOX Timeout
220 					 *	<12> TAG parity
221 					 *	<11> Data parity
222 					 */
223 	u_int64_t	dc_perr_stat;	/* D-CACHE error Reg:
224 					 * Bits set to 1:
225 					 *  <2> Data error in bank 0
226 					 *  <3> Data error in bank 1
227 					 *  <4> Tag error in bank 0
228 					 *  <5> Tag error in bank 1
229 					 */
230 	u_int64_t	va;		/* Effective VA of fault or miss. */
231 	u_int64_t	mm_stat;	/*
232 					 * Holds the reason for D-stream
233 					 * fault or D-cache parity errors
234 					 */
235 	u_int64_t	sc_addr;	/*
236 					 * Address that was being accessed
237 					 * when EV5 detected Secondary cache
238 					 * failure.
239 					 */
240 	u_int64_t	sc_stat;	/*
241 					 * Helps determine if the error was
242 					 * TAG/Data parity(Secondary Cache)
243 					 */
244 	u_int64_t	bc_tag_addr;	/* Contents of EV5 BC_TAG_ADDR	  */
245 	u_int64_t	ei_addr;	/*
246 					 * Physical address of any transfer
247 					 * that is logged in the EV5 EI_STAT
248 					 */
249 	u_int64_t	fill_syndrome;	/* For correcting ECC errors.	  */
250 	u_int64_t	ei_stat;	/*
251 					 * Helps identify reason of any
252 					 * processor uncorrectable error
253 					 * at its external interface.
254 					 */
255 	u_int64_t	ld_lock;	/* Contents of EV5 LD_LOCK register*/
256 } mc_uc_ev5;
257 #define	EV5_IC_PERR_IBOXTMO	0x2000
258 
259 /*
260  * EV5 Specific Machine Check logout frame for correctable errors.
261  *
262  * This is used to log correctable errors such as Single bit ECC errors.
263  */
264 typedef struct {
265 	u_int64_t	ei_addr;	/*
266 					 * Physical address of any transfer
267 					 * that is logged in the EV5 EI_STAT
268 					 */
269 	u_int64_t	fill_syndrome;	/* For correcting ECC errors.	  */
270 	u_int64_t	ei_stat;	/*
271 					 * Helps identify reason of any
272 					 * processor uncorrectable error
273 					 * at its external interface.
274 					 */
275 	u_int64_t	isr;		/* Interrupt Status Reg. 	  */
276 } mc_cc_ev5;
277 
278 /*
279  * Information gathered from: AlphaServer ES40 Service Guide
280  */
281 
282 /*
283  * EV6 Specific OSF/1 Pal Code Exception Logout Area Definitions
284  */
285 
286 /*
287  * EV6 Specific common logout frame header.
288  * *Almost* identical to the generic logout header listed in alpha_cpu.h.
289  */
290 
291 typedef struct {
292 	unsigned int	la_frame_size;		/* frame size */
293 	unsigned int	la_flags;		/* flags; see alpha_cpu.h */
294 	unsigned int	la_cpu_offset;		/* offset to CPU area */
295 	unsigned int	la_system_offset;	/* offset to system area */
296 	unsigned int	mcheck_code;		/* machine check code */
297 	unsigned int	mcheck_rev;		/* frame revision */
298 #define	MC_EV6_FRAME_REVISION		1
299 } mc_hdr_ev6;
300 
301 /*
302  * EV6 Specific Machine Check processor area.
303  */
304 
305 typedef struct {
306 	uint64_t	i_stat;
307 	uint64_t	dc_stat;
308 	uint64_t	c_addr;
309 	uint64_t	c_syndrome_0;
310 	uint64_t	c_syndrome_1;
311 	uint64_t	c_stat;
312 	uint64_t	c_sts;
313 	uint64_t	mm_stat;
314 	/* the following fields only exist for uncorrectable errors */
315 	uint64_t	exc_addr;
316 	uint64_t	ier_cm;
317 	uint64_t	isum;
318 	uint64_t	reserved0;
319 	uint64_t	pal_base;
320 	uint64_t	i_ctl;
321 	uint64_t	pctx;
322 	uint64_t	reserved1;
323 	uint64_t	reserved2;
324 } mc_cpu_ev6;
325 
326 /* C_STAT bits */
327 #define	EV6_C_STAT_MASK					0x1f
328 #define	EV6_C_STAT_NO_ERROR				0x00
329 #define	EV6_C_STAT_SNGL_BC_TAG_PERR			0x01
330 #define	EV6_C_STAT_SNGL_DC_DUPLICATE_TAG_PERR		0x02
331 #define	EV6_C_STAT_SNGL_DSTREAM_MEM_ECC_ERR		0x03
332 #define	EV6_C_STAT_SNGL_DSTREAM_BC_ECC_ERR		0x04
333 #define	EV6_C_STAT_SNGL_DSTREAM_DC_ECC_ERR		0x05
334 #define	EV6_C_STAT_SNGL_BC_PROBE_HIT_ERR		0x06
335 #define	EV6_C_STAT_SNGL_BC_PROBE_HIT_ERR2		0x07
336 #define	EV6_C_STAT_SNGL_ISTREAM_MEM_ECC_ERR		0x0b
337 #define	EV6_C_STAT_SNGL_ISTREAM_BC_ECC_ERR		0x0c
338 #define	EV6_C_STAT_DBL_DSTREAM_MEM_ECC_ERR		0x13
339 #define	EV6_C_STAT_DBL_DSTREAM_BC_ECC_ERR		0x14
340 #define	EV6_C_STAT_DBL_ISTREAM_MEM_ECC_ERR		0x1b
341 #define	EV6_C_STAT_DBL_ISTREAM_BC_ECC_ERR		0x1c
342 
343 /* C_STS bits */
344 #define	EV6_C_STS_MASK					0x0f
345 #define	EV6_C_STS_PARITY				0x08
346 #define	EV6_C_STS_VALID					0x04
347 #define	EV6_C_STS_DIRTY					0x02
348 #define	EV6_C_STS_SHARED				0x01
349 
350 /* DC_STAT */
351 #define	EV6_DC_STAT_MASK				0x1f
352 #define	EV6_DC_STAT_PIPELINE_0_ERROR			0x01
353 #define	EV6_DC_STAT_PIPELINE_1_ERROR			0x02
354 #define	EV6_DC_STAT_STORE_DATA_ECC_ERROR		0x04
355 #define	EV6_DC_STAT_LOAD_DATA_ECC_ERROR			0x08
356 #define	EV6_DC_STAT_STORE_DATA_ECC_ERROR_REPEATED	0x10
357 
358 /* MM_STAT */
359 #define	EV6_MM_STAT_MASK				0x03ff
360 #define	EV6_MM_STAT_WRITE				0x0001
361 #define	EV6_MM_STAT_ACCESS_VIOLATION			0x0002
362 #define	EV6_MM_STAT_FOR_SET				0x0004
363 #define	EV6_MM_STAT_FOW_SET				0x0008
364 #define	EV6_MM_STAT_OPCODE_MASK				0x02f0
365 #define	EV6_MM_STAT_DCACHE_CORRECTABLE_ERROR		0x0300
366 
367 /*
368  * EV6 Specific Machine Check system area.
369  */
370 
371 typedef struct {
372 	uint64_t	flags;
373 	uint64_t	c_dir;
374 	uint64_t	c_misc;
375 	uint64_t	p0_perror;
376 	uint64_t	p1_perror;
377 } mc_sys_ev6;
378 
379 /*
380  * EV6 Environmental Error logout frame.
381  */
382 
383 typedef struct {
384 	uint64_t	flags;
385 	uint64_t	c_dir;
386 	uint64_t	smir;
387 	uint64_t	cpuir;
388 	uint64_t	psir;
389 	uint64_t	lm78_isr;
390 	uint64_t	doors;
391 	uint64_t	temp_warning;
392 	uint64_t	fan_control;
393 	uint64_t	fatal_power_down;
394 	uint64_t	reserved;
395 } mc_env_ev6;
396 
397 /* SMIR */
398 #define	EV6_ENV_SMIR_RESET				0x80
399 #define	EV6_ENV_SMIR_PCI1_RESET				0x40
400 #define	EV6_ENV_SMIR_PCI0_RESET				0x20
401 #define	EV6_ENV_SMIR_OVERTEMP				0x10
402 #define	EV6_ENV_SMIR_DC_FAILURE				0x04
403 #define	EV6_ENV_SMIR_RMC_HALT				0x02
404 #define	EV6_ENV_SMIR_PSU_FAILURE			0x01
405 
406 /* CPUIR */
407 #define	EV6_ENV_CPUIR_CPU_FAIL(cpuno)			((cpuno) << 4)
408 #define	EV6_ENV_CPUIR_CPU_ENABLE(cpuno)			((cpuno) << 0)
409 
410 /* PSIR */
411 #define	EV6_ENV_PSIR_PSU_FAIL(psuno)			((psuno) << 4)
412 #define	EV6_ENV_PSIR_PSU_ENABLE(psuno)			((psuno) << 0)
413 
414 /* LM78_ISR */
415 #define	EV6_ENV_LM78_PSU_AC_HIGH_LIMIT			0x0000800000000000
416 #define	EV6_ENV_LM78_PSU_AC_LOW_LIMIT			0x0000400000000000
417 #define	EV6_ENV_LM78_PSU_OVERTEMP			0x0000200000000000
418 #define	EV6_ENV_LM78_PSU_12V_OVERAMP			0x0000100000000000
419 #define	EV6_ENV_LM78_PSU_5V_OVERAMP			0x0000080000000000
420 #define	EV6_ENV_LM78_PSU_3_3V_OVERAMP			0x0000040000000000
421 #define	EV6_ENV_LM78_PSU_NUMBER_MASK			0x0000030000000000
422 #define	EV6_ENV_LM78_PSU_NUMBER_SHIFT			40
423 #define	EV6_ENV_LM78_FAN6_FAILURE			0x0000008000000000
424 #define	EV6_ENV_LM78_FAN3_FAILURE			0x0000004000000000
425 #define	EV6_ENV_LM78_ZONE2_OVERTEMP			0x0000001000000000
426 #define	EV6_ENV_LM78_CPU3_VIO_OOT			0x0000000800000000
427 #define	EV6_ENV_LM78_CPU3_VCORE_OOT			0x0000000400000000
428 #define	EV6_ENV_LM78_CPU2_VIO_OOT			0x0000000200000000
429 #define	EV6_ENV_LM78_CPU2_VCORE_OOT			0x0000000100000000
430 #define	EV6_ENV_LM78_FAN5_FAILURE			0x0000000000800000
431 #define	EV6_ENV_LM78_FAN4_FAILURE			0x0000000000400000
432 #define	EV6_ENV_LM78_ZONE1_OVERTEMP			0x0000000000100000
433 #define	EV6_ENV_LM78_CPU1_VIO_OOT			0x0000000000080000
434 #define	EV6_ENV_LM78_CPU1_VCORE_OOT			0x0000000000040000
435 #define	EV6_ENV_LM78_CPU0_VIO_OOT			0x0000000000020000
436 #define	EV6_ENV_LM78_CPU0_VCORE_OOT			0x0000000000010000
437 #define	EV6_ENV_LM78_PSU_MINUS12V_OOT			0x0000000000000400
438 #define	EV6_ENV_LM78_CTERM_OOT				0x0000000000000100
439 #define	EV6_ENV_LM78_FAN2_FAILURE			0x0000000000000080
440 #define	EV6_ENV_LM78_FAN1_FAILURE			0x0000000000000040
441 #define	EV6_ENV_LM78_CPU_OVERTEMP			0x0000000000000020
442 #define	EV6_ENV_LM78_ZONA0_OVERTEMP			0x0000000000000010
443 #define	EV6_ENV_LM78_VTERM_OOT				0x0000000000000008
444 #define	EV6_ENV_LM78_PSU_12V_OOT			0x0000000000000004
445 #define	EV6_ENV_LM78_PSU_5V_OOT				0x0000000000000002
446 #define	EV6_ENV_LM78_PSU_3_3V_OOT			0x0000000000000001
447 
448 /* Doors */
449 #define	EV6_ENV_DOORS_PCI_CLOSED			0x80
450 #define	EV6_ENV_DOORS_FAN_CLOSED			0x40
451 #define	EV6_ENV_DOORS_CPU_CLOSED			0x20
452 #define	EV6_ENV_DOORS_PCI_OPEN				0x08
453 #define	EV6_ENV_DOORS_FAN_OPEN				0x04
454 #define	EV6_ENV_DOORS_CPU_OPEN				0x02
455 
456 /* System Temperature Warning (sticky?) */
457 #define	EV6_ENV_STW_ZONE2				0x40
458 #define	EV6_ENV_STW_ZONE1				0x20
459 #define	EV6_ENV_STW_ZONE0				0x10
460 #define	EV6_ENV_STW_CPU3				0x08
461 #define	EV6_ENV_STW_CPU2				0x04
462 #define	EV6_ENV_STW_CPU1				0x02
463 #define	EV6_ENV_STW_CPU0				0x01
464 
465 /* System Fan Control Fault */
466 #define	EV6_ENV_SFCF_FAN1234_LOW_SPEED			0x0800
467 #define	EV6_ENV_SFCF_FAN1234_HIGH_SPEED			0x0400
468 #define	EV6_ENV_SFCF_FAN56_LOW_SPEED			0x0200
469 #define	EV6_ENV_SFCF_FAN56_HIGH_SPEED			0x0100
470 #define	EV6_ENV_SFCF_FAN6_NONRESPONSIVE			0x0020
471 #define	EV6_ENV_SFCF_FAN5_NONRESPONSIVE			0x0010
472 #define	EV6_ENV_SFCF_FAN4_NONRESPONSIVE			0x0008
473 #define	EV6_ENV_SFCF_FAN3_NONRESPONSIVE			0x0004
474 #define	EV6_ENV_SFCF_FAN2_NONRESPONSIVE			0x0002
475 #define	EV6_ENV_SFCF_FAN1_NONRESPONSIVE			0x0001
476