1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Midhunchandra Kodiyath <midhunchandra.kodiyath@intel.com>
26 *
27 */
28
29 #include "media_drv_hw.h"
30 #include "media_drv_hwcmds.h"
31 #include "media_drv_defines.h"
32 //#define DEBUG
33 STATUS
mediadrv_gen_pipe_ctrl_cmd(MEDIA_BATCH_BUFFER * batch,PIPE_CONTROL_PARAMS * params)34 mediadrv_gen_pipe_ctrl_cmd (MEDIA_BATCH_BUFFER * batch,
35 PIPE_CONTROL_PARAMS * params)
36 {
37 STATUS status = SUCCESS;
38 BEGIN_BATCH (batch, 5);
39 OUT_BATCH (batch, CMD_PIPE_CONTROL | CMD_PIPE_CONTROL_DWORD_LEN);
40
41 switch (params->flush_mode)
42 {
43 case FLUSH_WRITE_CACHE:
44 OUT_BATCH (batch,
45 CMD_PIPE_CONTROL_DEST_ADDR_TYPE | CMD_PIPE_CONTROL_CS_STALL |
46 CMD_PIPE_CONTROL_RT_FLUSH_ENABLE |
47 CMD_PIPE_CONTROL_FLUSH_ENABLE | CMD_PIPE_CONTROL_DC_FLUSH |
48 CMD_PIPE_CONTROL_NOWRITE);
49 OUT_BATCH (batch, 0); /* write address */
50 break;
51
52 case FLUSH_READ_CACHE:
53 OUT_BATCH (batch,
54 CMD_PIPE_CONTROL_DEST_ADDR_TYPE | CMD_PIPE_CONTROL_NOWRITE |
55 CMD_PIPE_CONTROL_INSTR_CI_ENABLE |
56 CMD_PIPE_CONTROL_FLUSH_ENABLE | CMD_PIPE_CONTROL_VF_CI_ENABLE
57 | CMD_PIPE_CONTROL_CONSTANT_CI_ENABLE |
58 CMD_PIPE_CONTROL_STATE_CI_ENABLE);
59 OUT_BATCH (batch, 0); /* write address */
60 break;
61
62 default:
63 #ifdef DEBUG
64 printf ("params->status_buffer.bo=%x\n", params->status_buffer.bo);
65 #endif
66 if (params->status_buffer.bo)
67 {
68 OUT_BATCH (batch, CMD_PIPE_CONTROL_CS_STALL | CMD_PIPE_CONTROL_WRITE_QWORD | /*CMD_PIPE_CONTROL_DEST_ADDR_TYPE | */
69 CMD_PIPE_CONTROL_FLUSH_ENABLE);
70 OUT_RELOC (batch, params->status_buffer.bo,
71 I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
72
73 }
74 else
75 {
76
77 OUT_BATCH (batch, CMD_PIPE_CONTROL_FLUSH_ENABLE);
78 OUT_BATCH (batch, 0); /* write address */
79
80 }
81 break;
82 }
83 /*immediate_data needs to set before calling this function if Post Sync Operation is 1h */
84 /*in case params->status_buffer!=NULL immediate_data is set to 1 */
85 OUT_BATCH (batch, params->immediate_data); /* write data */
86 OUT_BATCH (batch, 0);
87 ADVANCE_BATCH (batch);
88 return status;
89 }
90
91 STATUS
mediadrv_gen_pipeline_select_cmd(MEDIA_BATCH_BUFFER * batch)92 mediadrv_gen_pipeline_select_cmd (MEDIA_BATCH_BUFFER * batch)
93 {
94 STATUS status = SUCCESS;
95 BEGIN_BATCH (batch, 1);
96 OUT_BATCH (batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
97 ADVANCE_BATCH (batch);
98 return status;
99 }
100
101 STATUS
mediadrv_gen_state_base_address_cmd(MEDIA_BATCH_BUFFER * batch,STATE_BASE_ADDR_PARAMS * params)102 mediadrv_gen_state_base_address_cmd (MEDIA_BATCH_BUFFER * batch,
103 STATE_BASE_ADDR_PARAMS * params)
104 {
105 STATUS status = SUCCESS;
106 BEGIN_BATCH (batch, CMD_STATE_BASE_ADDRESS_LEN);
107 OUT_BATCH (batch, (CMD_STATE_BASE_ADDRESS | (CMD_STATE_BASE_ADDRESS_LEN-2)));
108 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY*/); //General State Base Address
109 /*DW4 Surface state base address */
110 if (params->surface_state.bo) {
111 OUT_RELOC (batch, params->surface_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
112 }
113 else
114 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY */ );
115 /*DW6. Dynamic state base address */
116 if (params->dynamic_state.bo)
117 OUT_RELOC (batch, params->dynamic_state.bo,
118 I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
119 0, BASE_ADDRESS_MODIFY);
120 else
121 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY*/);
122 /*DW8. Indirect Object base address */
123 if (params->indirect_object.bo)
124 OUT_RELOC (batch, params->indirect_object.bo,
125 I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
126 else
127 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY*/);
128 /*DW10. Instruct base address */
129 if (params->instruction_buffer.bo)
130 OUT_RELOC (batch, params->instruction_buffer.bo,
131 I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
132 else
133 OUT_BATCH (batch, 0 | BASE_ADDRESS_MODIFY);
134 /* DW12. Size limitation */
135 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY */ ); //General State Access Upper Bound
136 OUT_BATCH (batch,0xFFFFF000 | BASE_ADDRESS_MODIFY); //Dynamic State Access Upper Bound
137 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY */ ); //Indirect Object Access Upper Bound
138 OUT_BATCH (batch,0xFFFFF000 | BASE_ADDRESS_MODIFY); //Instruction Access Upper Bound
139 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY*/);
140 OUT_BATCH (batch, 0 /*| BASE_ADDRESS_MODIFY*/);
141 ADVANCE_BATCH (batch);
142 return status;
143 }
144
145 STATUS
mediadrv_gen_media_vfe_state_cmd(MEDIA_BATCH_BUFFER * batch,VFE_STATE_PARAMS * params)146 mediadrv_gen_media_vfe_state_cmd (MEDIA_BATCH_BUFFER * batch,
147 VFE_STATE_PARAMS * params)
148 {
149 STATUS status = SUCCESS;
150 BEGIN_BATCH (batch, CMD_MEDIA_VFE_STATE_LEN);
151 OUT_BATCH (batch, CMD_MEDIA_VFE_STATE | (CMD_MEDIA_VFE_STATE_LEN - 2));
152 OUT_BATCH (batch, 0); /* Scratch Space Base Pointer and Space */
153 OUT_BATCH (batch, params->max_num_threads << 16 | /* Maximum Number of Threads */
154 params->num_urb_entries << 8 | /* Number of URB Entries */
155 params->gpgpu_mode << 2); /* MEDIA Mode */
156 OUT_BATCH (batch, 0); /* Debug: Object ID */
157 OUT_BATCH (batch, params->urb_entry_size << 16 | /* URB Entry Allocation Size */
158 params->curbe_allocation_size); /* CURBE Allocation Size */
159 /* the vfe_desc5/6/7 will decide whether the scoreboard is used. */
160 if (params->scoreboard_enable)
161 {
162 OUT_BATCH (batch, params->scoreboardDW5);
163 OUT_BATCH (batch, params->scoreboardDW6);
164 OUT_BATCH (batch, params->scoreboardDW7);
165 }
166 else
167 {
168 OUT_BATCH (batch, 0);
169 OUT_BATCH (batch, 0);
170 OUT_BATCH (batch, 0);
171 }
172 ADVANCE_BATCH (batch);
173 return status;
174
175 }
176
177 STATUS
mediadrv_gen_media_curbe_load_cmd(MEDIA_BATCH_BUFFER * batch,CURBE_LOAD_PARAMS * params)178 mediadrv_gen_media_curbe_load_cmd (MEDIA_BATCH_BUFFER * batch,
179 CURBE_LOAD_PARAMS * params)
180 {
181 STATUS status = SUCCESS;
182 BEGIN_BATCH (batch, 4);
183 OUT_BATCH (batch, CMD_MEDIA_CURBE_LOAD | (4 - 2));
184 OUT_BATCH (batch, 0);
185 OUT_BATCH (batch, params->curbe_size);
186 OUT_BATCH (batch, params->curbe_offset);
187 ADVANCE_BATCH (batch);
188 return status;
189 }
190
191 STATUS
mediadrv_gen_media_id_load_cmd(MEDIA_BATCH_BUFFER * batch,ID_LOAD_PARAMS * params)192 mediadrv_gen_media_id_load_cmd (MEDIA_BATCH_BUFFER * batch,
193 ID_LOAD_PARAMS * params)
194 {
195 STATUS status = SUCCESS;
196 BEGIN_BATCH (batch, 4);
197 OUT_BATCH (batch, CMD_MEDIA_INTERFACE_LOAD | (4 - 2));
198 OUT_BATCH (batch, 0);
199 OUT_BATCH (batch, params->idrt_size);
200 OUT_BATCH (batch, params->idrt_offset);
201 ADVANCE_BATCH (batch);
202 return status;
203 }
204
205 STATUS
mediadrv_media_mi_set_predicate_cmd(MEDIA_BATCH_BUFFER * batch,MI_SET_PREDICATE_PARAMS * params)206 mediadrv_media_mi_set_predicate_cmd (MEDIA_BATCH_BUFFER * batch,
207 MI_SET_PREDICATE_PARAMS * params)
208 {
209 STATUS status = SUCCESS;
210 BEGIN_BATCH (batch, 1);
211 OUT_BATCH (batch, CMD_MI_SET_PREDICATE | params->predicate_en);
212 ADVANCE_BATCH (batch);
213 return status;
214 }
215
216 STATUS
media_object_walker_cmd(MEDIA_BATCH_BUFFER * batch,MEDIA_OBJ_WALKER_PARAMS * params)217 media_object_walker_cmd (MEDIA_BATCH_BUFFER * batch,
218 MEDIA_OBJ_WALKER_PARAMS * params)
219 {
220 STATUS status = SUCCESS;
221 UINT dw5_cmd = 0, dw10_cmd = 0, dw11_cmd = 0, dw12_cmd = 0,use_scoreboard=0;
222 UINT mode = params->walker_mode;
223 UINT repel = (mode == SINGLE_MODE) ? 1 : 0;
224 UINT dual_mode = (mode == DUAL_MODE) ? 1 : 0;
225 UINT quad_mode = (mode == QUAD_MODE) ? 1 : 0;
226 BEGIN_BATCH (batch, CMD_MEDIA_OBJECT_WALKER_LEN /*17 */ );
227 if (params->mb_enc_iframe_dist_en || params->me_in_use)
228 {
229 use_scoreboard=0;
230 dw5_cmd = 0;
231 dw10_cmd = (params->frm_w_in_mb - 1); //do we really need to set this for HSW
232 dw11_cmd = dw11_cmd | 1 << 16;
233 dw12_cmd = dw12_cmd | 0x1;
234 }
235 else
236 {
237 use_scoreboard=params->use_scoreboard;
238 dw10_cmd = 0;
239 if (params->hybrid_pak2_pattern_enabled_45_deg)
240 {
241
242 dw11_cmd = 0x1;
243 dw12_cmd = dw12_cmd | 1 << 16 | 0x3FF;
244 dw5_cmd = 0x07;
245
246 }
247 else if ((params->pic_coding_type == I_FRM ||
248 (params->pic_coding_type == B_FRM &&
249 !params->direct_spatial_mv_pred)) &&
250 !params->force_26_degree)
251 {
252 dw5_cmd = 0x3;
253 dw11_cmd = 0x1;
254 dw12_cmd = dw12_cmd | 1 << 16 | 0x3FF;
255
256 }
257 else
258 {
259 dw5_cmd = 0x0F;
260 dw11_cmd = 0x1;
261 dw12_cmd = dw12_cmd | 1 << 16 | 0x3FE;
262 }
263
264 }
265 OUT_BATCH (batch,CMD_MEDIA_OBJECT_WALKER | (CMD_MEDIA_OBJECT_WALKER_LEN - 2));
266 OUT_BATCH (batch, 0);
267 OUT_BATCH (batch,use_scoreboard << 21);
268 OUT_BATCH (batch, 0);
269 OUT_BATCH (batch, 0);
270 OUT_BATCH (batch, dw5_cmd);
271 OUT_BATCH (batch, ((dual_mode << 31) | (repel << 30) | (quad_mode << 29)));
272 OUT_BATCH (batch, ((0x3FF << 16) | 0x3FF));
273 OUT_BATCH (batch, ((params->frmfield_h_in_mb << 16) | params->frm_w_in_mb));
274 OUT_BATCH (batch, 0);
275 OUT_BATCH (batch, dw10_cmd);
276 OUT_BATCH (batch, dw11_cmd);
277 OUT_BATCH (batch, dw12_cmd);
278 OUT_BATCH (batch, ((params->frmfield_h_in_mb << 16) | params->frm_w_in_mb));
279 OUT_BATCH (batch, 0);
280 OUT_BATCH (batch, (0 | params->frm_w_in_mb));
281 OUT_BATCH (batch, (0 | (params->frmfield_h_in_mb << 16)));
282 ADVANCE_BATCH (batch);
283 return status;
284 }
285
286 STATUS
media_object_cmd(MEDIA_BATCH_BUFFER * batch,MEDIA_OBJECT_PARAMS * params)287 media_object_cmd (MEDIA_BATCH_BUFFER *batch,
288 MEDIA_OBJECT_PARAMS *params)
289 {
290 STATUS status = SUCCESS;
291
292 BEGIN_BATCH (batch, CMD_MEDIA_OBJECT_LEN);
293 OUT_BATCH (batch, CMD_MEDIA_OBJECT | (CMD_MEDIA_OBJECT_LEN - 2));
294 OUT_BATCH (batch, params->interface_offset);
295 OUT_BATCH (batch, 0);
296 OUT_BATCH (batch, 0);
297 OUT_BATCH (batch, 0);
298 OUT_BATCH (batch, 0);
299 ADVANCE_BATCH (batch);
300
301 return status;
302 }
303
304 STATUS
mediadrv_mi_store_data_imm_cmd(MEDIA_BATCH_BUFFER * batch,MI_STORE_DATA_IMM_PARAMS * params)305 mediadrv_mi_store_data_imm_cmd (MEDIA_BATCH_BUFFER * batch,
306 MI_STORE_DATA_IMM_PARAMS * params)
307 {
308 STATUS status = SUCCESS;
309 BEGIN_BATCH (batch, 4);
310 OUT_BATCH (batch, CMD_MI_STORE_DATA_IMM | 0x2);
311 OUT_BATCH (batch, 0);
312 OUT_RELOC (batch, params->status_buffer.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
313 0);
314
315 OUT_BATCH (batch, params->value);
316 ADVANCE_BATCH (batch);
317 return status;
318 }
319
320 STATUS
mediadrv_set_curbe_scaling(MEDIA_GPE_CTX * gpe_context,SCALING_CURBE_PARAMS * params)321 mediadrv_set_curbe_scaling (MEDIA_GPE_CTX * gpe_context,
322 SCALING_CURBE_PARAMS * params)
323 {
324 STATUS status = SUCCESS;
325 CURBE_SCALING_DATA *cmd;
326 dri_bo_map (gpe_context->dynamic_state.res.bo, 1);
327 MEDIA_DRV_ASSERT (gpe_context->dynamic_state.res.bo->virtual);
328 cmd = (CURBE_SCALING_DATA *) gpe_context->dynamic_state.res.bo->virtual +
329 gpe_context->curbe_offset;
330 cmd->input_pic_height = params->input_pic_height;
331 cmd->input_pic_width = params->input_pic_width;
332 cmd->src_planar_y = SCALE_SRC_Y;
333 cmd->dest_planar_y = SCALE_DST_Y;
334
335 dri_bo_unmap (gpe_context->dynamic_state.res.bo);
336
337 return status;
338 }
339