1 /*-
2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_rss.h"
28 #include "opt_ratelimit.h"
29
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <linux/hardirq.h>
39 #include <dev/mlx5/driver.h>
40 #include <dev/mlx5/cq.h>
41 #include <dev/mlx5/qp.h>
42 #include <dev/mlx5/srq.h>
43 #include <dev/mlx5/mpfs.h>
44 #include <dev/mlx5/vport.h>
45 #include <linux/delay.h>
46 #include <dev/mlx5/mlx5_ifc.h>
47 #include <dev/mlx5/mlx5_fpga/core.h>
48 #include <dev/mlx5/mlx5_lib/mlx5.h>
49 #include <dev/mlx5/mlx5_core/mlx5_core.h>
50 #include <dev/mlx5/mlx5_core/eswitch.h>
51 #include <dev/mlx5/mlx5_core/fs_core.h>
52 #include <dev/mlx5/mlx5_core/diag_cnt.h>
53 #ifdef PCI_IOV
54 #include <sys/nv.h>
55 #include <sys/socket.h>
56 #include <dev/pci/pci_iov.h>
57 #include <sys/iov_schema.h>
58 #include <sys/iov.h>
59 #include <net/if.h>
60 #include <net/if_vlan_var.h>
61 #endif
62
63 static const char mlx5_version[] = "Mellanox Core driver "
64 DRIVER_VERSION " (" DRIVER_RELDATE ")";
65 MODULE_DESCRIPTION("Mellanox ConnectX-4 and onwards core driver");
66 MODULE_LICENSE("Dual BSD/GPL");
67 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
68 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
69 MODULE_DEPEND(mlx5, firmware, 1, 1, 1);
70 MODULE_VERSION(mlx5, 1);
71
72 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
73 "mlx5 hardware controls");
74
75 int mlx5_core_debug_mask;
76 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
77 &mlx5_core_debug_mask, 0,
78 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
79
80 #define MLX5_DEFAULT_PROF 2
81 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
82 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
83 &mlx5_prof_sel, 0,
84 "profile selector. Valid range 0 - 2");
85
86 static int mlx5_fast_unload_enabled = 1;
87 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
88 &mlx5_fast_unload_enabled, 0,
89 "Set to enable fast unload. Clear to disable.");
90
91 static int mlx5_core_comp_eq_size = 1024;
92 SYSCTL_INT(_hw_mlx5, OID_AUTO, comp_eq_size, CTLFLAG_RDTUN | CTLFLAG_MPSAFE,
93 &mlx5_core_comp_eq_size, 0,
94 "Set default completion EQ size between 1024 and 16384 inclusivly. Value should be power of two.");
95
96 static LIST_HEAD(intf_list);
97 static LIST_HEAD(dev_list);
98 static DEFINE_MUTEX(intf_mutex);
99
100 struct mlx5_device_context {
101 struct list_head list;
102 struct mlx5_interface *intf;
103 void *context;
104 };
105
106 enum {
107 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
108 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
109 };
110
111 static struct mlx5_profile profiles[] = {
112 [0] = {
113 .mask = 0,
114 },
115 [1] = {
116 .mask = MLX5_PROF_MASK_QP_SIZE,
117 .log_max_qp = 12,
118 },
119 [2] = {
120 .mask = MLX5_PROF_MASK_QP_SIZE |
121 MLX5_PROF_MASK_MR_CACHE,
122 .log_max_qp = 17,
123 .mr_cache[0] = {
124 .size = 500,
125 .limit = 250
126 },
127 .mr_cache[1] = {
128 .size = 500,
129 .limit = 250
130 },
131 .mr_cache[2] = {
132 .size = 500,
133 .limit = 250
134 },
135 .mr_cache[3] = {
136 .size = 500,
137 .limit = 250
138 },
139 .mr_cache[4] = {
140 .size = 500,
141 .limit = 250
142 },
143 .mr_cache[5] = {
144 .size = 500,
145 .limit = 250
146 },
147 .mr_cache[6] = {
148 .size = 500,
149 .limit = 250
150 },
151 .mr_cache[7] = {
152 .size = 500,
153 .limit = 250
154 },
155 .mr_cache[8] = {
156 .size = 500,
157 .limit = 250
158 },
159 .mr_cache[9] = {
160 .size = 500,
161 .limit = 250
162 },
163 .mr_cache[10] = {
164 .size = 500,
165 .limit = 250
166 },
167 .mr_cache[11] = {
168 .size = 500,
169 .limit = 250
170 },
171 .mr_cache[12] = {
172 .size = 64,
173 .limit = 32
174 },
175 .mr_cache[13] = {
176 .size = 32,
177 .limit = 16
178 },
179 .mr_cache[14] = {
180 .size = 16,
181 .limit = 8
182 },
183 },
184 [3] = {
185 .mask = MLX5_PROF_MASK_QP_SIZE,
186 .log_max_qp = 17,
187 },
188 };
189
190 static int
mlx5_core_get_comp_eq_size(void)191 mlx5_core_get_comp_eq_size(void)
192 {
193 int value = mlx5_core_comp_eq_size;
194
195 if (value < 1024)
196 value = 1024;
197 else if (value > 16384)
198 value = 16384;
199
200 /* make value power of two, rounded down */
201 while (value & (value - 1))
202 value &= (value - 1);
203 return (value);
204 }
205
mlx5_set_driver_version(struct mlx5_core_dev * dev)206 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
207 {
208 const size_t driver_ver_sz =
209 MLX5_FLD_SZ_BYTES(set_driver_version_in, driver_version);
210 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
211 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {};
212 char *string;
213
214 if (!MLX5_CAP_GEN(dev, driver_version))
215 return;
216
217 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
218
219 snprintf(string, driver_ver_sz, "FreeBSD,mlx5_core,%u.%u.%u," DRIVER_VERSION,
220 __FreeBSD_version / 100000, (__FreeBSD_version / 1000) % 100,
221 __FreeBSD_version % 1000);
222
223 /* Send the command */
224 MLX5_SET(set_driver_version_in, in, opcode,
225 MLX5_CMD_OP_SET_DRIVER_VERSION);
226
227 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
228 }
229
230 #ifdef PCI_IOV
231 static const char iov_mac_addr_name[] = "mac-addr";
232 static const char iov_vlan_name[] = "vlan";
233 static const char iov_node_guid_name[] = "node-guid";
234 static const char iov_port_guid_name[] = "port-guid";
235 #endif
236
set_dma_caps(struct pci_dev * pdev)237 static int set_dma_caps(struct pci_dev *pdev)
238 {
239 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
240 int err;
241
242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
243 if (err) {
244 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n");
245 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
246 if (err) {
247 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n");
248 return err;
249 }
250 }
251
252 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
253 if (err) {
254 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n");
255 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
256 if (err) {
257 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n");
258 return err;
259 }
260 }
261
262 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
263 return err;
264 }
265
mlx5_pci_read_power_status(struct mlx5_core_dev * dev,u16 * p_power,u8 * p_status)266 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev,
267 u16 *p_power, u8 *p_status)
268 {
269 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
270 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
271 int err;
272
273 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
274 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0);
275
276 *p_status = MLX5_GET(mpein_reg, out, pwr_status);
277 *p_power = MLX5_GET(mpein_reg, out, pci_power);
278 return err;
279 }
280
mlx5_pci_enable_device(struct mlx5_core_dev * dev)281 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
282 {
283 struct pci_dev *pdev = dev->pdev;
284 int err = 0;
285
286 mutex_lock(&dev->pci_status_mutex);
287 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
288 err = pci_enable_device(pdev);
289 if (!err)
290 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
291 }
292 mutex_unlock(&dev->pci_status_mutex);
293
294 return err;
295 }
296
mlx5_pci_disable_device(struct mlx5_core_dev * dev)297 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
298 {
299 struct pci_dev *pdev = dev->pdev;
300
301 mutex_lock(&dev->pci_status_mutex);
302 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
303 pci_disable_device(pdev);
304 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
305 }
306 mutex_unlock(&dev->pci_status_mutex);
307 }
308
request_bar(struct pci_dev * pdev)309 static int request_bar(struct pci_dev *pdev)
310 {
311 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
312 int err = 0;
313
314 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
315 mlx5_core_err(dev, "Missing registers BAR, aborting\n");
316 return -ENODEV;
317 }
318
319 err = pci_request_regions(pdev, DRIVER_NAME);
320 if (err)
321 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n");
322
323 return err;
324 }
325
release_bar(struct pci_dev * pdev)326 static void release_bar(struct pci_dev *pdev)
327 {
328 pci_release_regions(pdev);
329 }
330
mlx5_enable_msix(struct mlx5_core_dev * dev)331 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
332 {
333 struct mlx5_priv *priv = &dev->priv;
334 struct mlx5_eq_table *table = &priv->eq_table;
335 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
336 int limit = dev->msix_eqvec;
337 int nvec = MLX5_EQ_VEC_COMP_BASE;
338 int i;
339
340 if (limit > 0)
341 nvec += limit;
342 else
343 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
344
345 if (nvec > num_eqs)
346 nvec = num_eqs;
347 if (nvec > 256)
348 nvec = 256; /* limit of firmware API */
349 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
350 return -ENOMEM;
351
352 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
353
354 for (i = 0; i < nvec; i++)
355 priv->msix_arr[i].entry = i;
356
357 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
358 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
359 if (nvec < 0)
360 return nvec;
361
362 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
363 return 0;
364 }
365
mlx5_disable_msix(struct mlx5_core_dev * dev)366 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
367 {
368 struct mlx5_priv *priv = &dev->priv;
369
370 pci_disable_msix(dev->pdev);
371 kfree(priv->msix_arr);
372 }
373
374 struct mlx5_reg_host_endianess {
375 u8 he;
376 u8 rsvd[15];
377 };
378
379
380 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
381
382 enum {
383 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
384 MLX5_DEV_CAP_FLAG_DCT |
385 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
386 };
387
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)388 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
389 {
390 switch (size) {
391 case 128:
392 return 0;
393 case 256:
394 return 1;
395 case 512:
396 return 2;
397 case 1024:
398 return 3;
399 case 2048:
400 return 4;
401 case 4096:
402 return 5;
403 default:
404 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
405 return 0;
406 }
407 }
408
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)409 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
410 enum mlx5_cap_type cap_type,
411 enum mlx5_cap_mode cap_mode)
412 {
413 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
414 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
415 void *out, *hca_caps;
416 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
417 int err;
418
419 memset(in, 0, sizeof(in));
420 out = kzalloc(out_sz, GFP_KERNEL);
421
422 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
423 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
424 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
425 if (err) {
426 mlx5_core_warn(dev,
427 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
428 cap_type, cap_mode, err);
429 goto query_ex;
430 }
431
432 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
433
434 switch (cap_mode) {
435 case HCA_CAP_OPMOD_GET_MAX:
436 memcpy(dev->hca_caps_max[cap_type], hca_caps,
437 MLX5_UN_SZ_BYTES(hca_cap_union));
438 break;
439 case HCA_CAP_OPMOD_GET_CUR:
440 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
441 MLX5_UN_SZ_BYTES(hca_cap_union));
442 break;
443 default:
444 mlx5_core_warn(dev,
445 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
446 cap_type, cap_mode);
447 err = -EINVAL;
448 break;
449 }
450 query_ex:
451 kfree(out);
452 return err;
453 }
454
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)455 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
456 {
457 int ret;
458
459 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
460 if (ret)
461 return ret;
462
463 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
464 }
465
set_caps(struct mlx5_core_dev * dev,void * in,int in_sz)466 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
467 {
468 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
469
470 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
471
472 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
473 }
474
handle_hca_cap(struct mlx5_core_dev * dev)475 static int handle_hca_cap(struct mlx5_core_dev *dev)
476 {
477 void *set_ctx = NULL;
478 struct mlx5_profile *prof = dev->profile;
479 int err = -ENOMEM;
480 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
481 void *set_hca_cap;
482
483 set_ctx = kzalloc(set_sz, GFP_KERNEL);
484
485 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
486 if (err)
487 goto query_ex;
488
489 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
490 capability);
491 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
492 MLX5_ST_SZ_BYTES(cmd_hca_cap));
493
494 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
495 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
496 128);
497 /* we limit the size of the pkey table to 128 entries for now */
498 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
499 to_fw_pkey_sz(dev, 128));
500
501 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
502 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
503 prof->log_max_qp);
504
505 /* disable cmdif checksum */
506 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
507
508 /* Enable 4K UAR only when HCA supports it and page size is bigger
509 * than 4K.
510 */
511 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
512 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
513
514 /* enable drain sigerr */
515 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
516
517 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
518
519 err = set_caps(dev, set_ctx, set_sz);
520
521 query_ex:
522 kfree(set_ctx);
523 return err;
524 }
525
handle_hca_cap_atomic(struct mlx5_core_dev * dev)526 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
527 {
528 void *set_ctx;
529 void *set_hca_cap;
530 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
531 int req_endianness;
532 int err;
533
534 if (MLX5_CAP_GEN(dev, atomic)) {
535 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
536 if (err)
537 return err;
538 } else {
539 return 0;
540 }
541
542 req_endianness =
543 MLX5_CAP_ATOMIC(dev,
544 supported_atomic_req_8B_endianess_mode_1);
545
546 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
547 return 0;
548
549 set_ctx = kzalloc(set_sz, GFP_KERNEL);
550 if (!set_ctx)
551 return -ENOMEM;
552
553 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
554 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
555 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
556
557 /* Set requestor to host endianness */
558 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
559 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
560
561 err = set_caps(dev, set_ctx, set_sz);
562
563 kfree(set_ctx);
564 return err;
565 }
566
handle_hca_cap_2(struct mlx5_core_dev * dev)567 static int handle_hca_cap_2(struct mlx5_core_dev *dev)
568 {
569 int err;
570
571 if (MLX5_CAP_GEN_MAX(dev, hca_cap_2)) {
572 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
573 if (err)
574 return err;
575 }
576
577 return 0;
578 }
579
set_hca_ctrl(struct mlx5_core_dev * dev)580 static int set_hca_ctrl(struct mlx5_core_dev *dev)
581 {
582 struct mlx5_reg_host_endianess he_in;
583 struct mlx5_reg_host_endianess he_out;
584 int err;
585
586 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
587 !MLX5_CAP_GEN(dev, roce))
588 return 0;
589
590 memset(&he_in, 0, sizeof(he_in));
591 he_in.he = MLX5_SET_HOST_ENDIANNESS;
592 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
593 &he_out, sizeof(he_out),
594 MLX5_REG_HOST_ENDIANNESS, 0, 1);
595 return err;
596 }
597
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)598 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
599 {
600 int ret = 0;
601
602 /* Disable local_lb by default */
603 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
604 ret = mlx5_nic_vport_update_local_lb(dev, false);
605
606 return ret;
607 }
608
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)609 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
610 {
611 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
612 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
613
614 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
615 MLX5_SET(enable_hca_in, in, function_id, func_id);
616 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
617 }
618
mlx5_core_disable_hca(struct mlx5_core_dev * dev)619 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
620 {
621 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
622 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
623
624 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
625 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
626 }
627
mlx5_core_set_issi(struct mlx5_core_dev * dev)628 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
629 {
630 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
631 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
632 u32 sup_issi;
633 int err;
634
635 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
636
637 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
638 if (err) {
639 u32 syndrome;
640 u8 status;
641
642 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
643 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
644 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n");
645 return 0;
646 }
647
648 mlx5_core_err(dev, "failed to query ISSI\n");
649 return err;
650 }
651
652 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
653
654 if (sup_issi & (1 << 1)) {
655 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
656 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
657
658 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
659 MLX5_SET(set_issi_in, set_in, current_issi, 1);
660
661 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
662 if (err) {
663 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err);
664 return err;
665 }
666
667 dev->issi = 1;
668
669 return 0;
670 } else if (sup_issi & (1 << 0)) {
671 return 0;
672 }
673
674 return -ENOTSUPP;
675 }
676
677
mlx5_vector2eqn(struct mlx5_core_dev * dev,int vector,int * eqn,int * irqn)678 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
679 {
680 struct mlx5_eq_table *table = &dev->priv.eq_table;
681 struct mlx5_eq *eq;
682 int err = -ENOENT;
683
684 spin_lock(&table->lock);
685 list_for_each_entry(eq, &table->comp_eqs_list, list) {
686 if (eq->index == vector) {
687 *eqn = eq->eqn;
688 *irqn = eq->irqn;
689 err = 0;
690 break;
691 }
692 }
693 spin_unlock(&table->lock);
694
695 return err;
696 }
697 EXPORT_SYMBOL(mlx5_vector2eqn);
698
free_comp_eqs(struct mlx5_core_dev * dev)699 static void free_comp_eqs(struct mlx5_core_dev *dev)
700 {
701 struct mlx5_eq_table *table = &dev->priv.eq_table;
702 struct mlx5_eq *eq, *n;
703
704 spin_lock(&table->lock);
705 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
706 list_del(&eq->list);
707 spin_unlock(&table->lock);
708 if (mlx5_destroy_unmap_eq(dev, eq))
709 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
710 eq->eqn);
711 kfree(eq);
712 spin_lock(&table->lock);
713 }
714 spin_unlock(&table->lock);
715 }
716
alloc_comp_eqs(struct mlx5_core_dev * dev)717 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
718 {
719 struct mlx5_eq_table *table = &dev->priv.eq_table;
720 struct mlx5_eq *eq;
721 int ncomp_vec;
722 int nent;
723 int err;
724 int i;
725
726 INIT_LIST_HEAD(&table->comp_eqs_list);
727 ncomp_vec = table->num_comp_vectors;
728 nent = mlx5_core_get_comp_eq_size();
729 for (i = 0; i < ncomp_vec; i++) {
730 eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, dev->priv.numa_node);
731
732 err = mlx5_create_map_eq(dev, eq,
733 i + MLX5_EQ_VEC_COMP_BASE, nent, 0);
734 if (err) {
735 kfree(eq);
736 goto clean;
737 }
738 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
739 eq->index = i;
740 spin_lock(&table->lock);
741 list_add_tail(&eq->list, &table->comp_eqs_list);
742 spin_unlock(&table->lock);
743 }
744
745 return 0;
746
747 clean:
748 free_comp_eqs(dev);
749 return err;
750 }
751
fw_initializing(struct mlx5_core_dev * dev)752 static inline int fw_initializing(struct mlx5_core_dev *dev)
753 {
754 return ioread32be(&dev->iseg->initializing) >> 31;
755 }
756
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)757 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
758 u32 warn_time_mili)
759 {
760 int warn = jiffies + msecs_to_jiffies(warn_time_mili);
761 int end = jiffies + msecs_to_jiffies(max_wait_mili);
762 int err = 0;
763
764 MPASS(max_wait_mili > warn_time_mili);
765
766 while (fw_initializing(dev) == 1) {
767 if (time_after(jiffies, end)) {
768 err = -EBUSY;
769 break;
770 }
771 if (warn_time_mili && time_after(jiffies, warn)) {
772 mlx5_core_warn(dev,
773 "Waiting for FW initialization, timeout abort in %u s\n",
774 (unsigned)(jiffies_to_msecs(end - warn) / 1000));
775 warn = jiffies + msecs_to_jiffies(warn_time_mili);
776 }
777 msleep(FW_INIT_WAIT_MS);
778 }
779
780 if (err != 0)
781 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n",
782 ioread32be(&dev->iseg->initializing));
783
784 return err;
785 }
786
mlx5_add_device(struct mlx5_interface * intf,struct mlx5_priv * priv)787 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
788 {
789 struct mlx5_device_context *dev_ctx;
790 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
791
792 dev_ctx = kzalloc_node(sizeof(*dev_ctx), GFP_KERNEL, priv->numa_node);
793 if (!dev_ctx)
794 return;
795
796 dev_ctx->intf = intf;
797 CURVNET_SET_QUIET(vnet0);
798 dev_ctx->context = intf->add(dev);
799 CURVNET_RESTORE();
800
801 if (dev_ctx->context) {
802 spin_lock_irq(&priv->ctx_lock);
803 list_add_tail(&dev_ctx->list, &priv->ctx_list);
804 spin_unlock_irq(&priv->ctx_lock);
805 } else {
806 kfree(dev_ctx);
807 }
808 }
809
mlx5_remove_device(struct mlx5_interface * intf,struct mlx5_priv * priv)810 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
811 {
812 struct mlx5_device_context *dev_ctx;
813 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
814
815 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
816 if (dev_ctx->intf == intf) {
817 spin_lock_irq(&priv->ctx_lock);
818 list_del(&dev_ctx->list);
819 spin_unlock_irq(&priv->ctx_lock);
820
821 intf->remove(dev, dev_ctx->context);
822 kfree(dev_ctx);
823 return;
824 }
825 }
826
827 int
mlx5_register_device(struct mlx5_core_dev * dev)828 mlx5_register_device(struct mlx5_core_dev *dev)
829 {
830 struct mlx5_priv *priv = &dev->priv;
831 struct mlx5_interface *intf;
832
833 mutex_lock(&intf_mutex);
834 list_add_tail(&priv->dev_list, &dev_list);
835 list_for_each_entry(intf, &intf_list, list)
836 mlx5_add_device(intf, priv);
837 mutex_unlock(&intf_mutex);
838
839 return 0;
840 }
841
842 void
mlx5_unregister_device(struct mlx5_core_dev * dev)843 mlx5_unregister_device(struct mlx5_core_dev *dev)
844 {
845 struct mlx5_priv *priv = &dev->priv;
846 struct mlx5_interface *intf;
847
848 mutex_lock(&intf_mutex);
849 list_for_each_entry(intf, &intf_list, list)
850 mlx5_remove_device(intf, priv);
851 list_del(&priv->dev_list);
852 mutex_unlock(&intf_mutex);
853 }
854
mlx5_register_interface(struct mlx5_interface * intf)855 int mlx5_register_interface(struct mlx5_interface *intf)
856 {
857 struct mlx5_priv *priv;
858
859 if (!intf->add || !intf->remove)
860 return -EINVAL;
861
862 mutex_lock(&intf_mutex);
863 list_add_tail(&intf->list, &intf_list);
864 list_for_each_entry(priv, &dev_list, dev_list)
865 mlx5_add_device(intf, priv);
866 mutex_unlock(&intf_mutex);
867
868 return 0;
869 }
870 EXPORT_SYMBOL(mlx5_register_interface);
871
mlx5_unregister_interface(struct mlx5_interface * intf)872 void mlx5_unregister_interface(struct mlx5_interface *intf)
873 {
874 struct mlx5_priv *priv;
875
876 mutex_lock(&intf_mutex);
877 list_for_each_entry(priv, &dev_list, dev_list)
878 mlx5_remove_device(intf, priv);
879 list_del(&intf->list);
880 mutex_unlock(&intf_mutex);
881 }
882 EXPORT_SYMBOL(mlx5_unregister_interface);
883
mlx5_get_protocol_dev(struct mlx5_core_dev * mdev,int protocol)884 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
885 {
886 struct mlx5_priv *priv = &mdev->priv;
887 struct mlx5_device_context *dev_ctx;
888 unsigned long flags;
889 void *result = NULL;
890
891 spin_lock_irqsave(&priv->ctx_lock, flags);
892
893 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
894 if ((dev_ctx->intf->protocol == protocol) &&
895 dev_ctx->intf->get_dev) {
896 result = dev_ctx->intf->get_dev(dev_ctx->context);
897 break;
898 }
899
900 spin_unlock_irqrestore(&priv->ctx_lock, flags);
901
902 return result;
903 }
904 EXPORT_SYMBOL(mlx5_get_protocol_dev);
905
906 static int mlx5_auto_fw_update;
907 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
908 &mlx5_auto_fw_update, 0,
909 "Allow automatic firmware update on driver start");
910 static int
mlx5_firmware_update(struct mlx5_core_dev * dev)911 mlx5_firmware_update(struct mlx5_core_dev *dev)
912 {
913 const struct firmware *fw;
914 int err;
915
916 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update);
917 if (!mlx5_auto_fw_update)
918 return (0);
919 fw = firmware_get("mlx5fw_mfa");
920 if (fw) {
921 err = mlx5_firmware_flash(dev, fw);
922 firmware_put(fw, FIRMWARE_UNLOAD);
923 }
924 else
925 return (-ENOENT);
926
927 return err;
928 }
929
mlx5_pci_init(struct mlx5_core_dev * dev,struct mlx5_priv * priv)930 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
931 {
932 struct pci_dev *pdev = dev->pdev;
933 int err;
934
935 pdev = dev->pdev;
936 pci_set_drvdata(dev->pdev, dev);
937 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
938 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
939
940 mutex_init(&priv->pgdir_mutex);
941 INIT_LIST_HEAD(&priv->pgdir_list);
942 spin_lock_init(&priv->mkey_lock);
943
944 err = mlx5_pci_enable_device(dev);
945 if (err) {
946 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
947 goto err_dbg;
948 }
949
950 err = request_bar(pdev);
951 if (err) {
952 mlx5_core_err(dev, "error requesting BARs, aborting\n");
953 goto err_disable;
954 }
955
956 pci_set_master(pdev);
957
958 err = set_dma_caps(pdev);
959 if (err) {
960 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
961 goto err_clr_master;
962 }
963
964 dev->iseg_base = pci_resource_start(dev->pdev, 0);
965 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
966 if (!dev->iseg) {
967 err = -ENOMEM;
968 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
969 goto err_clr_master;
970 }
971
972 return 0;
973
974 err_clr_master:
975 release_bar(dev->pdev);
976 err_disable:
977 mlx5_pci_disable_device(dev);
978 err_dbg:
979 return err;
980 }
981
mlx5_pci_close(struct mlx5_core_dev * dev,struct mlx5_priv * priv)982 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
983 {
984 #ifdef PCI_IOV
985 if (MLX5_CAP_GEN(dev, eswitch_flow_table))
986 pci_iov_detach(dev->pdev->dev.bsddev);
987 #endif
988 iounmap(dev->iseg);
989 release_bar(dev->pdev);
990 mlx5_pci_disable_device(dev);
991 }
992
mlx5_init_once(struct mlx5_core_dev * dev,struct mlx5_priv * priv)993 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
994 {
995 int err;
996
997 err = mlx5_vsc_find_cap(dev);
998 if (err)
999 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n");
1000
1001 err = mlx5_query_hca_caps(dev);
1002 if (err) {
1003 mlx5_core_err(dev, "query hca failed\n");
1004 goto out;
1005 }
1006
1007 err = mlx5_query_board_id(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "query board id failed\n");
1010 goto out;
1011 }
1012
1013 err = mlx5_eq_init(dev);
1014 if (err) {
1015 mlx5_core_err(dev, "failed to initialize eq\n");
1016 goto out;
1017 }
1018
1019 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1020
1021 err = mlx5_init_cq_table(dev);
1022 if (err) {
1023 mlx5_core_err(dev, "failed to initialize cq table\n");
1024 goto err_eq_cleanup;
1025 }
1026
1027 mlx5_init_qp_table(dev);
1028 mlx5_init_srq_table(dev);
1029 mlx5_init_mr_table(dev);
1030
1031 mlx5_init_reserved_gids(dev);
1032 mlx5_fpga_init(dev);
1033
1034 #ifdef RATELIMIT
1035 err = mlx5_init_rl_table(dev);
1036 if (err) {
1037 mlx5_core_err(dev, "Failed to init rate limiting\n");
1038 goto err_tables_cleanup;
1039 }
1040 #endif
1041 return 0;
1042
1043 #ifdef RATELIMIT
1044 err_tables_cleanup:
1045 mlx5_cleanup_mr_table(dev);
1046 mlx5_cleanup_srq_table(dev);
1047 mlx5_cleanup_qp_table(dev);
1048 mlx5_cleanup_cq_table(dev);
1049 #endif
1050
1051 err_eq_cleanup:
1052 mlx5_eq_cleanup(dev);
1053
1054 out:
1055 return err;
1056 }
1057
mlx5_cleanup_once(struct mlx5_core_dev * dev)1058 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1059 {
1060 #ifdef RATELIMIT
1061 mlx5_cleanup_rl_table(dev);
1062 #endif
1063 mlx5_fpga_cleanup(dev);
1064 mlx5_cleanup_reserved_gids(dev);
1065 mlx5_cleanup_mr_table(dev);
1066 mlx5_cleanup_srq_table(dev);
1067 mlx5_cleanup_qp_table(dev);
1068 mlx5_cleanup_cq_table(dev);
1069 mlx5_eq_cleanup(dev);
1070 }
1071
mlx5_load_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool boot)1072 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1073 bool boot)
1074 {
1075 int err;
1076
1077 mutex_lock(&dev->intf_state_mutex);
1078 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1079 mlx5_core_warn(dev, "interface is up, NOP\n");
1080 goto out;
1081 }
1082
1083 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n",
1084 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
1085
1086 /*
1087 * On load removing any previous indication of internal error,
1088 * device is up
1089 */
1090 dev->state = MLX5_DEVICE_STATE_UP;
1091
1092 /* wait for firmware to accept initialization segments configurations
1093 */
1094 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI,
1095 FW_INIT_WARN_MESSAGE_INTERVAL);
1096 if (err) {
1097 dev_err(&dev->pdev->dev,
1098 "Firmware over %d MS in pre-initializing state, aborting\n",
1099 FW_PRE_INIT_TIMEOUT_MILI);
1100 goto out_err;
1101 }
1102
1103 err = mlx5_cmd_init(dev);
1104 if (err) {
1105 mlx5_core_err(dev,
1106 "Failed initializing command interface, aborting\n");
1107 goto out_err;
1108 }
1109
1110 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1111 if (err) {
1112 mlx5_core_err(dev,
1113 "Firmware over %d MS in initializing state, aborting\n",
1114 FW_INIT_TIMEOUT_MILI);
1115 goto err_cmd_cleanup;
1116 }
1117
1118 err = mlx5_core_enable_hca(dev, 0);
1119 if (err) {
1120 mlx5_core_err(dev, "enable hca failed\n");
1121 goto err_cmd_cleanup;
1122 }
1123
1124 err = mlx5_core_set_issi(dev);
1125 if (err) {
1126 mlx5_core_err(dev, "failed to set issi\n");
1127 goto err_disable_hca;
1128 }
1129
1130 err = mlx5_pagealloc_start(dev);
1131 if (err) {
1132 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n");
1133 goto err_disable_hca;
1134 }
1135
1136 err = mlx5_satisfy_startup_pages(dev, 1);
1137 if (err) {
1138 mlx5_core_err(dev, "failed to allocate boot pages\n");
1139 goto err_pagealloc_stop;
1140 }
1141
1142 err = set_hca_ctrl(dev);
1143 if (err) {
1144 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1145 goto reclaim_boot_pages;
1146 }
1147
1148 err = handle_hca_cap(dev);
1149 if (err) {
1150 mlx5_core_err(dev, "handle_hca_cap failed\n");
1151 goto reclaim_boot_pages;
1152 }
1153
1154 err = handle_hca_cap_atomic(dev);
1155 if (err) {
1156 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
1157 goto reclaim_boot_pages;
1158 }
1159
1160 err = handle_hca_cap_2(dev);
1161 if (err) {
1162 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
1163 goto reclaim_boot_pages;
1164 }
1165
1166 err = mlx5_satisfy_startup_pages(dev, 0);
1167 if (err) {
1168 mlx5_core_err(dev, "failed to allocate init pages\n");
1169 goto reclaim_boot_pages;
1170 }
1171
1172 err = mlx5_cmd_init_hca(dev);
1173 if (err) {
1174 mlx5_core_err(dev, "init hca failed\n");
1175 goto reclaim_boot_pages;
1176 }
1177
1178 mlx5_set_driver_version(dev);
1179
1180 mlx5_start_health_poll(dev);
1181
1182 if (boot && (err = mlx5_init_once(dev, priv))) {
1183 mlx5_core_err(dev, "sw objs init failed\n");
1184 goto err_stop_poll;
1185 }
1186
1187 dev->priv.uar = mlx5_get_uars_page(dev);
1188 if (IS_ERR(dev->priv.uar)) {
1189 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1190 err = PTR_ERR(dev->priv.uar);
1191 goto err_cleanup_once;
1192 }
1193
1194 err = mlx5_enable_msix(dev);
1195 if (err) {
1196 mlx5_core_err(dev, "enable msix failed\n");
1197 goto err_cleanup_uar;
1198 }
1199
1200 err = mlx5_start_eqs(dev);
1201 if (err) {
1202 mlx5_core_err(dev, "Failed to start pages and async EQs\n");
1203 goto err_disable_msix;
1204 }
1205
1206 err = alloc_comp_eqs(dev);
1207 if (err) {
1208 mlx5_core_err(dev, "Failed to alloc completion EQs\n");
1209 goto err_stop_eqs;
1210 }
1211
1212 err = mlx5_init_fs(dev);
1213 if (err) {
1214 mlx5_core_err(dev, "flow steering init %d\n", err);
1215 goto err_free_comp_eqs;
1216 }
1217
1218 err = mlx5_core_set_hca_defaults(dev);
1219 if (err) {
1220 mlx5_core_err(dev, "Failed to set HCA defaults %d\n", err);
1221 goto err_free_comp_eqs;
1222 }
1223
1224 err = mlx5_mpfs_init(dev);
1225 if (err) {
1226 mlx5_core_err(dev, "mpfs init failed %d\n", err);
1227 goto err_fs;
1228 }
1229
1230 err = mlx5_fpga_device_start(dev);
1231 if (err) {
1232 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1233 goto err_mpfs;
1234 }
1235
1236 err = mlx5_diag_cnt_init(dev);
1237 if (err) {
1238 mlx5_core_err(dev, "diag cnt init failed %d\n", err);
1239 goto err_fpga;
1240 }
1241
1242 err = mlx5_register_device(dev);
1243 if (err) {
1244 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err);
1245 goto err_diag_cnt;
1246 }
1247
1248 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1249
1250 out:
1251 mutex_unlock(&dev->intf_state_mutex);
1252 return 0;
1253
1254 err_diag_cnt:
1255 mlx5_diag_cnt_cleanup(dev);
1256
1257 err_fpga:
1258 mlx5_fpga_device_stop(dev);
1259
1260 err_mpfs:
1261 mlx5_mpfs_destroy(dev);
1262
1263 err_fs:
1264 mlx5_cleanup_fs(dev);
1265
1266 err_free_comp_eqs:
1267 free_comp_eqs(dev);
1268
1269 err_stop_eqs:
1270 mlx5_stop_eqs(dev);
1271
1272 err_disable_msix:
1273 mlx5_disable_msix(dev);
1274
1275 err_cleanup_uar:
1276 mlx5_put_uars_page(dev, dev->priv.uar);
1277
1278 err_cleanup_once:
1279 if (boot)
1280 mlx5_cleanup_once(dev);
1281
1282 err_stop_poll:
1283 mlx5_stop_health_poll(dev, boot);
1284 if (mlx5_cmd_teardown_hca(dev)) {
1285 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1286 goto out_err;
1287 }
1288
1289 reclaim_boot_pages:
1290 mlx5_reclaim_startup_pages(dev);
1291
1292 err_pagealloc_stop:
1293 mlx5_pagealloc_stop(dev);
1294
1295 err_disable_hca:
1296 mlx5_core_disable_hca(dev);
1297
1298 err_cmd_cleanup:
1299 mlx5_cmd_cleanup(dev);
1300
1301 out_err:
1302 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1303 mutex_unlock(&dev->intf_state_mutex);
1304
1305 return err;
1306 }
1307
mlx5_unload_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool cleanup)1308 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1309 bool cleanup)
1310 {
1311 int err = 0;
1312
1313 if (cleanup)
1314 mlx5_drain_health_recovery(dev);
1315
1316 mutex_lock(&dev->intf_state_mutex);
1317 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1318 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__);
1319 if (cleanup)
1320 mlx5_cleanup_once(dev);
1321 goto out;
1322 }
1323
1324 mlx5_unregister_device(dev);
1325
1326 mlx5_eswitch_cleanup(dev->priv.eswitch);
1327 mlx5_diag_cnt_cleanup(dev);
1328 mlx5_fpga_device_stop(dev);
1329 mlx5_mpfs_destroy(dev);
1330 mlx5_cleanup_fs(dev);
1331 mlx5_wait_for_reclaim_vfs_pages(dev);
1332 free_comp_eqs(dev);
1333 mlx5_stop_eqs(dev);
1334 mlx5_disable_msix(dev);
1335 mlx5_put_uars_page(dev, dev->priv.uar);
1336 if (cleanup)
1337 mlx5_cleanup_once(dev);
1338 mlx5_stop_health_poll(dev, cleanup);
1339 err = mlx5_cmd_teardown_hca(dev);
1340 if (err) {
1341 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1342 goto out;
1343 }
1344 mlx5_pagealloc_stop(dev);
1345 mlx5_reclaim_startup_pages(dev);
1346 mlx5_core_disable_hca(dev);
1347 mlx5_cmd_cleanup(dev);
1348
1349 out:
1350 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1351 mutex_unlock(&dev->intf_state_mutex);
1352 return err;
1353 }
1354
mlx5_core_event(struct mlx5_core_dev * dev,enum mlx5_dev_event event,unsigned long param)1355 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1356 unsigned long param)
1357 {
1358 struct mlx5_priv *priv = &dev->priv;
1359 struct mlx5_device_context *dev_ctx;
1360 unsigned long flags;
1361
1362 spin_lock_irqsave(&priv->ctx_lock, flags);
1363
1364 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1365 if (dev_ctx->intf->event)
1366 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1367
1368 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1369 }
1370
1371 struct mlx5_core_event_handler {
1372 void (*event)(struct mlx5_core_dev *dev,
1373 enum mlx5_dev_event event,
1374 void *data);
1375 };
1376
1377 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e,
1378
1379 #define MLX5_PORT_MODULE_ERROR_STATS(m) \
1380 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \
1381 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \
1382 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \
1383 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \
1384 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \
1385 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \
1386 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \
1387 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \
1388 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \
1389 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \
1390 m(+1, u64, high_current, "high_current", "High current") \
1391 m(+1, u64, high_voltage, "high_voltage", "High voltage") \
1392 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \
1393 m(+1, u64, high_power, "high_power", "High power") \
1394 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault")
1395
1396 static const char *mlx5_pme_err_desc[] = {
1397 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC)
1398 };
1399
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1400 static int init_one(struct pci_dev *pdev,
1401 const struct pci_device_id *id)
1402 {
1403 struct mlx5_core_dev *dev;
1404 struct mlx5_priv *priv;
1405 device_t bsddev = pdev->dev.bsddev;
1406 #ifdef PCI_IOV
1407 nvlist_t *pf_schema, *vf_schema;
1408 int num_vfs, sriov_pos;
1409 #endif
1410 int i,err;
1411 int numa_node;
1412 struct sysctl_oid *pme_sysctl_node;
1413 struct sysctl_oid *pme_err_sysctl_node;
1414 struct sysctl_oid *cap_sysctl_node;
1415 struct sysctl_oid *current_cap_sysctl_node;
1416 struct sysctl_oid *max_cap_sysctl_node;
1417
1418 printk_once("mlx5: %s", mlx5_version);
1419
1420 numa_node = dev_to_node(&pdev->dev);
1421
1422 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, numa_node);
1423
1424 priv = &dev->priv;
1425 priv->numa_node = numa_node;
1426
1427 if (id)
1428 priv->pci_dev_data = id->driver_data;
1429
1430 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1431 device_printf(bsddev,
1432 "WARN: selected profile out of range, selecting default (%d)\n",
1433 MLX5_DEFAULT_PROF);
1434 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1435 }
1436 dev->profile = &profiles[mlx5_prof_sel];
1437 dev->pdev = pdev;
1438 dev->event = mlx5_core_event;
1439
1440 /* Set desc */
1441 device_set_desc(bsddev, mlx5_version);
1442
1443 sysctl_ctx_init(&dev->sysctl_ctx);
1444 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1445 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1446 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1447 "Maximum number of MSIX event queue vectors, if set");
1448 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1449 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1450 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0,
1451 "0:Invalid 1:Sufficient 2:Insufficient");
1452 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1453 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1454 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0,
1455 "Current power value in Watts");
1456
1457 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1458 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1459 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1460 "Port module event statistics");
1461 if (pme_sysctl_node == NULL) {
1462 err = -ENOMEM;
1463 goto clean_sysctl_ctx;
1464 }
1465 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1466 SYSCTL_CHILDREN(pme_sysctl_node),
1467 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1468 "Port module event error statistics");
1469 if (pme_err_sysctl_node == NULL) {
1470 err = -ENOMEM;
1471 goto clean_sysctl_ctx;
1472 }
1473 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1474 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1475 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1476 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED],
1477 0, "Number of time module plugged");
1478 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1479 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1480 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1481 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED],
1482 0, "Number of time module unplugged");
1483 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) {
1484 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1485 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO,
1486 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE,
1487 &dev->priv.pme_stats.error_counters[i],
1488 0, mlx5_pme_err_desc[2 * i + 1]);
1489 }
1490
1491 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1492 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1493 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1494 "hardware capabilities raw bitstrings");
1495 if (cap_sysctl_node == NULL) {
1496 err = -ENOMEM;
1497 goto clean_sysctl_ctx;
1498 }
1499 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1500 SYSCTL_CHILDREN(cap_sysctl_node),
1501 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1502 "");
1503 if (current_cap_sysctl_node == NULL) {
1504 err = -ENOMEM;
1505 goto clean_sysctl_ctx;
1506 }
1507 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1508 SYSCTL_CHILDREN(cap_sysctl_node),
1509 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1510 "");
1511 if (max_cap_sysctl_node == NULL) {
1512 err = -ENOMEM;
1513 goto clean_sysctl_ctx;
1514 }
1515 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1516 SYSCTL_CHILDREN(current_cap_sysctl_node),
1517 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1518 &dev->hca_caps_cur[MLX5_CAP_GENERAL],
1519 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1520 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1521 SYSCTL_CHILDREN(max_cap_sysctl_node),
1522 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1523 &dev->hca_caps_max[MLX5_CAP_GENERAL],
1524 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1525 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1526 SYSCTL_CHILDREN(current_cap_sysctl_node),
1527 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1528 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS],
1529 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1530 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1531 SYSCTL_CHILDREN(max_cap_sysctl_node),
1532 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1533 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS],
1534 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1535 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1536 SYSCTL_CHILDREN(current_cap_sysctl_node),
1537 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1538 &dev->hca_caps_cur[MLX5_CAP_ODP],
1539 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1540 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1541 SYSCTL_CHILDREN(max_cap_sysctl_node),
1542 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1543 &dev->hca_caps_max[MLX5_CAP_ODP],
1544 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1545 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1546 SYSCTL_CHILDREN(current_cap_sysctl_node),
1547 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1548 &dev->hca_caps_cur[MLX5_CAP_ATOMIC],
1549 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1550 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1551 SYSCTL_CHILDREN(max_cap_sysctl_node),
1552 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1553 &dev->hca_caps_max[MLX5_CAP_ATOMIC],
1554 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1555 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1556 SYSCTL_CHILDREN(current_cap_sysctl_node),
1557 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1558 &dev->hca_caps_cur[MLX5_CAP_ROCE],
1559 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1560 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1561 SYSCTL_CHILDREN(max_cap_sysctl_node),
1562 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1563 &dev->hca_caps_max[MLX5_CAP_ROCE],
1564 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1565 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1566 SYSCTL_CHILDREN(current_cap_sysctl_node),
1567 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1568 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS],
1569 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1570 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1571 SYSCTL_CHILDREN(max_cap_sysctl_node),
1572 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1573 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS],
1574 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1575 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1576 SYSCTL_CHILDREN(current_cap_sysctl_node),
1577 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1578 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS],
1579 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1580 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1581 SYSCTL_CHILDREN(max_cap_sysctl_node),
1582 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1583 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS],
1584 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1585 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1586 SYSCTL_CHILDREN(current_cap_sysctl_node),
1587 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1588 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE],
1589 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1590 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1591 SYSCTL_CHILDREN(max_cap_sysctl_node),
1592 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1593 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE],
1594 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1595 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1596 SYSCTL_CHILDREN(current_cap_sysctl_node),
1597 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1598 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE],
1599 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1600 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1601 SYSCTL_CHILDREN(max_cap_sysctl_node),
1602 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1603 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE],
1604 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1605 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1606 SYSCTL_CHILDREN(current_cap_sysctl_node),
1607 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1608 &dev->hca_caps_cur[MLX5_CAP_ESWITCH],
1609 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1610 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1611 SYSCTL_CHILDREN(max_cap_sysctl_node),
1612 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1613 &dev->hca_caps_max[MLX5_CAP_ESWITCH],
1614 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1615 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1616 SYSCTL_CHILDREN(current_cap_sysctl_node),
1617 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1618 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT],
1619 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1620 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1621 SYSCTL_CHILDREN(max_cap_sysctl_node),
1622 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1623 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT],
1624 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1625 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1626 SYSCTL_CHILDREN(current_cap_sysctl_node),
1627 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1628 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC],
1629 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1630 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1631 SYSCTL_CHILDREN(max_cap_sysctl_node),
1632 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1633 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC],
1634 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1635 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1636 SYSCTL_CHILDREN(current_cap_sysctl_node),
1637 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1638 &dev->hca_caps_cur[MLX5_CAP_QOS],
1639 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1640 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1641 SYSCTL_CHILDREN(max_cap_sysctl_node),
1642 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1643 &dev->hca_caps_max[MLX5_CAP_QOS],
1644 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1645 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1646 SYSCTL_CHILDREN(current_cap_sysctl_node),
1647 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1648 &dev->hca_caps_cur[MLX5_CAP_DEBUG],
1649 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1650 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1651 SYSCTL_CHILDREN(max_cap_sysctl_node),
1652 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1653 &dev->hca_caps_max[MLX5_CAP_DEBUG],
1654 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1655 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1656 SYSCTL_CHILDREN(cap_sysctl_node),
1657 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1658 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", "");
1659 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1660 SYSCTL_CHILDREN(cap_sysctl_node),
1661 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1662 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", "");
1663 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1664 SYSCTL_CHILDREN(cap_sysctl_node),
1665 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1666 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", "");
1667 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1668 SYSCTL_CHILDREN(cap_sysctl_node),
1669 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE,
1670 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", "");
1671
1672 INIT_LIST_HEAD(&priv->ctx_list);
1673 spin_lock_init(&priv->ctx_lock);
1674 mutex_init(&dev->pci_status_mutex);
1675 mutex_init(&dev->intf_state_mutex);
1676
1677 mutex_init(&priv->bfregs.reg_head.lock);
1678 mutex_init(&priv->bfregs.wc_head.lock);
1679 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1680 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1681
1682 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW);
1683 err = mlx5_pci_init(dev, priv);
1684 if (err) {
1685 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err);
1686 goto clean_dev;
1687 }
1688
1689 err = mlx5_health_init(dev);
1690 if (err) {
1691 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err);
1692 goto close_pci;
1693 }
1694
1695 mlx5_pagealloc_init(dev);
1696
1697 err = mlx5_load_one(dev, priv, true);
1698 if (err) {
1699 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err);
1700 goto clean_health;
1701 }
1702
1703 mlx5_fwdump_prep(dev);
1704
1705 mlx5_firmware_update(dev);
1706
1707 #ifdef PCI_IOV
1708 if (MLX5_CAP_GEN(dev, vport_group_manager)) {
1709 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) {
1710 num_vfs = pci_read_config(bsddev, sriov_pos +
1711 PCIR_SRIOV_TOTAL_VFS, 2);
1712 } else {
1713 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n");
1714 num_vfs = 0;
1715 }
1716 err = mlx5_eswitch_init(dev, 1 + num_vfs);
1717 if (err == 0) {
1718 pf_schema = pci_iov_schema_alloc_node();
1719 vf_schema = pci_iov_schema_alloc_node();
1720 pci_iov_schema_add_unicast_mac(vf_schema,
1721 iov_mac_addr_name, 0, NULL);
1722 pci_iov_schema_add_vlan(vf_schema,
1723 iov_vlan_name, 0, 0);
1724 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name,
1725 0, 0);
1726 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name,
1727 0, 0);
1728 err = pci_iov_attach(bsddev, pf_schema, vf_schema);
1729 if (err == 0) {
1730 dev->iov_pf = true;
1731 } else {
1732 device_printf(bsddev,
1733 "Failed to initialize SR-IOV support, error %d\n",
1734 err);
1735 }
1736 } else {
1737 mlx5_core_err(dev, "eswitch init failed, error %d\n",
1738 err);
1739 }
1740 }
1741 #endif
1742
1743 pci_save_state(pdev);
1744 return 0;
1745
1746 clean_health:
1747 mlx5_pagealloc_cleanup(dev);
1748 mlx5_health_cleanup(dev);
1749 close_pci:
1750 mlx5_pci_close(dev, priv);
1751 clean_dev:
1752 mtx_destroy(&dev->dump_lock);
1753 clean_sysctl_ctx:
1754 sysctl_ctx_free(&dev->sysctl_ctx);
1755 kfree(dev);
1756 return err;
1757 }
1758
remove_one(struct pci_dev * pdev)1759 static void remove_one(struct pci_dev *pdev)
1760 {
1761 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1762 struct mlx5_priv *priv = &dev->priv;
1763
1764 #ifdef PCI_IOV
1765 if (dev->iov_pf) {
1766 pci_iov_detach(pdev->dev.bsddev);
1767 mlx5_eswitch_disable_sriov(priv->eswitch);
1768 dev->iov_pf = false;
1769 }
1770 #endif
1771
1772 if (mlx5_unload_one(dev, priv, true)) {
1773 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n",
1774 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE));
1775 }
1776
1777 mlx5_pagealloc_cleanup(dev);
1778 mlx5_health_cleanup(dev);
1779 mlx5_fwdump_clean(dev);
1780 mlx5_pci_close(dev, priv);
1781 mtx_destroy(&dev->dump_lock);
1782 pci_set_drvdata(pdev, NULL);
1783 sysctl_ctx_free(&dev->sysctl_ctx);
1784 kfree(dev);
1785 }
1786
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1787 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1788 pci_channel_state_t state)
1789 {
1790 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1791 struct mlx5_priv *priv = &dev->priv;
1792
1793 mlx5_core_info(dev, "%s was called\n", __func__);
1794 mlx5_enter_error_state(dev, false);
1795 mlx5_unload_one(dev, priv, false);
1796
1797 if (state) {
1798 mlx5_drain_health_wq(dev);
1799 mlx5_pci_disable_device(dev);
1800 }
1801
1802 return state == pci_channel_io_perm_failure ?
1803 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1804 }
1805
mlx5_pci_slot_reset(struct pci_dev * pdev)1806 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1807 {
1808 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1809 int err = 0;
1810
1811 mlx5_core_info(dev,"%s was called\n", __func__);
1812
1813 err = mlx5_pci_enable_device(dev);
1814 if (err) {
1815 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n"
1816 ,err);
1817 return PCI_ERS_RESULT_DISCONNECT;
1818 }
1819 pci_set_master(pdev);
1820 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1821 pci_restore_state(pdev);
1822 pci_save_state(pdev);
1823
1824 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1825 }
1826
1827 /* wait for the device to show vital signs. For now we check
1828 * that we can read the device ID and that the health buffer
1829 * shows a non zero value which is different than 0xffffffff
1830 */
wait_vital(struct pci_dev * pdev)1831 static void wait_vital(struct pci_dev *pdev)
1832 {
1833 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1834 struct mlx5_core_health *health = &dev->priv.health;
1835 const int niter = 100;
1836 u32 count;
1837 u16 did;
1838 int i;
1839
1840 /* Wait for firmware to be ready after reset */
1841 msleep(1000);
1842 for (i = 0; i < niter; i++) {
1843 if (pci_read_config_word(pdev, 2, &did)) {
1844 mlx5_core_warn(dev, "failed reading config word\n");
1845 break;
1846 }
1847 if (did == pdev->device) {
1848 mlx5_core_info(dev,
1849 "device ID correctly read after %d iterations\n", i);
1850 break;
1851 }
1852 msleep(50);
1853 }
1854 if (i == niter)
1855 mlx5_core_warn(dev, "could not read device ID\n");
1856
1857 for (i = 0; i < niter; i++) {
1858 count = ioread32be(health->health_counter);
1859 if (count && count != 0xffffffff) {
1860 mlx5_core_info(dev,
1861 "Counter value 0x%x after %d iterations\n", count, i);
1862 break;
1863 }
1864 msleep(50);
1865 }
1866
1867 if (i == niter)
1868 mlx5_core_warn(dev, "could not read device ID\n");
1869 }
1870
mlx5_pci_resume(struct pci_dev * pdev)1871 static void mlx5_pci_resume(struct pci_dev *pdev)
1872 {
1873 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1874 struct mlx5_priv *priv = &dev->priv;
1875 int err;
1876
1877 mlx5_core_info(dev,"%s was called\n", __func__);
1878
1879 wait_vital(pdev);
1880
1881 err = mlx5_load_one(dev, priv, false);
1882 if (err)
1883 mlx5_core_err(dev,
1884 "mlx5_load_one failed with error code: %d\n" ,err);
1885 else
1886 mlx5_core_info(dev,"device recovered\n");
1887 }
1888
1889 static const struct pci_error_handlers mlx5_err_handler = {
1890 .error_detected = mlx5_pci_err_detected,
1891 .slot_reset = mlx5_pci_slot_reset,
1892 .resume = mlx5_pci_resume
1893 };
1894
1895 #ifdef PCI_IOV
1896 static int
mlx5_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * pf_config)1897 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config)
1898 {
1899 struct pci_dev *pdev;
1900 struct mlx5_core_dev *core_dev;
1901 struct mlx5_priv *priv;
1902 int err;
1903
1904 pdev = device_get_softc(dev);
1905 core_dev = pci_get_drvdata(pdev);
1906 priv = &core_dev->priv;
1907
1908 if (priv->eswitch == NULL)
1909 return (ENXIO);
1910 if (priv->eswitch->total_vports < num_vfs + 1)
1911 num_vfs = priv->eswitch->total_vports - 1;
1912 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs);
1913 return (-err);
1914 }
1915
1916 static void
mlx5_iov_uninit(device_t dev)1917 mlx5_iov_uninit(device_t dev)
1918 {
1919 struct pci_dev *pdev;
1920 struct mlx5_core_dev *core_dev;
1921 struct mlx5_priv *priv;
1922
1923 pdev = device_get_softc(dev);
1924 core_dev = pci_get_drvdata(pdev);
1925 priv = &core_dev->priv;
1926
1927 mlx5_eswitch_disable_sriov(priv->eswitch);
1928 }
1929
1930 static int
mlx5_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * vf_config)1931 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config)
1932 {
1933 struct pci_dev *pdev;
1934 struct mlx5_core_dev *core_dev;
1935 struct mlx5_priv *priv;
1936 const void *mac;
1937 size_t mac_size;
1938 uint64_t node_guid, port_guid;
1939 int error;
1940
1941 pdev = device_get_softc(dev);
1942 core_dev = pci_get_drvdata(pdev);
1943 priv = &core_dev->priv;
1944
1945 if (vfnum + 1 >= priv->eswitch->total_vports)
1946 return (ENXIO);
1947
1948 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) {
1949 mac = nvlist_get_binary(vf_config, iov_mac_addr_name,
1950 &mac_size);
1951 error = -mlx5_eswitch_set_vport_mac(priv->eswitch,
1952 vfnum + 1, __DECONST(u8 *, mac));
1953 if (error != 0) {
1954 mlx5_core_err(core_dev,
1955 "setting MAC for VF %d failed, error %d\n",
1956 vfnum + 1, error);
1957 }
1958 }
1959
1960 if (nvlist_exists_number(vf_config, iov_vlan_name)) {
1961 uint16_t vlan = nvlist_get_number(vf_config, iov_vlan_name);
1962
1963 if (vlan == DOT1Q_VID_NULL)
1964 error = ENOTSUP;
1965 else {
1966 if (vlan == VF_VLAN_TRUNK)
1967 vlan = DOT1Q_VID_NULL;
1968
1969 error = -mlx5_eswitch_set_vport_vlan(priv->eswitch,
1970 vfnum + 1, vlan, 0);
1971 }
1972 if (error != 0) {
1973 mlx5_core_err(core_dev,
1974 "setting VLAN for VF %d failed, error %d\n",
1975 vfnum + 1, error);
1976 }
1977 }
1978
1979 if (nvlist_exists_number(vf_config, iov_node_guid_name)) {
1980 node_guid = nvlist_get_number(vf_config, iov_node_guid_name);
1981 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1,
1982 node_guid);
1983 if (error != 0) {
1984 mlx5_core_err(core_dev,
1985 "modifying node GUID for VF %d failed, error %d\n",
1986 vfnum + 1, error);
1987 }
1988 }
1989
1990 if (nvlist_exists_number(vf_config, iov_port_guid_name)) {
1991 port_guid = nvlist_get_number(vf_config, iov_port_guid_name);
1992 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1,
1993 port_guid);
1994 if (error != 0) {
1995 mlx5_core_err(core_dev,
1996 "modifying port GUID for VF %d failed, error %d\n",
1997 vfnum + 1, error);
1998 }
1999 }
2000
2001 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1,
2002 VPORT_STATE_FOLLOW);
2003 if (error != 0) {
2004 mlx5_core_err(core_dev,
2005 "upping vport for VF %d failed, error %d\n",
2006 vfnum + 1, error);
2007 }
2008 error = -mlx5_core_enable_hca(core_dev, vfnum + 1);
2009 if (error != 0) {
2010 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n",
2011 vfnum + 1, error);
2012 }
2013 return (error);
2014 }
2015 #endif
2016
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2017 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2018 {
2019 bool fast_teardown, force_teardown;
2020 int err;
2021
2022 if (!mlx5_fast_unload_enabled) {
2023 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
2024 return -EOPNOTSUPP;
2025 }
2026
2027 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2028 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2029
2030 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2031 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2032
2033 if (!fast_teardown && !force_teardown)
2034 return -EOPNOTSUPP;
2035
2036 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2037 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2038 return -EAGAIN;
2039 }
2040
2041 /* Panic tear down fw command will stop the PCI bus communication
2042 * with the HCA, so the health polll is no longer needed.
2043 */
2044 mlx5_drain_health_wq(dev);
2045 mlx5_stop_health_poll(dev, false);
2046
2047 err = mlx5_cmd_fast_teardown_hca(dev);
2048 if (!err)
2049 goto done;
2050
2051 err = mlx5_cmd_force_teardown_hca(dev);
2052 if (!err)
2053 goto done;
2054
2055 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
2056 mlx5_start_health_poll(dev);
2057 return err;
2058 done:
2059 mlx5_enter_error_state(dev, true);
2060 return 0;
2061 }
2062
mlx5_shutdown_disable_interrupts(struct mlx5_core_dev * mdev)2063 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev)
2064 {
2065 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
2066 int x;
2067
2068 mdev->priv.disable_irqs = 1;
2069
2070 /* wait for all IRQ handlers to finish processing */
2071 for (x = 0; x != nvec; x++)
2072 synchronize_irq(mdev->priv.msix_arr[x].vector);
2073 }
2074
shutdown_one(struct pci_dev * pdev)2075 static void shutdown_one(struct pci_dev *pdev)
2076 {
2077 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2078 struct mlx5_priv *priv = &dev->priv;
2079 int err;
2080
2081 /* enter polling mode */
2082 mlx5_cmd_use_polling(dev);
2083
2084 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state);
2085
2086 /* disable all interrupts */
2087 mlx5_shutdown_disable_interrupts(dev);
2088
2089 err = mlx5_try_fast_unload(dev);
2090 if (err)
2091 mlx5_unload_one(dev, priv, false);
2092 mlx5_pci_disable_device(dev);
2093 }
2094
2095 static const struct pci_device_id mlx5_core_pci_table[] = {
2096 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
2097 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
2098 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
2099 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
2100 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
2101 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
2102 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */
2103 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
2104 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */
2105 { PCI_VDEVICE(MELLANOX, 4122) }, /* ConnectX-5 Ex VF */
2106 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */
2107 { PCI_VDEVICE(MELLANOX, 4124) }, /* ConnectX-6 VF */
2108 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */
2109 { PCI_VDEVICE(MELLANOX, 4126) }, /* ConnectX Family mlx5Gen Virtual Function */
2110 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */
2111 { PCI_VDEVICE(MELLANOX, 4128) },
2112 { PCI_VDEVICE(MELLANOX, 4129) }, /* ConnectX-7 */
2113 { PCI_VDEVICE(MELLANOX, 4130) },
2114 { PCI_VDEVICE(MELLANOX, 4131) }, /* ConnectX-8 */
2115 { PCI_VDEVICE(MELLANOX, 4132) },
2116 { PCI_VDEVICE(MELLANOX, 4133) },
2117 { PCI_VDEVICE(MELLANOX, 4134) },
2118 { PCI_VDEVICE(MELLANOX, 4135) },
2119 { PCI_VDEVICE(MELLANOX, 4136) },
2120 { PCI_VDEVICE(MELLANOX, 4137) },
2121 { PCI_VDEVICE(MELLANOX, 4138) },
2122 { PCI_VDEVICE(MELLANOX, 4139) },
2123 { PCI_VDEVICE(MELLANOX, 4140) },
2124 { PCI_VDEVICE(MELLANOX, 4141) },
2125 { PCI_VDEVICE(MELLANOX, 4142) },
2126 { PCI_VDEVICE(MELLANOX, 4143) },
2127 { PCI_VDEVICE(MELLANOX, 4144) },
2128 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2129 { PCI_VDEVICE(MELLANOX, 0xa2d3) }, /* BlueField integrated ConnectX-5 network controller VF */
2130 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2131 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2132 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
2133 { }
2134 };
2135
2136 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2137
mlx5_disable_device(struct mlx5_core_dev * dev)2138 void mlx5_disable_device(struct mlx5_core_dev *dev)
2139 {
2140 mlx5_pci_err_detected(dev->pdev, 0);
2141 }
2142
mlx5_recover_device(struct mlx5_core_dev * dev)2143 void mlx5_recover_device(struct mlx5_core_dev *dev)
2144 {
2145 mlx5_pci_disable_device(dev);
2146 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
2147 mlx5_pci_resume(dev->pdev);
2148 }
2149
2150 struct pci_driver mlx5_core_driver = {
2151 .name = DRIVER_NAME,
2152 .id_table = mlx5_core_pci_table,
2153 .shutdown = shutdown_one,
2154 .probe = init_one,
2155 .remove = remove_one,
2156 .err_handler = &mlx5_err_handler,
2157 #ifdef PCI_IOV
2158 .bsd_iov_init = mlx5_iov_init,
2159 .bsd_iov_uninit = mlx5_iov_uninit,
2160 .bsd_iov_add_vf = mlx5_iov_add_vf,
2161 #endif
2162 };
2163
init(void)2164 static int __init init(void)
2165 {
2166 int err;
2167
2168 err = pci_register_driver(&mlx5_core_driver);
2169 if (err)
2170 goto err_debug;
2171
2172 err = mlx5_ctl_init();
2173 if (err)
2174 goto err_ctl;
2175
2176 return 0;
2177
2178 err_ctl:
2179 pci_unregister_driver(&mlx5_core_driver);
2180
2181 err_debug:
2182 return err;
2183 }
2184
cleanup(void)2185 static void __exit cleanup(void)
2186 {
2187 mlx5_ctl_fini();
2188 pci_unregister_driver(&mlx5_core_driver);
2189 }
2190
2191 module_init_order(init, SI_ORDER_FIRST);
2192 module_exit_order(cleanup, SI_ORDER_FIRST);
2193