1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved */ 3 4 #ifndef __MLX5_EN_DIM_H__ 5 #define __MLX5_EN_DIM_H__ 6 7 #include <linux/dim.h> 8 #include <linux/types.h> 9 #include <linux/mlx5/mlx5_ifc.h> 10 11 /* Forward declarations */ 12 struct mlx5e_rq; 13 struct mlx5e_txqsq; 14 struct work_struct; 15 16 /* convert a boolean value for cqe mode to appropriate dim constant 17 * true : DIM_CQ_PERIOD_MODE_START_FROM_CQE 18 * false : DIM_CQ_PERIOD_MODE_START_FROM_EQE 19 */ mlx5e_dim_cq_period_mode(bool start_from_cqe)20static inline int mlx5e_dim_cq_period_mode(bool start_from_cqe) 21 { 22 return start_from_cqe ? DIM_CQ_PERIOD_MODE_START_FROM_CQE : 23 DIM_CQ_PERIOD_MODE_START_FROM_EQE; 24 } 25 26 static inline enum mlx5_cq_period_mode mlx5e_cq_period_mode(enum dim_cq_period_mode cq_period_mode)27mlx5e_cq_period_mode(enum dim_cq_period_mode cq_period_mode) 28 { 29 switch (cq_period_mode) { 30 case DIM_CQ_PERIOD_MODE_START_FROM_EQE: 31 return MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 32 case DIM_CQ_PERIOD_MODE_START_FROM_CQE: 33 return MLX5_CQ_PERIOD_MODE_START_FROM_CQE; 34 default: 35 WARN_ON_ONCE(true); 36 return MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 37 } 38 } 39 40 void mlx5e_rx_dim_work(struct work_struct *work); 41 void mlx5e_tx_dim_work(struct work_struct *work); 42 int mlx5e_dim_rx_change(struct mlx5e_rq *rq, bool enabled); 43 int mlx5e_dim_tx_change(struct mlx5e_txqsq *sq, bool enabled); 44 45 #endif /* __MLX5_EN_DIM_H__ */ 46