1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * All rights reserved.
7 *
8 * Adapted and extended to Marvell SoCs by Semihalf.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/ktr.h>
38 #include <sys/module.h>
39 #include <sys/rman.h>
40 #include <machine/bus.h>
41 #include <machine/intr.h>
42
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <arm/mv/mvreg.h>
47 #include <arm/mv/mvvar.h>
48
49 struct mv_ic_softc {
50 struct resource * ic_res[1];
51 bus_space_tag_t ic_bst;
52 bus_space_handle_t ic_bsh;
53 int ic_high_regs;
54 int ic_error_regs;
55 };
56
57 static struct resource_spec mv_ic_spec[] = {
58 { SYS_RES_MEMORY, 0, RF_ACTIVE },
59 { -1, 0 }
60 };
61
62 static struct mv_ic_softc *mv_ic_sc = NULL;
63
64 static int mv_ic_probe(device_t);
65 static int mv_ic_attach(device_t);
66
67 uint32_t mv_ic_get_cause(void);
68 uint32_t mv_ic_get_mask(void);
69 void mv_ic_set_mask(uint32_t);
70 uint32_t mv_ic_get_cause_hi(void);
71 uint32_t mv_ic_get_mask_hi(void);
72 void mv_ic_set_mask_hi(uint32_t);
73 uint32_t mv_ic_get_cause_error(void);
74 uint32_t mv_ic_get_mask_error(void);
75 void mv_ic_set_mask_error(uint32_t);
76 static void arm_mask_irq_all(void);
77
78 static int
mv_ic_probe(device_t dev)79 mv_ic_probe(device_t dev)
80 {
81
82 if (!ofw_bus_status_okay(dev))
83 return (ENXIO);
84
85 if (!ofw_bus_is_compatible(dev, "mrvl,pic"))
86 return (ENXIO);
87
88 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
89 return (0);
90 }
91
92 static int
mv_ic_attach(device_t dev)93 mv_ic_attach(device_t dev)
94 {
95 struct mv_ic_softc *sc;
96 uint32_t dev_id, rev_id;
97 int error;
98
99 sc = (struct mv_ic_softc *)device_get_softc(dev);
100
101 if (mv_ic_sc != NULL)
102 return (ENXIO);
103 mv_ic_sc = sc;
104
105 soc_id(&dev_id, &rev_id);
106
107 sc->ic_high_regs = 0;
108 sc->ic_error_regs = 0;
109
110 if (dev_id == MV_DEV_88F6281 ||
111 dev_id == MV_DEV_88F6282 ||
112 dev_id == MV_DEV_MV78100 ||
113 dev_id == MV_DEV_MV78100_Z0)
114 sc->ic_high_regs = 1;
115
116 if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
117 sc->ic_error_regs = 1;
118
119 error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
120 if (error) {
121 device_printf(dev, "could not allocate resources\n");
122 return (ENXIO);
123 }
124
125 sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
126 sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
127
128 /* Mask all interrupts */
129 arm_mask_irq_all();
130
131 return (0);
132 }
133
134 static device_method_t mv_ic_methods[] = {
135 DEVMETHOD(device_probe, mv_ic_probe),
136 DEVMETHOD(device_attach, mv_ic_attach),
137 { 0, 0 }
138 };
139
140 static driver_t mv_ic_driver = {
141 "ic",
142 mv_ic_methods,
143 sizeof(struct mv_ic_softc),
144 };
145
146 DRIVER_MODULE(ic, simplebus, mv_ic_driver, 0, 0);
147
148 int
arm_get_next_irq(int last)149 arm_get_next_irq(int last)
150 {
151 u_int filt, irq;
152 int next;
153
154 filt = ~((last >= 0) ? (2 << last) - 1 : 0);
155 irq = mv_ic_get_cause() & mv_ic_get_mask();
156 if (irq & filt) {
157 next = ffs(irq & filt) - 1;
158 goto out;
159 }
160 if (mv_ic_sc->ic_high_regs) {
161 filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0);
162 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
163 if (irq & filt) {
164 next = ffs(irq & filt) + 31;
165 goto out;
166 }
167 }
168 if (mv_ic_sc->ic_error_regs) {
169 filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0);
170 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
171 if (irq & filt) {
172 next = ffs(irq & filt) + 63;
173 goto out;
174 }
175 }
176 next = -1;
177
178 out:
179 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
180 return (next);
181 }
182
183 static void
arm_mask_irq_all(void)184 arm_mask_irq_all(void)
185 {
186
187 mv_ic_set_mask(0);
188
189 if (mv_ic_sc->ic_high_regs)
190 mv_ic_set_mask_hi(0);
191
192 if (mv_ic_sc->ic_error_regs)
193 mv_ic_set_mask_error(0);
194 }
195
196 void
arm_mask_irq(uintptr_t nb)197 arm_mask_irq(uintptr_t nb)
198 {
199 uint32_t mr;
200
201 if (nb < 32) {
202 mr = mv_ic_get_mask();
203 mr &= ~(1 << nb);
204 mv_ic_set_mask(mr);
205
206 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
207 mr = mv_ic_get_mask_hi();
208 mr &= ~(1 << (nb - 32));
209 mv_ic_set_mask_hi(mr);
210
211 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
212 mr = mv_ic_get_mask_error();
213 mr &= ~(1 << (nb - 64));
214 mv_ic_set_mask_error(mr);
215 }
216 }
217
218 void
arm_unmask_irq(uintptr_t nb)219 arm_unmask_irq(uintptr_t nb)
220 {
221 uint32_t mr;
222
223 if (nb < 32) {
224 mr = mv_ic_get_mask();
225 mr |= (1 << nb);
226 mv_ic_set_mask(mr);
227
228 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
229 mr = mv_ic_get_mask_hi();
230 mr |= (1 << (nb - 32));
231 mv_ic_set_mask_hi(mr);
232
233 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
234 mr = mv_ic_get_mask_error();
235 mr |= (1 << (nb - 64));
236 mv_ic_set_mask_error(mr);
237 }
238 }
239
240 void
mv_ic_set_mask(uint32_t val)241 mv_ic_set_mask(uint32_t val)
242 {
243
244 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
245 IRQ_MASK, val);
246 }
247
248 uint32_t
mv_ic_get_mask(void)249 mv_ic_get_mask(void)
250 {
251
252 return (bus_space_read_4(mv_ic_sc->ic_bst,
253 mv_ic_sc->ic_bsh, IRQ_MASK));
254 }
255
256 uint32_t
mv_ic_get_cause(void)257 mv_ic_get_cause(void)
258 {
259
260 return (bus_space_read_4(mv_ic_sc->ic_bst,
261 mv_ic_sc->ic_bsh, IRQ_CAUSE));
262 }
263
264 void
mv_ic_set_mask_hi(uint32_t val)265 mv_ic_set_mask_hi(uint32_t val)
266 {
267
268 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
269 IRQ_MASK_HI, val);
270 }
271
272 uint32_t
mv_ic_get_mask_hi(void)273 mv_ic_get_mask_hi(void)
274 {
275
276 return (bus_space_read_4(mv_ic_sc->ic_bst,
277 mv_ic_sc->ic_bsh, IRQ_MASK_HI));
278 }
279
280 uint32_t
mv_ic_get_cause_hi(void)281 mv_ic_get_cause_hi(void)
282 {
283
284 return (bus_space_read_4(mv_ic_sc->ic_bst,
285 mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
286 }
287
288 void
mv_ic_set_mask_error(uint32_t val)289 mv_ic_set_mask_error(uint32_t val)
290 {
291
292 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
293 IRQ_MASK_ERROR, val);
294 }
295
296 uint32_t
mv_ic_get_mask_error(void)297 mv_ic_get_mask_error(void)
298 {
299
300 return (bus_space_read_4(mv_ic_sc->ic_bst,
301 mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
302 }
303
304 uint32_t
mv_ic_get_cause_error(void)305 mv_ic_get_cause_error(void)
306 {
307
308 return (bus_space_read_4(mv_ic_sc->ic_bst,
309 mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));
310 }
311