1 //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/PointerUnion.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringSet.h"
23 #include "llvm/ADT/iterator_range.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBundle.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/RegisterBank.h"
29 #include "llvm/CodeGen/TargetRegisterInfo.h"
30 #include "llvm/CodeGen/TargetSubtargetInfo.h"
31 #include "llvm/MC/LaneBitmask.h"
32 #include <cassert>
33 #include <cstddef>
34 #include <cstdint>
35 #include <iterator>
36 #include <memory>
37 #include <utility>
38 #include <vector>
39
40 namespace llvm {
41
42 class PSetIterator;
43
44 /// Convenient type to represent either a register class or a register bank.
45 using RegClassOrRegBank =
46 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
47
48 /// MachineRegisterInfo - Keep track of information for virtual and physical
49 /// registers, including vreg register classes, use/def chains for registers,
50 /// etc.
51 class MachineRegisterInfo {
52 public:
53 class Delegate {
54 virtual void anchor();
55
56 public:
57 virtual ~Delegate() = default;
58
59 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
MRI_NoteCloneVirtualRegister(Register NewReg,Register SrcReg)60 virtual void MRI_NoteCloneVirtualRegister(Register NewReg,
61 Register SrcReg) {
62 MRI_NoteNewVirtualRegister(NewReg);
63 }
64 };
65
66 private:
67 MachineFunction *MF;
68 SmallPtrSet<Delegate *, 1> TheDelegates;
69
70 /// True if subregister liveness is tracked.
71 const bool TracksSubRegLiveness;
72
73 /// VRegInfo - Information we keep for each virtual register.
74 ///
75 /// Each element in this list contains the register class of the vreg and the
76 /// start of the use/def list for the register.
77 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
78 VirtReg2IndexFunctor>
79 VRegInfo;
80
81 /// Map for recovering vreg name from vreg number.
82 /// This map is used by the MIR Printer.
83 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
84
85 /// StringSet that is used to unique vreg names.
86 StringSet<> VRegNames;
87
88 /// The flag is true upon \p UpdatedCSRs initialization
89 /// and false otherwise.
90 bool IsUpdatedCSRsInitialized = false;
91
92 /// Contains the updated callee saved register list.
93 /// As opposed to the static list defined in register info,
94 /// all registers that were disabled are removed from the list.
95 SmallVector<MCPhysReg, 16> UpdatedCSRs;
96
97 /// RegAllocHints - This vector records register allocation hints for
98 /// virtual registers. For each virtual register, it keeps a pair of hint
99 /// type and hints vector making up the allocation hints. Only the first
100 /// hint may be target specific, and in that case this is reflected by the
101 /// first member of the pair being non-zero. If the hinted register is
102 /// virtual, it means the allocator should prefer the physical register
103 /// allocated to it if any.
104 IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>,
105 VirtReg2IndexFunctor>
106 RegAllocHints;
107
108 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
109 /// physical registers.
110 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
111
112 /// getRegUseDefListHead - Return the head pointer for the register use/def
113 /// list for the specified virtual or physical register.
getRegUseDefListHead(Register RegNo)114 MachineOperand *&getRegUseDefListHead(Register RegNo) {
115 if (RegNo.isVirtual())
116 return VRegInfo[RegNo.id()].second;
117 return PhysRegUseDefLists[RegNo.id()];
118 }
119
getRegUseDefListHead(Register RegNo)120 MachineOperand *getRegUseDefListHead(Register RegNo) const {
121 if (RegNo.isVirtual())
122 return VRegInfo[RegNo.id()].second;
123 return PhysRegUseDefLists[RegNo.id()];
124 }
125
126 /// Get the next element in the use-def chain.
getNextOperandForReg(const MachineOperand * MO)127 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
128 assert(MO && MO->isReg() && "This is not a register operand!");
129 return MO->Contents.Reg.Next;
130 }
131
132 /// UsedPhysRegMask - Additional used physregs including aliases.
133 /// This bit vector represents all the registers clobbered by function calls.
134 BitVector UsedPhysRegMask;
135
136 /// ReservedRegs - This is a bit vector of reserved registers. The target
137 /// may change its mind about which registers should be reserved. This
138 /// vector is the frozen set of reserved registers when register allocation
139 /// started.
140 BitVector ReservedRegs;
141
142 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
143 /// Map generic virtual registers to their low-level type.
144 VRegToTypeMap VRegToType;
145
146 /// Keep track of the physical registers that are live in to the function.
147 /// Live in values are typically arguments in registers. LiveIn values are
148 /// allowed to have virtual registers associated with them, stored in the
149 /// second element.
150 std::vector<std::pair<MCRegister, Register>> LiveIns;
151
152 public:
153 explicit MachineRegisterInfo(MachineFunction *MF);
154 MachineRegisterInfo(const MachineRegisterInfo &) = delete;
155 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
156
getTargetRegisterInfo()157 const TargetRegisterInfo *getTargetRegisterInfo() const {
158 return MF->getSubtarget().getRegisterInfo();
159 }
160
resetDelegate(Delegate * delegate)161 void resetDelegate(Delegate *delegate) {
162 // Ensure another delegate does not take over unless the current
163 // delegate first unattaches itself.
164 assert(TheDelegates.count(delegate) &&
165 "Only an existing delegate can perform reset!");
166 TheDelegates.erase(delegate);
167 }
168
addDelegate(Delegate * delegate)169 void addDelegate(Delegate *delegate) {
170 assert(delegate && !TheDelegates.count(delegate) &&
171 "Attempted to add null delegate, or to change it without "
172 "first resetting it!");
173
174 TheDelegates.insert(delegate);
175 }
176
noteNewVirtualRegister(Register Reg)177 void noteNewVirtualRegister(Register Reg) {
178 for (auto *TheDelegate : TheDelegates)
179 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
180 }
181
noteCloneVirtualRegister(Register NewReg,Register SrcReg)182 void noteCloneVirtualRegister(Register NewReg, Register SrcReg) {
183 for (auto *TheDelegate : TheDelegates)
184 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
185 }
186
187 //===--------------------------------------------------------------------===//
188 // Function State
189 //===--------------------------------------------------------------------===//
190
191 // isSSA - Returns true when the machine function is in SSA form. Early
192 // passes require the machine function to be in SSA form where every virtual
193 // register has a single defining instruction.
194 //
195 // The TwoAddressInstructionPass and PHIElimination passes take the machine
196 // function out of SSA form when they introduce multiple defs per virtual
197 // register.
isSSA()198 bool isSSA() const {
199 return MF->getProperties().hasProperty(
200 MachineFunctionProperties::Property::IsSSA);
201 }
202
203 // leaveSSA - Indicates that the machine function is no longer in SSA form.
leaveSSA()204 void leaveSSA() {
205 MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
206 }
207
208 /// tracksLiveness - Returns true when tracking register liveness accurately.
209 /// (see MachineFUnctionProperties::Property description for details)
tracksLiveness()210 bool tracksLiveness() const {
211 return MF->getProperties().hasProperty(
212 MachineFunctionProperties::Property::TracksLiveness);
213 }
214
215 /// invalidateLiveness - Indicates that register liveness is no longer being
216 /// tracked accurately.
217 ///
218 /// This should be called by late passes that invalidate the liveness
219 /// information.
invalidateLiveness()220 void invalidateLiveness() {
221 MF->getProperties().reset(
222 MachineFunctionProperties::Property::TracksLiveness);
223 }
224
225 /// Returns true if liveness for register class @p RC should be tracked at
226 /// the subregister level.
shouldTrackSubRegLiveness(const TargetRegisterClass & RC)227 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
228 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
229 }
shouldTrackSubRegLiveness(Register VReg)230 bool shouldTrackSubRegLiveness(Register VReg) const {
231 assert(VReg.isVirtual() && "Must pass a VReg");
232 const TargetRegisterClass *RC = getRegClassOrNull(VReg);
233 return LLVM_LIKELY(RC) ? shouldTrackSubRegLiveness(*RC) : false;
234 }
subRegLivenessEnabled()235 bool subRegLivenessEnabled() const {
236 return TracksSubRegLiveness;
237 }
238
239 //===--------------------------------------------------------------------===//
240 // Register Info
241 //===--------------------------------------------------------------------===//
242
243 /// Returns true if the updated CSR list was initialized and false otherwise.
isUpdatedCSRsInitialized()244 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
245
246 /// Returns true if a register can be used as an argument to a function.
247 bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
248
249 /// Returns true if a register is a fixed register.
250 bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
251
252 /// Returns true if a register is a general purpose register.
253 bool isGeneralPurposeRegister(const MachineFunction &MF,
254 MCRegister Reg) const;
255
256 /// Disables the register from the list of CSRs.
257 /// I.e. the register will not appear as part of the CSR mask.
258 /// \see UpdatedCalleeSavedRegs.
259 void disableCalleeSavedRegister(MCRegister Reg);
260
261 /// Returns list of callee saved registers.
262 /// The function returns the updated CSR list (after taking into account
263 /// registers that are disabled from the CSR list).
264 const MCPhysReg *getCalleeSavedRegs() const;
265
266 /// Sets the updated Callee Saved Registers list.
267 /// Notice that it will override ant previously disabled/saved CSRs.
268 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
269
270 // Strictly for use by MachineInstr.cpp.
271 void addRegOperandToUseList(MachineOperand *MO);
272
273 // Strictly for use by MachineInstr.cpp.
274 void removeRegOperandFromUseList(MachineOperand *MO);
275
276 // Strictly for use by MachineInstr.cpp.
277 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
278
279 /// Verify the sanity of the use list for Reg.
280 void verifyUseList(Register Reg) const;
281
282 /// Verify the use list of all registers.
283 void verifyUseLists() const;
284
285 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
286 /// and uses of a register within the MachineFunction that corresponds to this
287 /// MachineRegisterInfo object.
288 template<bool Uses, bool Defs, bool SkipDebug,
289 bool ByOperand, bool ByInstr, bool ByBundle>
290 class defusechain_iterator;
291 template<bool Uses, bool Defs, bool SkipDebug,
292 bool ByOperand, bool ByInstr, bool ByBundle>
293 class defusechain_instr_iterator;
294
295 // Make it a friend so it can access getNextOperandForReg().
296 template<bool, bool, bool, bool, bool, bool>
297 friend class defusechain_iterator;
298 template<bool, bool, bool, bool, bool, bool>
299 friend class defusechain_instr_iterator;
300
301 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
302 /// register.
303 using reg_iterator =
304 defusechain_iterator<true, true, false, true, false, false>;
reg_begin(Register RegNo)305 reg_iterator reg_begin(Register RegNo) const {
306 return reg_iterator(getRegUseDefListHead(RegNo));
307 }
reg_end()308 static reg_iterator reg_end() { return reg_iterator(nullptr); }
309
reg_operands(Register Reg)310 inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
311 return make_range(reg_begin(Reg), reg_end());
312 }
313
314 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
315 /// of the specified register, stepping by MachineInstr.
316 using reg_instr_iterator =
317 defusechain_instr_iterator<true, true, false, false, true, false>;
reg_instr_begin(Register RegNo)318 reg_instr_iterator reg_instr_begin(Register RegNo) const {
319 return reg_instr_iterator(getRegUseDefListHead(RegNo));
320 }
reg_instr_end()321 static reg_instr_iterator reg_instr_end() {
322 return reg_instr_iterator(nullptr);
323 }
324
325 inline iterator_range<reg_instr_iterator>
reg_instructions(Register Reg)326 reg_instructions(Register Reg) const {
327 return make_range(reg_instr_begin(Reg), reg_instr_end());
328 }
329
330 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
331 /// of the specified register, stepping by bundle.
332 using reg_bundle_iterator =
333 defusechain_instr_iterator<true, true, false, false, false, true>;
reg_bundle_begin(Register RegNo)334 reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
335 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
336 }
reg_bundle_end()337 static reg_bundle_iterator reg_bundle_end() {
338 return reg_bundle_iterator(nullptr);
339 }
340
reg_bundles(Register Reg)341 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
342 return make_range(reg_bundle_begin(Reg), reg_bundle_end());
343 }
344
345 /// reg_empty - Return true if there are no instructions using or defining the
346 /// specified register (it may be live-in).
reg_empty(Register RegNo)347 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
348
349 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
350 /// of the specified register, skipping those marked as Debug.
351 using reg_nodbg_iterator =
352 defusechain_iterator<true, true, true, true, false, false>;
reg_nodbg_begin(Register RegNo)353 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const {
354 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
355 }
reg_nodbg_end()356 static reg_nodbg_iterator reg_nodbg_end() {
357 return reg_nodbg_iterator(nullptr);
358 }
359
360 inline iterator_range<reg_nodbg_iterator>
reg_nodbg_operands(Register Reg)361 reg_nodbg_operands(Register Reg) const {
362 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
363 }
364
365 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
366 /// all defs and uses of the specified register, stepping by MachineInstr,
367 /// skipping those marked as Debug.
368 using reg_instr_nodbg_iterator =
369 defusechain_instr_iterator<true, true, true, false, true, false>;
reg_instr_nodbg_begin(Register RegNo)370 reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
371 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
372 }
reg_instr_nodbg_end()373 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
374 return reg_instr_nodbg_iterator(nullptr);
375 }
376
377 inline iterator_range<reg_instr_nodbg_iterator>
reg_nodbg_instructions(Register Reg)378 reg_nodbg_instructions(Register Reg) const {
379 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
380 }
381
382 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
383 /// all defs and uses of the specified register, stepping by bundle,
384 /// skipping those marked as Debug.
385 using reg_bundle_nodbg_iterator =
386 defusechain_instr_iterator<true, true, true, false, false, true>;
reg_bundle_nodbg_begin(Register RegNo)387 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
388 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
389 }
reg_bundle_nodbg_end()390 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
391 return reg_bundle_nodbg_iterator(nullptr);
392 }
393
394 inline iterator_range<reg_bundle_nodbg_iterator>
reg_nodbg_bundles(Register Reg)395 reg_nodbg_bundles(Register Reg) const {
396 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
397 }
398
399 /// reg_nodbg_empty - Return true if the only instructions using or defining
400 /// Reg are Debug instructions.
reg_nodbg_empty(Register RegNo)401 bool reg_nodbg_empty(Register RegNo) const {
402 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
403 }
404
405 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
406 using def_iterator =
407 defusechain_iterator<false, true, false, true, false, false>;
def_begin(Register RegNo)408 def_iterator def_begin(Register RegNo) const {
409 return def_iterator(getRegUseDefListHead(RegNo));
410 }
def_end()411 static def_iterator def_end() { return def_iterator(nullptr); }
412
def_operands(Register Reg)413 inline iterator_range<def_iterator> def_operands(Register Reg) const {
414 return make_range(def_begin(Reg), def_end());
415 }
416
417 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
418 /// specified register, stepping by MachineInst.
419 using def_instr_iterator =
420 defusechain_instr_iterator<false, true, false, false, true, false>;
def_instr_begin(Register RegNo)421 def_instr_iterator def_instr_begin(Register RegNo) const {
422 return def_instr_iterator(getRegUseDefListHead(RegNo));
423 }
def_instr_end()424 static def_instr_iterator def_instr_end() {
425 return def_instr_iterator(nullptr);
426 }
427
428 inline iterator_range<def_instr_iterator>
def_instructions(Register Reg)429 def_instructions(Register Reg) const {
430 return make_range(def_instr_begin(Reg), def_instr_end());
431 }
432
433 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
434 /// specified register, stepping by bundle.
435 using def_bundle_iterator =
436 defusechain_instr_iterator<false, true, false, false, false, true>;
def_bundle_begin(Register RegNo)437 def_bundle_iterator def_bundle_begin(Register RegNo) const {
438 return def_bundle_iterator(getRegUseDefListHead(RegNo));
439 }
def_bundle_end()440 static def_bundle_iterator def_bundle_end() {
441 return def_bundle_iterator(nullptr);
442 }
443
def_bundles(Register Reg)444 inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
445 return make_range(def_bundle_begin(Reg), def_bundle_end());
446 }
447
448 /// def_empty - Return true if there are no instructions defining the
449 /// specified register (it may be live-in).
def_empty(Register RegNo)450 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
451
getVRegName(Register Reg)452 StringRef getVRegName(Register Reg) const {
453 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
454 }
455
insertVRegByName(StringRef Name,Register Reg)456 void insertVRegByName(StringRef Name, Register Reg) {
457 assert((Name.empty() || !VRegNames.contains(Name)) &&
458 "Named VRegs Must be Unique.");
459 if (!Name.empty()) {
460 VRegNames.insert(Name);
461 VReg2Name.grow(Reg);
462 VReg2Name[Reg] = Name.str();
463 }
464 }
465
466 /// Return true if there is exactly one operand defining the specified
467 /// register.
hasOneDef(Register RegNo)468 bool hasOneDef(Register RegNo) const {
469 return hasSingleElement(def_operands(RegNo));
470 }
471
472 /// Returns the defining operand if there is exactly one operand defining the
473 /// specified register, otherwise nullptr.
getOneDef(Register Reg)474 MachineOperand *getOneDef(Register Reg) const {
475 def_iterator DI = def_begin(Reg);
476 if (DI == def_end()) // No defs.
477 return nullptr;
478
479 def_iterator OneDef = DI;
480 if (++DI == def_end())
481 return &*OneDef;
482 return nullptr; // Multiple defs.
483 }
484
485 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
486 using use_iterator =
487 defusechain_iterator<true, false, false, true, false, false>;
use_begin(Register RegNo)488 use_iterator use_begin(Register RegNo) const {
489 return use_iterator(getRegUseDefListHead(RegNo));
490 }
use_end()491 static use_iterator use_end() { return use_iterator(nullptr); }
492
use_operands(Register Reg)493 inline iterator_range<use_iterator> use_operands(Register Reg) const {
494 return make_range(use_begin(Reg), use_end());
495 }
496
497 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
498 /// specified register, stepping by MachineInstr.
499 using use_instr_iterator =
500 defusechain_instr_iterator<true, false, false, false, true, false>;
use_instr_begin(Register RegNo)501 use_instr_iterator use_instr_begin(Register RegNo) const {
502 return use_instr_iterator(getRegUseDefListHead(RegNo));
503 }
use_instr_end()504 static use_instr_iterator use_instr_end() {
505 return use_instr_iterator(nullptr);
506 }
507
508 inline iterator_range<use_instr_iterator>
use_instructions(Register Reg)509 use_instructions(Register Reg) const {
510 return make_range(use_instr_begin(Reg), use_instr_end());
511 }
512
513 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
514 /// specified register, stepping by bundle.
515 using use_bundle_iterator =
516 defusechain_instr_iterator<true, false, false, false, false, true>;
use_bundle_begin(Register RegNo)517 use_bundle_iterator use_bundle_begin(Register RegNo) const {
518 return use_bundle_iterator(getRegUseDefListHead(RegNo));
519 }
use_bundle_end()520 static use_bundle_iterator use_bundle_end() {
521 return use_bundle_iterator(nullptr);
522 }
523
use_bundles(Register Reg)524 inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
525 return make_range(use_bundle_begin(Reg), use_bundle_end());
526 }
527
528 /// use_empty - Return true if there are no instructions using the specified
529 /// register.
use_empty(Register RegNo)530 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
531
532 /// hasOneUse - Return true if there is exactly one instruction using the
533 /// specified register.
hasOneUse(Register RegNo)534 bool hasOneUse(Register RegNo) const {
535 return hasSingleElement(use_operands(RegNo));
536 }
537
538 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
539 /// specified register, skipping those marked as Debug.
540 using use_nodbg_iterator =
541 defusechain_iterator<true, false, true, true, false, false>;
use_nodbg_begin(Register RegNo)542 use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
543 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
544 }
use_nodbg_end()545 static use_nodbg_iterator use_nodbg_end() {
546 return use_nodbg_iterator(nullptr);
547 }
548
549 inline iterator_range<use_nodbg_iterator>
use_nodbg_operands(Register Reg)550 use_nodbg_operands(Register Reg) const {
551 return make_range(use_nodbg_begin(Reg), use_nodbg_end());
552 }
553
554 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
555 /// all uses of the specified register, stepping by MachineInstr, skipping
556 /// those marked as Debug.
557 using use_instr_nodbg_iterator =
558 defusechain_instr_iterator<true, false, true, false, true, false>;
use_instr_nodbg_begin(Register RegNo)559 use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
560 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
561 }
use_instr_nodbg_end()562 static use_instr_nodbg_iterator use_instr_nodbg_end() {
563 return use_instr_nodbg_iterator(nullptr);
564 }
565
566 inline iterator_range<use_instr_nodbg_iterator>
use_nodbg_instructions(Register Reg)567 use_nodbg_instructions(Register Reg) const {
568 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
569 }
570
571 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
572 /// all uses of the specified register, stepping by bundle, skipping
573 /// those marked as Debug.
574 using use_bundle_nodbg_iterator =
575 defusechain_instr_iterator<true, false, true, false, false, true>;
use_bundle_nodbg_begin(Register RegNo)576 use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
577 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
578 }
use_bundle_nodbg_end()579 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
580 return use_bundle_nodbg_iterator(nullptr);
581 }
582
583 inline iterator_range<use_bundle_nodbg_iterator>
use_nodbg_bundles(Register Reg)584 use_nodbg_bundles(Register Reg) const {
585 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
586 }
587
588 /// use_nodbg_empty - Return true if there are no non-Debug instructions
589 /// using the specified register.
use_nodbg_empty(Register RegNo)590 bool use_nodbg_empty(Register RegNo) const {
591 return use_nodbg_begin(RegNo) == use_nodbg_end();
592 }
593
594 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
595 /// use of the specified register.
596 bool hasOneNonDBGUse(Register RegNo) const;
597
598 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
599 /// instruction using the specified register. Said instruction may have
600 /// multiple uses.
601 bool hasOneNonDBGUser(Register RegNo) const;
602
603
604 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
605 /// non-debug user instructions.
606 bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
607
608 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
609 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
610 /// except that it also changes any definitions of the register as well.
611 ///
612 /// Note that it is usually necessary to first constrain ToReg's register
613 /// class and register bank to match the FromReg constraints using one of the
614 /// methods:
615 ///
616 /// constrainRegClass(ToReg, getRegClass(FromReg))
617 /// constrainRegAttrs(ToReg, FromReg)
618 /// RegisterBankInfo::constrainGenericRegister(ToReg,
619 /// *MRI.getRegClass(FromReg), MRI)
620 ///
621 /// These functions will return a falsy result if the virtual registers have
622 /// incompatible constraints.
623 ///
624 /// Note that if ToReg is a physical register the function will replace and
625 /// apply sub registers to ToReg in order to obtain a final/proper physical
626 /// register.
627 void replaceRegWith(Register FromReg, Register ToReg);
628
629 /// getVRegDef - Return the machine instr that defines the specified virtual
630 /// register or null if none is found. This assumes that the code is in SSA
631 /// form, so there should only be one definition.
632 MachineInstr *getVRegDef(Register Reg) const;
633
634 /// getUniqueVRegDef - Return the unique machine instr that defines the
635 /// specified virtual register or null if none is found. If there are
636 /// multiple definitions or no definition, return null.
637 MachineInstr *getUniqueVRegDef(Register Reg) const;
638
639 /// clearKillFlags - Iterate over all the uses of the given register and
640 /// clear the kill flag from the MachineOperand. This function is used by
641 /// optimization passes which extend register lifetimes and need only
642 /// preserve conservative kill flag information.
643 void clearKillFlags(Register Reg) const;
644
645 void dumpUses(Register RegNo) const;
646
647 /// Returns true if PhysReg is unallocatable and constant throughout the
648 /// function. Writing to a constant register has no effect.
649 bool isConstantPhysReg(MCRegister PhysReg) const;
650
651 /// Get an iterator over the pressure sets affected by the given physical or
652 /// virtual register. If RegUnit is physical, it must be a register unit (from
653 /// MCRegUnitIterator).
654 PSetIterator getPressureSets(Register RegUnit) const;
655
656 //===--------------------------------------------------------------------===//
657 // Virtual Register Info
658 //===--------------------------------------------------------------------===//
659
660 /// Return the register class of the specified virtual register.
661 /// This shouldn't be used directly unless \p Reg has a register class.
662 /// \see getRegClassOrNull when this might happen.
getRegClass(Register Reg)663 const TargetRegisterClass *getRegClass(Register Reg) const {
664 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) &&
665 "Register class not set, wrong accessor");
666 return cast<const TargetRegisterClass *>(VRegInfo[Reg.id()].first);
667 }
668
669 /// Return the register class of \p Reg, or null if Reg has not been assigned
670 /// a register class yet.
671 ///
672 /// \note A null register class can only happen when these two
673 /// conditions are met:
674 /// 1. Generic virtual registers are created.
675 /// 2. The machine function has not completely been through the
676 /// instruction selection process.
677 /// None of this condition is possible without GlobalISel for now.
678 /// In other words, if GlobalISel is not used or if the query happens after
679 /// the select pass, using getRegClass is safe.
getRegClassOrNull(Register Reg)680 const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
681 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
682 return dyn_cast_if_present<const TargetRegisterClass *>(Val);
683 }
684
685 /// Return the register bank of \p Reg, or null if Reg has not been assigned
686 /// a register bank or has been assigned a register class.
687 /// \note It is possible to get the register bank from the register class via
688 /// RegisterBankInfo::getRegBankFromRegClass.
getRegBankOrNull(Register Reg)689 const RegisterBank *getRegBankOrNull(Register Reg) const {
690 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
691 return dyn_cast_if_present<const RegisterBank *>(Val);
692 }
693
694 /// Return the register bank or register class of \p Reg.
695 /// \note Before the register bank gets assigned (i.e., before the
696 /// RegBankSelect pass) \p Reg may not have either.
getRegClassOrRegBank(Register Reg)697 const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
698 return VRegInfo[Reg].first;
699 }
700
701 /// setRegClass - Set the register class of the specified virtual register.
702 void setRegClass(Register Reg, const TargetRegisterClass *RC);
703
704 /// Set the register bank to \p RegBank for \p Reg.
705 void setRegBank(Register Reg, const RegisterBank &RegBank);
706
setRegClassOrRegBank(Register Reg,const RegClassOrRegBank & RCOrRB)707 void setRegClassOrRegBank(Register Reg,
708 const RegClassOrRegBank &RCOrRB){
709 VRegInfo[Reg].first = RCOrRB;
710 }
711
712 /// constrainRegClass - Constrain the register class of the specified virtual
713 /// register to be a common subclass of RC and the current register class,
714 /// but only if the new class has at least MinNumRegs registers. Return the
715 /// new register class, or NULL if no such class exists.
716 /// This should only be used when the constraint is known to be trivial, like
717 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
718 ///
719 /// \note Assumes that the register has a register class assigned.
720 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
721 /// InstructionSelect pass and constrainRegAttrs in every other pass,
722 /// including non-select passes of GlobalISel, instead.
723 const TargetRegisterClass *constrainRegClass(Register Reg,
724 const TargetRegisterClass *RC,
725 unsigned MinNumRegs = 0);
726
727 /// Constrain the register class or the register bank of the virtual register
728 /// \p Reg (and low-level type) to be a common subclass or a common bank of
729 /// both registers provided respectively (and a common low-level type). Do
730 /// nothing if any of the attributes (classes, banks, or low-level types) of
731 /// the registers are deemed incompatible, or if the resulting register will
732 /// have a class smaller than before and of size less than \p MinNumRegs.
733 /// Return true if such register attributes exist, false otherwise.
734 ///
735 /// \note Use this method instead of constrainRegClass and
736 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
737 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
738 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
739 unsigned MinNumRegs = 0);
740
741 /// recomputeRegClass - Try to find a legal super-class of Reg's register
742 /// class that still satisfies the constraints from the instructions using
743 /// Reg. Returns true if Reg was upgraded.
744 ///
745 /// This method can be used after constraints have been removed from a
746 /// virtual register, for example after removing instructions or splitting
747 /// the live range.
748 bool recomputeRegClass(Register Reg);
749
750 /// createVirtualRegister - Create and return a new virtual register in the
751 /// function with the specified register class.
752 Register createVirtualRegister(const TargetRegisterClass *RegClass,
753 StringRef Name = "");
754
755 /// Create and return a new virtual register in the function with the same
756 /// attributes as the given register.
757 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
758
759 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
760 /// (target independent) virtual register.
getType(Register Reg)761 LLT getType(Register Reg) const {
762 if (Reg.isVirtual() && VRegToType.inBounds(Reg))
763 return VRegToType[Reg];
764 return LLT{};
765 }
766
767 /// Set the low-level type of \p VReg to \p Ty.
768 void setType(Register VReg, LLT Ty);
769
770 /// Create and return a new generic virtual register with low-level
771 /// type \p Ty.
772 Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
773
774 /// Remove all types associated to virtual registers (after instruction
775 /// selection and constraining of all generic virtual registers).
776 void clearVirtRegTypes();
777
778 /// Creates a new virtual register that has no register class, register bank
779 /// or size assigned yet. This is only allowed to be used
780 /// temporarily while constructing machine instructions. Most operations are
781 /// undefined on an incomplete register until one of setRegClass(),
782 /// setRegBank() or setSize() has been called on it.
783 Register createIncompleteVirtualRegister(StringRef Name = "");
784
785 /// getNumVirtRegs - Return the number of virtual registers created.
getNumVirtRegs()786 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
787
788 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
789 void clearVirtRegs();
790
791 /// setRegAllocationHint - Specify a register allocation hint for the
792 /// specified virtual register. This is typically used by target, and in case
793 /// of an earlier hint it will be overwritten.
setRegAllocationHint(Register VReg,unsigned Type,Register PrefReg)794 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
795 assert(VReg.isVirtual());
796 RegAllocHints[VReg].first = Type;
797 RegAllocHints[VReg].second.clear();
798 RegAllocHints[VReg].second.push_back(PrefReg);
799 }
800
801 /// addRegAllocationHint - Add a register allocation hint to the hints
802 /// vector for VReg.
addRegAllocationHint(Register VReg,Register PrefReg)803 void addRegAllocationHint(Register VReg, Register PrefReg) {
804 assert(VReg.isVirtual());
805 RegAllocHints[VReg].second.push_back(PrefReg);
806 }
807
808 /// Specify the preferred (target independent) register allocation hint for
809 /// the specified virtual register.
setSimpleHint(Register VReg,Register PrefReg)810 void setSimpleHint(Register VReg, Register PrefReg) {
811 setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
812 }
813
clearSimpleHint(Register VReg)814 void clearSimpleHint(Register VReg) {
815 assert (!RegAllocHints[VReg].first &&
816 "Expected to clear a non-target hint!");
817 RegAllocHints[VReg].second.clear();
818 }
819
820 /// getRegAllocationHint - Return the register allocation hint for the
821 /// specified virtual register. If there are many hints, this returns the
822 /// one with the greatest weight.
getRegAllocationHint(Register VReg)823 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const {
824 assert(VReg.isVirtual());
825 Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
826 RegAllocHints[VReg.id()].second[0] : Register());
827 return {RegAllocHints[VReg.id()].first, BestHint};
828 }
829
830 /// getSimpleHint - same as getRegAllocationHint except it will only return
831 /// a target independent hint.
getSimpleHint(Register VReg)832 Register getSimpleHint(Register VReg) const {
833 assert(VReg.isVirtual());
834 std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg);
835 return Hint.first ? Register() : Hint.second;
836 }
837
838 /// getRegAllocationHints - Return a reference to the vector of all
839 /// register allocation hints for VReg.
840 const std::pair<unsigned, SmallVector<Register, 4>> &
getRegAllocationHints(Register VReg)841 getRegAllocationHints(Register VReg) const {
842 assert(VReg.isVirtual());
843 return RegAllocHints[VReg];
844 }
845
846 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
847 /// specified register as undefined which causes the DBG_VALUE to be
848 /// deleted during LiveDebugVariables analysis.
849 void markUsesInDebugValueAsUndef(Register Reg) const;
850
851 /// updateDbgUsersToReg - Update a collection of debug instructions
852 /// to refer to the designated register.
updateDbgUsersToReg(MCRegister OldReg,MCRegister NewReg,ArrayRef<MachineInstr * > Users)853 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg,
854 ArrayRef<MachineInstr *> Users) const {
855 // If this operand is a register, check whether it overlaps with OldReg.
856 // If it does, replace with NewReg.
857 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
858 if (Op.isReg() &&
859 getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
860 Op.setReg(NewReg);
861 };
862
863 // Iterate through (possibly several) operands to DBG_VALUEs and update
864 // each. For DBG_PHIs, only one operand will be present.
865 for (MachineInstr *MI : Users) {
866 if (MI->isDebugValue()) {
867 for (auto &Op : MI->debug_operands())
868 UpdateOp(Op);
869 assert(MI->hasDebugOperandForReg(NewReg) &&
870 "Expected debug value to have some overlap with OldReg");
871 } else if (MI->isDebugPHI()) {
872 UpdateOp(MI->getOperand(0));
873 } else {
874 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
875 }
876 }
877 }
878
879 /// Return true if the specified register is modified in this function.
880 /// This checks that no defining machine operands exist for the register or
881 /// any of its aliases. Definitions found on functions marked noreturn are
882 /// ignored, to consider them pass 'true' for optional parameter
883 /// SkipNoReturnDef. The register is also considered modified when it is set
884 /// in the UsedPhysRegMask.
885 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
886
887 /// Return true if the specified register is modified or read in this
888 /// function. This checks that no machine operands exist for the register or
889 /// any of its aliases. If SkipRegMaskTest is false, the register is
890 /// considered used when it is set in the UsedPhysRegMask.
891 bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
892
893 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
894 /// This corresponds to the bit mask attached to register mask operands.
addPhysRegsUsedFromRegMask(const uint32_t * RegMask)895 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
896 UsedPhysRegMask.setBitsNotInMask(RegMask);
897 }
898
getUsedPhysRegsMask()899 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
900
901 //===--------------------------------------------------------------------===//
902 // Reserved Register Info
903 //===--------------------------------------------------------------------===//
904 //
905 // The set of reserved registers must be invariant during register
906 // allocation. For example, the target cannot suddenly decide it needs a
907 // frame pointer when the register allocator has already used the frame
908 // pointer register for something else.
909 //
910 // These methods can be used by target hooks like hasFP() to avoid changing
911 // the reserved register set during register allocation.
912
913 /// freezeReservedRegs - Called by the register allocator to freeze the set
914 /// of reserved registers before allocation begins.
915 void freezeReservedRegs(const MachineFunction&);
916
917 /// reserveReg -- Mark a register as reserved so checks like isAllocatable
918 /// will not suggest using it. This should not be used during the middle
919 /// of a function walk, or when liveness info is available.
reserveReg(MCRegister PhysReg,const TargetRegisterInfo * TRI)920 void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) {
921 assert(reservedRegsFrozen() &&
922 "Reserved registers haven't been frozen yet. ");
923 MCRegAliasIterator R(PhysReg, TRI, true);
924
925 for (; R.isValid(); ++R)
926 ReservedRegs.set(*R);
927 }
928
929 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
930 /// to ensure the set of reserved registers stays constant.
reservedRegsFrozen()931 bool reservedRegsFrozen() const {
932 return !ReservedRegs.empty();
933 }
934
935 /// canReserveReg - Returns true if PhysReg can be used as a reserved
936 /// register. Any register can be reserved before freezeReservedRegs() is
937 /// called.
canReserveReg(MCRegister PhysReg)938 bool canReserveReg(MCRegister PhysReg) const {
939 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
940 }
941
942 /// getReservedRegs - Returns a reference to the frozen set of reserved
943 /// registers. This method should always be preferred to calling
944 /// TRI::getReservedRegs() when possible.
getReservedRegs()945 const BitVector &getReservedRegs() const {
946 assert(reservedRegsFrozen() &&
947 "Reserved registers haven't been frozen yet. "
948 "Use TRI::getReservedRegs().");
949 return ReservedRegs;
950 }
951
952 /// isReserved - Returns true when PhysReg is a reserved register.
953 ///
954 /// Reserved registers may belong to an allocatable register class, but the
955 /// target has explicitly requested that they are not used.
isReserved(MCRegister PhysReg)956 bool isReserved(MCRegister PhysReg) const {
957 return getReservedRegs().test(PhysReg.id());
958 }
959
960 /// Returns true when the given register unit is considered reserved.
961 ///
962 /// Register units are considered reserved when for at least one of their
963 /// root registers, the root register and all super registers are reserved.
964 /// This currently iterates the register hierarchy and may be slower than
965 /// expected.
966 bool isReservedRegUnit(unsigned Unit) const;
967
968 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
969 /// register class and it hasn't been reserved.
970 ///
971 /// Allocatable registers may show up in the allocation order of some virtual
972 /// register, so a register allocator needs to track its liveness and
973 /// availability.
isAllocatable(MCRegister PhysReg)974 bool isAllocatable(MCRegister PhysReg) const {
975 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
976 !isReserved(PhysReg);
977 }
978
979 //===--------------------------------------------------------------------===//
980 // LiveIn Management
981 //===--------------------------------------------------------------------===//
982
983 /// addLiveIn - Add the specified register as a live-in. Note that it
984 /// is an error to add the same register to the same set more than once.
985 void addLiveIn(MCRegister Reg, Register vreg = Register()) {
986 LiveIns.push_back(std::make_pair(Reg, vreg));
987 }
988
989 // Iteration support for the live-ins set. It's kept in sorted order
990 // by register number.
991 using livein_iterator =
992 std::vector<std::pair<MCRegister,Register>>::const_iterator;
livein_begin()993 livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_end()994 livein_iterator livein_end() const { return LiveIns.end(); }
livein_empty()995 bool livein_empty() const { return LiveIns.empty(); }
996
liveins()997 ArrayRef<std::pair<MCRegister, Register>> liveins() const {
998 return LiveIns;
999 }
1000
1001 bool isLiveIn(Register Reg) const;
1002
1003 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
1004 /// corresponding live-in physical register.
1005 MCRegister getLiveInPhysReg(Register VReg) const;
1006
1007 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
1008 /// corresponding live-in virtual register.
1009 Register getLiveInVirtReg(MCRegister PReg) const;
1010
1011 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
1012 /// into the given entry block.
1013 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
1014 const TargetRegisterInfo &TRI,
1015 const TargetInstrInfo &TII);
1016
1017 /// Returns a mask covering all bits that can appear in lane masks of
1018 /// subregisters of the virtual register @p Reg.
1019 LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
1020
1021 /// defusechain_iterator - This class provides iterator support for machine
1022 /// operands in the function that use or define a specific register. If
1023 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1024 /// returns defs. If neither are true then you are silly and it always
1025 /// returns end(). If SkipDebug is true it skips uses marked Debug
1026 /// when incrementing.
1027 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1028 bool ByInstr, bool ByBundle>
1029 class defusechain_iterator {
1030 friend class MachineRegisterInfo;
1031
1032 public:
1033 using iterator_category = std::forward_iterator_tag;
1034 using value_type = MachineOperand;
1035 using difference_type = std::ptrdiff_t;
1036 using pointer = value_type *;
1037 using reference = value_type &;
1038
1039 private:
1040 MachineOperand *Op = nullptr;
1041
defusechain_iterator(MachineOperand * op)1042 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1043 // If the first node isn't one we're interested in, advance to one that
1044 // we are interested in.
1045 if (op) {
1046 if ((!ReturnUses && op->isUse()) ||
1047 (!ReturnDefs && op->isDef()) ||
1048 (SkipDebug && op->isDebug()))
1049 advance();
1050 }
1051 }
1052
advance()1053 void advance() {
1054 assert(Op && "Cannot increment end iterator!");
1055 Op = getNextOperandForReg(Op);
1056
1057 // All defs come before the uses, so stop def_iterator early.
1058 if (!ReturnUses) {
1059 if (Op) {
1060 if (Op->isUse())
1061 Op = nullptr;
1062 else
1063 assert(!Op->isDebug() && "Can't have debug defs");
1064 }
1065 } else {
1066 // If this is an operand we don't care about, skip it.
1067 while (Op && ((!ReturnDefs && Op->isDef()) ||
1068 (SkipDebug && Op->isDebug())))
1069 Op = getNextOperandForReg(Op);
1070 }
1071 }
1072
1073 public:
1074 defusechain_iterator() = default;
1075
1076 bool operator==(const defusechain_iterator &x) const {
1077 return Op == x.Op;
1078 }
1079 bool operator!=(const defusechain_iterator &x) const {
1080 return !operator==(x);
1081 }
1082
1083 /// atEnd - return true if this iterator is equal to reg_end() on the value.
atEnd()1084 bool atEnd() const { return Op == nullptr; }
1085
1086 // Iterator traversal: forward iteration only
1087 defusechain_iterator &operator++() { // Preincrement
1088 assert(Op && "Cannot increment end iterator!");
1089 if (ByOperand)
1090 advance();
1091 else if (ByInstr) {
1092 MachineInstr *P = Op->getParent();
1093 do {
1094 advance();
1095 } while (Op && Op->getParent() == P);
1096 } else if (ByBundle) {
1097 MachineBasicBlock::instr_iterator P =
1098 getBundleStart(Op->getParent()->getIterator());
1099 do {
1100 advance();
1101 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1102 }
1103
1104 return *this;
1105 }
1106 defusechain_iterator operator++(int) { // Postincrement
1107 defusechain_iterator tmp = *this; ++*this; return tmp;
1108 }
1109
1110 /// getOperandNo - Return the operand # of this MachineOperand in its
1111 /// MachineInstr.
getOperandNo()1112 unsigned getOperandNo() const {
1113 assert(Op && "Cannot dereference end iterator!");
1114 return Op - &Op->getParent()->getOperand(0);
1115 }
1116
1117 // Retrieve a reference to the current operand.
1118 MachineOperand &operator*() const {
1119 assert(Op && "Cannot dereference end iterator!");
1120 return *Op;
1121 }
1122
1123 MachineOperand *operator->() const {
1124 assert(Op && "Cannot dereference end iterator!");
1125 return Op;
1126 }
1127 };
1128
1129 /// defusechain_iterator - This class provides iterator support for machine
1130 /// operands in the function that use or define a specific register. If
1131 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1132 /// returns defs. If neither are true then you are silly and it always
1133 /// returns end(). If SkipDebug is true it skips uses marked Debug
1134 /// when incrementing.
1135 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1136 bool ByInstr, bool ByBundle>
1137 class defusechain_instr_iterator {
1138 friend class MachineRegisterInfo;
1139
1140 public:
1141 using iterator_category = std::forward_iterator_tag;
1142 using value_type = MachineInstr;
1143 using difference_type = std::ptrdiff_t;
1144 using pointer = value_type *;
1145 using reference = value_type &;
1146
1147 private:
1148 MachineOperand *Op = nullptr;
1149
defusechain_instr_iterator(MachineOperand * op)1150 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1151 // If the first node isn't one we're interested in, advance to one that
1152 // we are interested in.
1153 if (op) {
1154 if ((!ReturnUses && op->isUse()) ||
1155 (!ReturnDefs && op->isDef()) ||
1156 (SkipDebug && op->isDebug()))
1157 advance();
1158 }
1159 }
1160
advance()1161 void advance() {
1162 assert(Op && "Cannot increment end iterator!");
1163 Op = getNextOperandForReg(Op);
1164
1165 // All defs come before the uses, so stop def_iterator early.
1166 if (!ReturnUses) {
1167 if (Op) {
1168 if (Op->isUse())
1169 Op = nullptr;
1170 else
1171 assert(!Op->isDebug() && "Can't have debug defs");
1172 }
1173 } else {
1174 // If this is an operand we don't care about, skip it.
1175 while (Op && ((!ReturnDefs && Op->isDef()) ||
1176 (SkipDebug && Op->isDebug())))
1177 Op = getNextOperandForReg(Op);
1178 }
1179 }
1180
1181 public:
1182 defusechain_instr_iterator() = default;
1183
1184 bool operator==(const defusechain_instr_iterator &x) const {
1185 return Op == x.Op;
1186 }
1187 bool operator!=(const defusechain_instr_iterator &x) const {
1188 return !operator==(x);
1189 }
1190
1191 /// atEnd - return true if this iterator is equal to reg_end() on the value.
atEnd()1192 bool atEnd() const { return Op == nullptr; }
1193
1194 // Iterator traversal: forward iteration only
1195 defusechain_instr_iterator &operator++() { // Preincrement
1196 assert(Op && "Cannot increment end iterator!");
1197 if (ByOperand)
1198 advance();
1199 else if (ByInstr) {
1200 MachineInstr *P = Op->getParent();
1201 do {
1202 advance();
1203 } while (Op && Op->getParent() == P);
1204 } else if (ByBundle) {
1205 MachineBasicBlock::instr_iterator P =
1206 getBundleStart(Op->getParent()->getIterator());
1207 do {
1208 advance();
1209 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1210 }
1211
1212 return *this;
1213 }
1214 defusechain_instr_iterator operator++(int) { // Postincrement
1215 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1216 }
1217
1218 // Retrieve a reference to the current operand.
1219 MachineInstr &operator*() const {
1220 assert(Op && "Cannot dereference end iterator!");
1221 if (ByBundle)
1222 return *getBundleStart(Op->getParent()->getIterator());
1223 return *Op->getParent();
1224 }
1225
1226 MachineInstr *operator->() const { return &operator*(); }
1227 };
1228 };
1229
1230 /// Iterate over the pressure sets affected by the given physical or virtual
1231 /// register. If Reg is physical, it must be a register unit (from
1232 /// MCRegUnitIterator).
1233 class PSetIterator {
1234 const int *PSet = nullptr;
1235 unsigned Weight = 0;
1236
1237 public:
1238 PSetIterator() = default;
1239
PSetIterator(Register RegUnit,const MachineRegisterInfo * MRI)1240 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) {
1241 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1242 if (RegUnit.isVirtual()) {
1243 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1244 PSet = TRI->getRegClassPressureSets(RC);
1245 Weight = TRI->getRegClassWeight(RC).RegWeight;
1246 } else {
1247 PSet = TRI->getRegUnitPressureSets(RegUnit);
1248 Weight = TRI->getRegUnitWeight(RegUnit);
1249 }
1250 if (*PSet == -1)
1251 PSet = nullptr;
1252 }
1253
isValid()1254 bool isValid() const { return PSet; }
1255
getWeight()1256 unsigned getWeight() const { return Weight; }
1257
1258 unsigned operator*() const { return *PSet; }
1259
1260 void operator++() {
1261 assert(isValid() && "Invalid PSetIterator.");
1262 ++PSet;
1263 if (*PSet == -1)
1264 PSet = nullptr;
1265 }
1266 };
1267
1268 inline PSetIterator
getPressureSets(Register RegUnit)1269 MachineRegisterInfo::getPressureSets(Register RegUnit) const {
1270 return PSetIterator(RegUnit, this);
1271 }
1272
1273 } // end namespace llvm
1274
1275 #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
1276