1 //===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone enum definitions for the RISCV target
10 // useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "RISCVBaseInfo.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/Triple.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/RISCVISAInfo.h"
21 #include "llvm/Support/TargetParser.h"
22 #include "llvm/Support/raw_ostream.h"
23
24 namespace llvm {
25
26 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
27
28 namespace RISCVSysReg {
29 #define GET_SysRegsList_IMPL
30 #include "RISCVGenSearchableTables.inc"
31 } // namespace RISCVSysReg
32
33 namespace RISCVInsnOpcode {
34 #define GET_RISCVOpcodesList_IMPL
35 #include "RISCVGenSearchableTables.inc"
36 } // namespace RISCVInsnOpcode
37
38 namespace RISCVABI {
computeTargetABI(const Triple & TT,FeatureBitset FeatureBits,StringRef ABIName)39 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
40 StringRef ABIName) {
41 auto TargetABI = getTargetABI(ABIName);
42 bool IsRV64 = TT.isArch64Bit();
43 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
44
45 if (!ABIName.empty() && TargetABI == ABI_Unknown) {
46 errs()
47 << "'" << ABIName
48 << "' is not a recognized ABI for this target (ignoring target-abi)\n";
49 } else if (ABIName.startswith("ilp32") && IsRV64) {
50 errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
51 "target-abi)\n";
52 TargetABI = ABI_Unknown;
53 } else if (ABIName.startswith("lp64") && !IsRV64) {
54 errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
55 "target-abi)\n";
56 TargetABI = ABI_Unknown;
57 } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
58 // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
59 errs()
60 << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
61 TargetABI = ABI_Unknown;
62 }
63
64 if (TargetABI != ABI_Unknown)
65 return TargetABI;
66
67 // If no explicit ABI is given, try to compute the default ABI.
68 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
69 if (!ISAInfo)
70 report_fatal_error(ISAInfo.takeError());
71 return getTargetABI((*ISAInfo)->computeDefaultABI());
72 }
73
getTargetABI(StringRef ABIName)74 ABI getTargetABI(StringRef ABIName) {
75 auto TargetABI = StringSwitch<ABI>(ABIName)
76 .Case("ilp32", ABI_ILP32)
77 .Case("ilp32f", ABI_ILP32F)
78 .Case("ilp32d", ABI_ILP32D)
79 .Case("ilp32e", ABI_ILP32E)
80 .Case("lp64", ABI_LP64)
81 .Case("lp64f", ABI_LP64F)
82 .Case("lp64d", ABI_LP64D)
83 .Default(ABI_Unknown);
84 return TargetABI;
85 }
86
87 // To avoid the BP value clobbered by a function call, we need to choose a
88 // callee saved register to save the value. RV32E only has X8 and X9 as callee
89 // saved registers and X8 will be used as fp. So we choose X9 as bp.
getBPReg()90 MCRegister getBPReg() { return RISCV::X9; }
91
92 // Returns the register holding shadow call stack pointer.
getSCSPReg()93 MCRegister getSCSPReg() { return RISCV::X18; }
94
95 } // namespace RISCVABI
96
97 namespace RISCVFeatures {
98
validate(const Triple & TT,const FeatureBitset & FeatureBits)99 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
100 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
101 report_fatal_error("RV64 target requires an RV64 CPU");
102 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
103 report_fatal_error("RV32 target requires an RV32 CPU");
104 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
105 report_fatal_error("RV32E can't be enabled for an RV64 target");
106 if (FeatureBits[RISCV::Feature32Bit] &&
107 FeatureBits[RISCV::Feature64Bit])
108 report_fatal_error("RV32 and RV64 can't be combined");
109 }
110
111 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
parseFeatureBits(bool IsRV64,const FeatureBitset & FeatureBits)112 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
113 unsigned XLen = IsRV64 ? 64 : 32;
114 std::vector<std::string> FeatureVector;
115 // Convert FeatureBitset to FeatureVector.
116 for (auto Feature : RISCVFeatureKV) {
117 if (FeatureBits[Feature.Value] &&
118 llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
119 FeatureVector.push_back(std::string("+") + Feature.Key);
120 }
121 return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
122 }
123
124 } // namespace RISCVFeatures
125
126 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
127 // is used by our MC layer representation.
128 //
129 // Bits | Name | Description
130 // -----+------------+------------------------------------------------
131 // 7 | vma | Vector mask agnostic
132 // 6 | vta | Vector tail agnostic
133 // 5:3 | vsew[2:0] | Standard element width (SEW) setting
134 // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
encodeVTYPE(RISCVII::VLMUL VLMUL,unsigned SEW,bool TailAgnostic,bool MaskAgnostic)135 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
136 bool TailAgnostic, bool MaskAgnostic) {
137 assert(isValidSEW(SEW) && "Invalid SEW");
138 unsigned VLMULBits = static_cast<unsigned>(VLMUL);
139 unsigned VSEWBits = encodeSEW(SEW);
140 unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
141 if (TailAgnostic)
142 VTypeI |= 0x40;
143 if (MaskAgnostic)
144 VTypeI |= 0x80;
145
146 return VTypeI;
147 }
148
decodeVLMUL(RISCVII::VLMUL VLMUL)149 std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
150 switch (VLMUL) {
151 default:
152 llvm_unreachable("Unexpected LMUL value!");
153 case RISCVII::VLMUL::LMUL_1:
154 case RISCVII::VLMUL::LMUL_2:
155 case RISCVII::VLMUL::LMUL_4:
156 case RISCVII::VLMUL::LMUL_8:
157 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
158 case RISCVII::VLMUL::LMUL_F2:
159 case RISCVII::VLMUL::LMUL_F4:
160 case RISCVII::VLMUL::LMUL_F8:
161 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
162 }
163 }
164
printVType(unsigned VType,raw_ostream & OS)165 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
166 unsigned Sew = getSEW(VType);
167 OS << "e" << Sew;
168
169 unsigned LMul;
170 bool Fractional;
171 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
172
173 if (Fractional)
174 OS << ", mf";
175 else
176 OS << ", m";
177 OS << LMul;
178
179 if (isTailAgnostic(VType))
180 OS << ", ta";
181 else
182 OS << ", tu";
183
184 if (isMaskAgnostic(VType))
185 OS << ", ma";
186 else
187 OS << ", mu";
188 }
189
getSEWLMULRatio(unsigned SEW,RISCVII::VLMUL VLMul)190 unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
191 unsigned LMul;
192 bool Fractional;
193 std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
194
195 // Convert LMul to a fixed point value with 3 fractional bits.
196 LMul = Fractional ? (8 / LMul) : (LMul * 8);
197
198 assert(SEW >= 8 && "Unexpected SEW value");
199 return (SEW * 8) / LMul;
200 }
201
202 // Include the auto-generated portion of the compress emitter.
203 #define GEN_UNCOMPRESS_INSTR
204 #define GEN_COMPRESS_INSTR
205 #include "RISCVGenCompressInstEmitter.inc"
206
compress(MCInst & OutInst,const MCInst & MI,const MCSubtargetInfo & STI)207 bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
208 const MCSubtargetInfo &STI) {
209 return compressInst(OutInst, MI, STI);
210 }
211
uncompress(MCInst & OutInst,const MCInst & MI,const MCSubtargetInfo & STI)212 bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
213 const MCSubtargetInfo &STI) {
214 return uncompressInst(OutInst, MI, STI);
215 }
216
217 } // namespace llvm
218