1 /*
2 * SiFive PLIC (Platform Level Interrupt Controller)
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * This provides a parameterizable interrupt controller based on SiFive's PLIC.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "qemu/error-report.h"
26 #include "hw/sysbus.h"
27 #include "hw/pci/msi.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/intc/sifive_plic.h"
30 #include "target/riscv/cpu.h"
31 #include "migration/vmstate.h"
32 #include "hw/irq.h"
33 #include "sysemu/kvm.h"
34
addr_between(uint32_t addr,uint32_t base,uint32_t num)35 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
36 {
37 return addr >= base && addr - base < num;
38 }
39
char_to_mode(char c)40 static PLICMode char_to_mode(char c)
41 {
42 switch (c) {
43 case 'U': return PLICMode_U;
44 case 'S': return PLICMode_S;
45 case 'M': return PLICMode_M;
46 default:
47 error_report("plic: invalid mode '%c'", c);
48 exit(1);
49 }
50 }
51
atomic_set_masked(uint32_t * a,uint32_t mask,uint32_t value)52 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
53 {
54 uint32_t old, new, cmp = qatomic_read(a);
55
56 do {
57 old = cmp;
58 new = (old & ~mask) | (value & mask);
59 cmp = qatomic_cmpxchg(a, old, new);
60 } while (old != cmp);
61
62 return old;
63 }
64
sifive_plic_set_pending(SiFivePLICState * plic,int irq,bool level)65 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
66 {
67 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
68 }
69
sifive_plic_set_claimed(SiFivePLICState * plic,int irq,bool level)70 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
71 {
72 atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
73 }
74
sifive_plic_claimed(SiFivePLICState * plic,uint32_t addrid)75 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
76 {
77 uint32_t max_irq = 0;
78 uint32_t max_prio = plic->target_priority[addrid];
79 int i, j;
80 int num_irq_in_word = 32;
81
82 for (i = 0; i < plic->bitfield_words; i++) {
83 uint32_t pending_enabled_not_claimed =
84 (plic->pending[i] & ~plic->claimed[i]) &
85 plic->enable[addrid * plic->bitfield_words + i];
86
87 if (!pending_enabled_not_claimed) {
88 continue;
89 }
90
91 if (i == (plic->bitfield_words - 1)) {
92 /*
93 * If plic->num_sources is not multiple of 32, num-of-irq in last
94 * word is not 32. Compute the num-of-irq of last word to avoid
95 * out-of-bound access of source_priority array.
96 */
97 num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5);
98 }
99
100 for (j = 0; j < num_irq_in_word; j++) {
101 int irq = (i << 5) + j;
102 uint32_t prio = plic->source_priority[irq];
103 int enabled = pending_enabled_not_claimed & (1 << j);
104
105 if (enabled && prio > max_prio) {
106 max_irq = irq;
107 max_prio = prio;
108 }
109 }
110 }
111
112 return max_irq;
113 }
114
sifive_plic_update(SiFivePLICState * plic)115 static void sifive_plic_update(SiFivePLICState *plic)
116 {
117 int addrid;
118
119 /* raise irq on harts where this irq is enabled */
120 for (addrid = 0; addrid < plic->num_addrs; addrid++) {
121 uint32_t hartid = plic->addr_config[addrid].hartid;
122 PLICMode mode = plic->addr_config[addrid].mode;
123 bool level = !!sifive_plic_claimed(plic, addrid);
124
125 switch (mode) {
126 case PLICMode_M:
127 qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level);
128 break;
129 case PLICMode_S:
130 qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level);
131 break;
132 default:
133 break;
134 }
135 }
136 }
137
sifive_plic_read(void * opaque,hwaddr addr,unsigned size)138 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
139 {
140 SiFivePLICState *plic = opaque;
141
142 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
143 uint32_t irq = (addr - plic->priority_base) >> 2;
144
145 return plic->source_priority[irq];
146 } else if (addr_between(addr, plic->pending_base,
147 (plic->num_sources + 31) >> 3)) {
148 uint32_t word = (addr - plic->pending_base) >> 2;
149
150 return plic->pending[word];
151 } else if (addr_between(addr, plic->enable_base,
152 plic->num_addrs * plic->enable_stride)) {
153 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
154 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
155
156 if (wordid < plic->bitfield_words) {
157 return plic->enable[addrid * plic->bitfield_words + wordid];
158 }
159 } else if (addr_between(addr, plic->context_base,
160 plic->num_addrs * plic->context_stride)) {
161 uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
162 uint32_t contextid = (addr & (plic->context_stride - 1));
163
164 if (contextid == 0) {
165 return plic->target_priority[addrid];
166 } else if (contextid == 4) {
167 uint32_t max_irq = sifive_plic_claimed(plic, addrid);
168
169 if (max_irq) {
170 sifive_plic_set_pending(plic, max_irq, false);
171 sifive_plic_set_claimed(plic, max_irq, true);
172 }
173
174 sifive_plic_update(plic);
175 return max_irq;
176 }
177 }
178
179 qemu_log_mask(LOG_GUEST_ERROR,
180 "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
181 __func__, addr);
182 return 0;
183 }
184
sifive_plic_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)185 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
186 unsigned size)
187 {
188 SiFivePLICState *plic = opaque;
189
190 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
191 uint32_t irq = (addr - plic->priority_base) >> 2;
192 if (irq == 0) {
193 /* IRQ 0 source prioority is reserved */
194 qemu_log_mask(LOG_GUEST_ERROR,
195 "%s: Invalid source priority write 0x%"
196 HWADDR_PRIx "\n", __func__, addr);
197 return;
198 } else if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
199 /*
200 * if "num_priorities + 1" is power-of-2, make each register bit of
201 * interrupt priority WARL (Write-Any-Read-Legal). Just filter
202 * out the access to unsupported priority bits.
203 */
204 plic->source_priority[irq] = value % (plic->num_priorities + 1);
205 sifive_plic_update(plic);
206 } else if (value <= plic->num_priorities) {
207 plic->source_priority[irq] = value;
208 sifive_plic_update(plic);
209 }
210 } else if (addr_between(addr, plic->pending_base,
211 (plic->num_sources + 31) >> 3)) {
212 qemu_log_mask(LOG_GUEST_ERROR,
213 "%s: invalid pending write: 0x%" HWADDR_PRIx "",
214 __func__, addr);
215 } else if (addr_between(addr, plic->enable_base,
216 plic->num_addrs * plic->enable_stride)) {
217 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
218 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
219
220 if (wordid < plic->bitfield_words) {
221 plic->enable[addrid * plic->bitfield_words + wordid] = value;
222 } else {
223 qemu_log_mask(LOG_GUEST_ERROR,
224 "%s: Invalid enable write 0x%" HWADDR_PRIx "\n",
225 __func__, addr);
226 }
227 } else if (addr_between(addr, plic->context_base,
228 plic->num_addrs * plic->context_stride)) {
229 uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
230 uint32_t contextid = (addr & (plic->context_stride - 1));
231
232 if (contextid == 0) {
233 if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
234 /*
235 * if "num_priorities + 1" is power-of-2, each register bit of
236 * interrupt priority is WARL (Write-Any-Read-Legal). Just
237 * filter out the access to unsupported priority bits.
238 */
239 plic->target_priority[addrid] = value %
240 (plic->num_priorities + 1);
241 sifive_plic_update(plic);
242 } else if (value <= plic->num_priorities) {
243 plic->target_priority[addrid] = value;
244 sifive_plic_update(plic);
245 }
246 } else if (contextid == 4) {
247 if (value < plic->num_sources) {
248 sifive_plic_set_claimed(plic, value, false);
249 sifive_plic_update(plic);
250 }
251 } else {
252 qemu_log_mask(LOG_GUEST_ERROR,
253 "%s: Invalid context write 0x%" HWADDR_PRIx "\n",
254 __func__, addr);
255 }
256 } else {
257 qemu_log_mask(LOG_GUEST_ERROR,
258 "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
259 __func__, addr);
260 }
261 }
262
263 static const MemoryRegionOps sifive_plic_ops = {
264 .read = sifive_plic_read,
265 .write = sifive_plic_write,
266 .endianness = DEVICE_LITTLE_ENDIAN,
267 .valid = {
268 .min_access_size = 4,
269 .max_access_size = 4
270 }
271 };
272
sifive_plic_reset(DeviceState * dev)273 static void sifive_plic_reset(DeviceState *dev)
274 {
275 SiFivePLICState *s = SIFIVE_PLIC(dev);
276 int i;
277
278 memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
279 memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
280 memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
281 memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
282 memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
283
284 for (i = 0; i < s->num_harts; i++) {
285 qemu_set_irq(s->m_external_irqs[i], 0);
286 qemu_set_irq(s->s_external_irqs[i], 0);
287 }
288 }
289
290 /*
291 * parse PLIC hart/mode address offset config
292 *
293 * "M" 1 hart with M mode
294 * "MS,MS" 2 harts, 0-1 with M and S mode
295 * "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode
296 */
parse_hart_config(SiFivePLICState * plic)297 static void parse_hart_config(SiFivePLICState *plic)
298 {
299 int addrid, hartid, modes, m;
300 const char *p;
301 char c;
302
303 /* count and validate hart/mode combinations */
304 addrid = 0, hartid = 0, modes = 0;
305 p = plic->hart_config;
306 while ((c = *p++)) {
307 if (c == ',') {
308 if (modes) {
309 addrid += ctpop8(modes);
310 hartid++;
311 modes = 0;
312 }
313 } else {
314 m = 1 << char_to_mode(c);
315 if (modes == (modes | m)) {
316 error_report("plic: duplicate mode '%c' in config: %s",
317 c, plic->hart_config);
318 exit(1);
319 }
320 modes |= m;
321 }
322 }
323 if (modes) {
324 addrid += ctpop8(modes);
325 hartid++;
326 modes = 0;
327 }
328
329 plic->num_addrs = addrid;
330 plic->num_harts = hartid;
331
332 /* store hart/mode combinations */
333 plic->addr_config = g_new(PLICAddr, plic->num_addrs);
334 addrid = 0, hartid = plic->hartid_base;
335 p = plic->hart_config;
336 while ((c = *p++)) {
337 if (c == ',') {
338 if (modes) {
339 hartid++;
340 modes = 0;
341 }
342 } else {
343 m = char_to_mode(c);
344 plic->addr_config[addrid].addrid = addrid;
345 plic->addr_config[addrid].hartid = hartid;
346 plic->addr_config[addrid].mode = m;
347 modes |= (1 << m);
348 addrid++;
349 }
350 }
351 }
352
sifive_plic_irq_request(void * opaque,int irq,int level)353 static void sifive_plic_irq_request(void *opaque, int irq, int level)
354 {
355 SiFivePLICState *s = opaque;
356
357 if (level > 0) {
358 sifive_plic_set_pending(s, irq, true);
359 sifive_plic_update(s);
360 }
361 }
362
sifive_plic_realize(DeviceState * dev,Error ** errp)363 static void sifive_plic_realize(DeviceState *dev, Error **errp)
364 {
365 SiFivePLICState *s = SIFIVE_PLIC(dev);
366 int i;
367
368 memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
369 TYPE_SIFIVE_PLIC, s->aperture_size);
370 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
371
372 parse_hart_config(s);
373
374 if (!s->num_sources) {
375 error_setg(errp, "plic: invalid number of interrupt sources");
376 return;
377 }
378
379 s->bitfield_words = (s->num_sources + 31) >> 5;
380 s->num_enables = s->bitfield_words * s->num_addrs;
381 s->source_priority = g_new0(uint32_t, s->num_sources);
382 s->target_priority = g_new(uint32_t, s->num_addrs);
383 s->pending = g_new0(uint32_t, s->bitfield_words);
384 s->claimed = g_new0(uint32_t, s->bitfield_words);
385 s->enable = g_new0(uint32_t, s->num_enables);
386
387 qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
388
389 s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
390 qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
391
392 s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
393 qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
394
395 /*
396 * We can't allow the supervisor to control SEIP as this would allow the
397 * supervisor to clear a pending external interrupt which will result in
398 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
399 * hardware controlled when a PLIC is attached.
400 */
401 for (i = 0; i < s->num_harts; i++) {
402 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
403 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
404 error_setg(errp, "SEIP already claimed");
405 return;
406 }
407 }
408
409 msi_nonbroken = true;
410 }
411
412 static const VMStateDescription vmstate_sifive_plic = {
413 .name = "riscv_sifive_plic",
414 .version_id = 1,
415 .minimum_version_id = 1,
416 .fields = (const VMStateField[]) {
417 VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
418 num_sources, 0,
419 vmstate_info_uint32, uint32_t),
420 VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
421 num_addrs, 0,
422 vmstate_info_uint32, uint32_t),
423 VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
424 vmstate_info_uint32, uint32_t),
425 VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
426 vmstate_info_uint32, uint32_t),
427 VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
428 vmstate_info_uint32, uint32_t),
429 VMSTATE_END_OF_LIST()
430 }
431 };
432
433 static Property sifive_plic_properties[] = {
434 DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
435 DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
436 /* number of interrupt sources including interrupt source 0 */
437 DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
438 DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
439 /* interrupt priority register base starting from source 0 */
440 DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
441 DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
442 DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
443 DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
444 DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
445 DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
446 DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
447 DEFINE_PROP_END_OF_LIST(),
448 };
449
sifive_plic_class_init(ObjectClass * klass,void * data)450 static void sifive_plic_class_init(ObjectClass *klass, void *data)
451 {
452 DeviceClass *dc = DEVICE_CLASS(klass);
453
454 device_class_set_legacy_reset(dc, sifive_plic_reset);
455 device_class_set_props(dc, sifive_plic_properties);
456 dc->realize = sifive_plic_realize;
457 dc->vmsd = &vmstate_sifive_plic;
458 }
459
460 static const TypeInfo sifive_plic_info = {
461 .name = TYPE_SIFIVE_PLIC,
462 .parent = TYPE_SYS_BUS_DEVICE,
463 .instance_size = sizeof(SiFivePLICState),
464 .class_init = sifive_plic_class_init,
465 };
466
sifive_plic_register_types(void)467 static void sifive_plic_register_types(void)
468 {
469 type_register_static(&sifive_plic_info);
470 }
471
type_init(sifive_plic_register_types)472 type_init(sifive_plic_register_types)
473
474 /*
475 * Create PLIC device.
476 */
477 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
478 uint32_t num_harts,
479 uint32_t hartid_base, uint32_t num_sources,
480 uint32_t num_priorities, uint32_t priority_base,
481 uint32_t pending_base, uint32_t enable_base,
482 uint32_t enable_stride, uint32_t context_base,
483 uint32_t context_stride, uint32_t aperture_size)
484 {
485 DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
486 int i;
487 SiFivePLICState *plic;
488
489 assert(enable_stride == (enable_stride & -enable_stride));
490 assert(context_stride == (context_stride & -context_stride));
491 qdev_prop_set_string(dev, "hart-config", hart_config);
492 qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
493 qdev_prop_set_uint32(dev, "num-sources", num_sources);
494 qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
495 qdev_prop_set_uint32(dev, "priority-base", priority_base);
496 qdev_prop_set_uint32(dev, "pending-base", pending_base);
497 qdev_prop_set_uint32(dev, "enable-base", enable_base);
498 qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
499 qdev_prop_set_uint32(dev, "context-base", context_base);
500 qdev_prop_set_uint32(dev, "context-stride", context_stride);
501 qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
502 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
503 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
504
505 plic = SIFIVE_PLIC(dev);
506
507 for (i = 0; i < plic->num_addrs; i++) {
508 int cpu_num = plic->addr_config[i].hartid;
509 CPUState *cpu = qemu_get_cpu(cpu_num);
510
511 if (plic->addr_config[i].mode == PLICMode_M) {
512 qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
513 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
514 }
515 if (plic->addr_config[i].mode == PLICMode_S) {
516 qdev_connect_gpio_out(dev, cpu_num - hartid_base,
517 qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
518 }
519 }
520
521 return dev;
522 }
523