1 /* $NetBSD: i82365.c,v 1.116 2013/10/13 06:55:34 riz Exp $ */
2
3 /*
4 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Charles M. Hannum.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 */
20
21 /*
22 * Copyright (c) 2000 Christian E. Hopps. All rights reserved.
23 * Copyright (c) 1997 Marc Horowitz. All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
27 * are met:
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution.
33 * 3. All advertising materials mentioning features or use of this software
34 * must display the following acknowledgement:
35 * This product includes software developed by Marc Horowitz.
36 * 4. The name of the author may not be used to endorse or promote products
37 * derived from this software without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
40 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
41 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
42 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
44 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
48 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 */
50
51 #include <sys/cdefs.h>
52 __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.116 2013/10/13 06:55:34 riz Exp $");
53
54 #define PCICDEBUG
55
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/device.h>
59 #include <sys/extent.h>
60 #include <sys/kernel.h>
61 #include <sys/malloc.h>
62 #include <sys/kthread.h>
63
64 #include <sys/bus.h>
65 #include <sys/intr.h>
66
67 #include <dev/pcmcia/pcmciareg.h>
68 #include <dev/pcmcia/pcmciavar.h>
69
70 #include <dev/ic/i82365reg.h>
71 #include <dev/ic/i82365var.h>
72
73 #include "locators.h"
74
75 #ifdef PCICDEBUG
76 int pcic_debug = 0;
77 #define DPRINTF(arg) if (pcic_debug) printf arg;
78 #else
79 #define DPRINTF(arg)
80 #endif
81
82 /*
83 * Individual drivers will allocate their own memory and io regions. Memory
84 * regions must be a multiple of 4k, aligned on a 4k boundary.
85 */
86
87 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE
88
89 void pcic_attach_socket(struct pcic_handle *);
90 void pcic_attach_socket_finish(struct pcic_handle *);
91
92 int pcic_print (void *arg, const char *pnp);
93 int pcic_intr_socket(struct pcic_handle *);
94 void pcic_poll_intr(void *);
95
96 void pcic_attach_card(struct pcic_handle *);
97 void pcic_detach_card(struct pcic_handle *, int);
98 void pcic_deactivate_card(struct pcic_handle *);
99
100 void pcic_chip_do_mem_map(struct pcic_handle *, int);
101 void pcic_chip_do_io_map(struct pcic_handle *, int);
102
103 void pcic_event_thread(void *);
104
105 void pcic_queue_event(struct pcic_handle *, int);
106 void pcic_power(int, void *);
107
108 static int pcic_wait_ready(struct pcic_handle *);
109 static void pcic_delay(struct pcic_handle *, int, const char *);
110
111 static uint8_t st_pcic_read(struct pcic_handle *, int);
112 static void st_pcic_write(struct pcic_handle *, int, uint8_t);
113
114 int
pcic_ident_ok(int ident)115 pcic_ident_ok(int ident)
116 {
117
118 /* this is very empirical and heuristic */
119
120 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO))
121 return 0;
122
123 if ((ident & PCIC_IDENT_REV_MASK) == 0)
124 return 0;
125
126 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) {
127 #ifdef DIAGNOSTIC
128 printf("pcic: does not support memory and I/O cards, "
129 "ignored (ident=%0x)\n", ident);
130 #endif
131 return 0;
132 }
133
134 return 1;
135 }
136
137 int
pcic_vendor(struct pcic_handle * h)138 pcic_vendor(struct pcic_handle *h)
139 {
140 int reg;
141 int vendor;
142
143 reg = pcic_read(h, PCIC_IDENT);
144
145 if ((reg & PCIC_IDENT_REV_MASK) == 0)
146 return PCIC_VENDOR_NONE;
147
148 switch (reg) {
149 case 0x00:
150 case 0xff:
151 return PCIC_VENDOR_NONE;
152 case PCIC_IDENT_ID_INTEL0:
153 vendor = PCIC_VENDOR_I82365SLR0;
154 break;
155 case PCIC_IDENT_ID_INTEL1:
156 vendor = PCIC_VENDOR_I82365SLR1;
157 break;
158 case PCIC_IDENT_ID_INTEL2:
159 vendor = PCIC_VENDOR_I82365SL_DF;
160 break;
161 case PCIC_IDENT_ID_IBM1:
162 case PCIC_IDENT_ID_IBM2:
163 vendor = PCIC_VENDOR_IBM;
164 break;
165 case PCIC_IDENT_ID_IBM3:
166 vendor = PCIC_VENDOR_IBM_KING;
167 break;
168 default:
169 vendor = PCIC_VENDOR_UNKNOWN;
170 break;
171 }
172
173 if (vendor == PCIC_VENDOR_I82365SLR0 ||
174 vendor == PCIC_VENDOR_I82365SLR1) {
175 /*
176 * Check for Cirrus PD67xx.
177 * the chip_id of the cirrus toggles between 11 and 00 after a
178 * write. weird.
179 */
180 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0);
181 reg = pcic_read(h, -1);
182 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
183 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) {
184 reg = pcic_read(h, -1);
185 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0)
186 return PCIC_VENDOR_CIRRUS_PD67XX;
187 }
188
189 /*
190 * check for Ricoh RF5C[23]96
191 */
192 reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID);
193 switch (reg) {
194 case PCIC_RICOH_CHIP_ID_5C296:
195 return PCIC_VENDOR_RICOH_5C296;
196 case PCIC_RICOH_CHIP_ID_5C396:
197 return PCIC_VENDOR_RICOH_5C396;
198 }
199 }
200
201 return vendor;
202 }
203
204 const char *
pcic_vendor_to_string(int vendor)205 pcic_vendor_to_string(int vendor)
206 {
207
208 switch (vendor) {
209 case PCIC_VENDOR_I82365SLR0:
210 return "Intel 82365SL Revision 0";
211 case PCIC_VENDOR_I82365SLR1:
212 return "Intel 82365SL Revision 1";
213 case PCIC_VENDOR_CIRRUS_PD67XX:
214 return "Cirrus PD6710/2X";
215 case PCIC_VENDOR_I82365SL_DF:
216 return "Intel 82365SL-DF";
217 case PCIC_VENDOR_RICOH_5C296:
218 return "Ricoh RF5C296";
219 case PCIC_VENDOR_RICOH_5C396:
220 return "Ricoh RF5C396";
221 case PCIC_VENDOR_IBM:
222 return "IBM PCIC";
223 case PCIC_VENDOR_IBM_KING:
224 return "IBM KING";
225 }
226
227 return "Unknown controller";
228 }
229
230 void
pcic_attach(struct pcic_softc * sc)231 pcic_attach(struct pcic_softc *sc)
232 {
233 int i, reg, chip, socket;
234 struct pcic_handle *h;
235 device_t self;
236
237 DPRINTF(("pcic ident regs:"));
238
239 self = sc->dev;
240 mutex_init(&sc->sc_pcic_lock, MUTEX_DEFAULT, IPL_NONE);
241
242 /* find and configure for the available sockets */
243 for (i = 0; i < __arraycount(sc->handle); i++) {
244 h = &sc->handle[i];
245 chip = i / 2;
246 socket = i % 2;
247
248 h->ph_parent = self;
249 h->chip = chip;
250 h->socket = socket;
251 h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET;
252 h->laststate = PCIC_LASTSTATE_EMPTY;
253 /* initialize pcic_read and pcic_write functions */
254 h->ph_read = st_pcic_read;
255 h->ph_write = st_pcic_write;
256 h->ph_bus_t = sc->iot;
257 h->ph_bus_h = sc->ioh;
258 h->flags = 0;
259
260 /* need to read vendor -- for cirrus to report no xtra chip */
261 if (socket == 0) {
262 h->vendor = pcic_vendor(h);
263 if (i < __arraycount(sc->handle) - 1)
264 (h + 1)->vendor = h->vendor;
265 }
266
267 switch (h->vendor) {
268 case PCIC_VENDOR_NONE:
269 /* no chip */
270 continue;
271 case PCIC_VENDOR_CIRRUS_PD67XX:
272 reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO);
273 if (socket == 0 ||
274 (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS))
275 h->flags = PCIC_FLAG_SOCKETP;
276 break;
277 default:
278 /*
279 * During the socket probe, read the ident register
280 * twice. I don't understand why, but sometimes the
281 * clone chips in hpcmips boxes read all-0s the first
282 * time. -- mycroft
283 */
284 reg = pcic_read(h, PCIC_IDENT);
285 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg));
286 reg = pcic_read(h, PCIC_IDENT);
287 DPRINTF(("socket %d ident reg 0x%02x\n", i, reg));
288 if (pcic_ident_ok(reg))
289 h->flags = PCIC_FLAG_SOCKETP;
290 break;
291 }
292 }
293
294 for (i = 0; i < __arraycount(sc->handle); i++) {
295 h = &sc->handle[i];
296
297 if (h->flags & PCIC_FLAG_SOCKETP) {
298 SIMPLEQ_INIT(&h->events);
299
300 /* disable interrupts and leave socket in reset */
301 pcic_write(h, PCIC_INTR, 0);
302
303 /* zero out the address windows */
304 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
305
306 /* power down the socket */
307 pcic_write(h, PCIC_PWRCTL, 0);
308
309 pcic_write(h, PCIC_CSC_INTR, 0);
310 (void) pcic_read(h, PCIC_CSC);
311 }
312 }
313
314 /* print detected info */
315 for (i = 0; i < __arraycount(sc->handle) - 1; i += 2) {
316 h = &sc->handle[i];
317 chip = i / 2;
318
319 if (h->vendor == PCIC_VENDOR_NONE)
320 continue;
321
322 aprint_normal_dev(self, "controller %d (%s) has ",
323 chip, pcic_vendor_to_string(sc->handle[i].vendor));
324
325 if ((h->flags & PCIC_FLAG_SOCKETP) &&
326 ((h + 1)->flags & PCIC_FLAG_SOCKETP))
327 aprint_normal("sockets A and B\n");
328 else if (h->flags & PCIC_FLAG_SOCKETP)
329 aprint_normal("socket A only\n");
330 else if ((h + 1)->flags & PCIC_FLAG_SOCKETP)
331 aprint_normal("socket B only\n");
332 else
333 aprint_normal("no sockets\n");
334 }
335 }
336
337 /*
338 * attach the sockets before we know what interrupts we have
339 */
340 void
pcic_attach_sockets(struct pcic_softc * sc)341 pcic_attach_sockets(struct pcic_softc *sc)
342 {
343 int i;
344
345 for (i = 0; i < __arraycount(sc->handle); i++)
346 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
347 pcic_attach_socket(&sc->handle[i]);
348 }
349
350 void
pcic_power(int why,void * arg)351 pcic_power(int why, void *arg)
352 {
353 struct pcic_handle *h = arg;
354 struct pcic_softc *sc = device_private(h->ph_parent);
355 int reg;
356
357 DPRINTF(("%s: power: why %d\n", device_xname(h->ph_parent), why));
358
359 if (h->flags & PCIC_FLAG_SOCKETP) {
360 if ((why == PWR_RESUME) &&
361 (pcic_read(h, PCIC_CSC_INTR) == 0)) {
362 #ifdef PCICDEBUG
363 char bitbuf[64];
364 #endif
365 reg = PCIC_CSC_INTR_CD_ENABLE;
366 if (sc->irq != -1)
367 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;
368 pcic_write(h, PCIC_CSC_INTR, reg);
369 #ifdef PCICDEBUG
370 snprintb(bitbuf, sizeof(bitbuf), PCIC_CSC_INTR_FORMAT,
371 pcic_read(h, PCIC_CSC_INTR));
372 #endif
373 DPRINTF(("%s: CSC_INTR was zero; reset to %s\n",
374 device_xname(sc->dev), bitbuf));
375 }
376
377 /*
378 * check for card insertion or removal during suspend period.
379 * XXX: the code can't cope with card swap (remove then insert).
380 * how can we detect such situation?
381 */
382 if (why == PWR_RESUME)
383 (void)pcic_intr_socket(h);
384 }
385 }
386
387
388 /*
389 * attach a socket -- we don't know about irqs yet
390 */
391 void
pcic_attach_socket(struct pcic_handle * h)392 pcic_attach_socket(struct pcic_handle *h)
393 {
394 struct pcmciabus_attach_args paa;
395 struct pcic_softc *sc = device_private(h->ph_parent);
396 int locs[PCMCIABUSCF_NLOCS];
397
398 /* initialize the rest of the handle */
399
400 h->shutdown = 0;
401 h->memalloc = 0;
402 h->ioalloc = 0;
403 h->ih_irq = 0;
404
405 /* now, config one pcmcia device per socket */
406
407 paa.paa_busname = "pcmcia";
408 paa.pct = (pcmcia_chipset_tag_t) sc->pct;
409 paa.pch = (pcmcia_chipset_handle_t) h;
410
411 locs[PCMCIABUSCF_CONTROLLER] = h->chip;
412 locs[PCMCIABUSCF_SOCKET] = h->socket;
413
414 h->pcmcia = config_found_sm_loc(sc->dev, "pcmciabus", locs, &paa,
415 pcic_print, config_stdsubmatch);
416 if (h->pcmcia == NULL) {
417 h->flags &= ~PCIC_FLAG_SOCKETP;
418 return;
419 }
420
421 }
422
423 /*
424 * now finish attaching the sockets, we are ready to allocate
425 * interrupts
426 */
427 void
pcic_attach_sockets_finish(struct pcic_softc * sc)428 pcic_attach_sockets_finish(struct pcic_softc *sc)
429 {
430 int i;
431
432 for (i = 0; i < __arraycount(sc->handle); i++)
433 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
434 pcic_attach_socket_finish(&sc->handle[i]);
435 }
436
437 /*
438 * finishing attaching the socket. Interrupts may now be on
439 * if so expects the pcic interrupt to be blocked
440 */
441 void
pcic_attach_socket_finish(struct pcic_handle * h)442 pcic_attach_socket_finish(struct pcic_handle *h)
443 {
444 struct pcic_softc *sc = device_private(h->ph_parent);
445 int reg;
446 char cs[4];
447
448 DPRINTF(("%s: attach finish socket %ld\n", device_xname(h->ph_parent),
449 (long) (h - &sc->handle[0])));
450
451 /*
452 * Set up a powerhook to ensure it continues to interrupt on
453 * card detect even after suspend.
454 * (this works around a bug seen in suspend-to-disk on the
455 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved).
456 */
457 powerhook_establish(device_xname(h->ph_parent), pcic_power, h);
458
459 /* enable interrupts on card detect, poll for them if no irq avail */
460 reg = PCIC_CSC_INTR_CD_ENABLE;
461 if (sc->irq == -1) {
462 if (sc->poll_established == 0) {
463 callout_init(&sc->poll_ch, 0);
464 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc);
465 sc->poll_established = 1;
466 }
467 } else
468 reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;
469 pcic_write(h, PCIC_CSC_INTR, reg);
470
471 /* steer above mgmt interrupt to configured place */
472 if (sc->irq == 0)
473 pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE);
474
475 /* clear possible card detect interrupt */
476 (void) pcic_read(h, PCIC_CSC);
477
478 DPRINTF(("%s: attach finish vendor 0x%02x\n",
479 device_xname(h->ph_parent), h->vendor));
480
481 /* unsleep the cirrus controller */
482 if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) {
483 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
484 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
485 DPRINTF(("%s: socket %02x was suspended\n",
486 device_xname(h->ph_parent), h->sock));
487 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
488 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
489 }
490 }
491
492 /* if there's a card there, then attach it. */
493 reg = pcic_read(h, PCIC_IF_STATUS);
494 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
495 PCIC_IF_STATUS_CARDDETECT_PRESENT) {
496 pcic_queue_event(h, PCIC_EVENT_INSERTION);
497 h->laststate = PCIC_LASTSTATE_PRESENT;
498 } else {
499 h->laststate = PCIC_LASTSTATE_EMPTY;
500 }
501
502 /*
503 * queue creation of a kernel thread to handle insert/removal events.
504 */
505 #ifdef DIAGNOSTIC
506 if (h->event_thread != NULL)
507 panic("pcic_attach_socket: event thread");
508 #endif
509 config_pending_incr(sc->dev);
510 snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket);
511
512 if (kthread_create(PRI_NONE, 0, NULL, pcic_event_thread, h,
513 &h->event_thread, "%s,%s", device_xname(h->ph_parent), cs)) {
514 aprint_error_dev(h->ph_parent,
515 "unable to create event thread for sock 0x%02x\n", h->sock);
516 panic("pcic_attach_socket");
517 }
518 }
519
520 void
pcic_event_thread(void * arg)521 pcic_event_thread(void *arg)
522 {
523 struct pcic_handle *h = arg;
524 struct pcic_event *pe;
525 int s, first = 1;
526 struct pcic_softc *sc = device_private(h->ph_parent);
527
528 while (h->shutdown == 0) {
529 /*
530 * Serialize event processing on the PCIC. We may
531 * sleep while we hold this lock.
532 */
533 mutex_enter(&sc->sc_pcic_lock);
534
535 s = splhigh();
536 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
537 splx(s);
538 if (first) {
539 first = 0;
540 config_pending_decr(sc->dev);
541 }
542 /*
543 * No events to process; release the PCIC lock.
544 */
545 (void) mutex_exit(&sc->sc_pcic_lock);
546 (void) tsleep(&h->events, PWAIT, "pcicev", 0);
547 continue;
548 } else {
549 splx(s);
550 /* sleep .25s to be enqueued chatterling interrupts */
551 (void) tsleep((void *)pcic_event_thread, PWAIT,
552 "pcicss", hz / 4);
553 }
554 s = splhigh();
555 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
556 splx(s);
557
558 switch (pe->pe_type) {
559 case PCIC_EVENT_INSERTION:
560 s = splhigh();
561 for (;;) {
562 struct pcic_event *pe1, *pe2;
563
564 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
565 break;
566 if (pe1->pe_type != PCIC_EVENT_REMOVAL)
567 break;
568 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL)
569 break;
570 if (pe2->pe_type == PCIC_EVENT_INSERTION) {
571 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
572 free(pe1, M_TEMP);
573 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
574 free(pe2, M_TEMP);
575 }
576 }
577 splx(s);
578
579 DPRINTF(("%s: insertion event\n",
580 device_xname(h->ph_parent)));
581 pcic_attach_card(h);
582 break;
583
584 case PCIC_EVENT_REMOVAL:
585 s = splhigh();
586 for (;;) {
587 struct pcic_event *pe1, *pe2;
588
589 if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
590 break;
591 if (pe1->pe_type != PCIC_EVENT_INSERTION)
592 break;
593 if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL)
594 break;
595 if (pe2->pe_type == PCIC_EVENT_REMOVAL) {
596 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
597 free(pe1, M_TEMP);
598 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
599 free(pe2, M_TEMP);
600 }
601 }
602 splx(s);
603
604 DPRINTF(("%s: removal event\n",
605 device_xname(h->ph_parent)));
606 pcic_detach_card(h, DETACH_FORCE);
607 break;
608
609 default:
610 panic("pcic_event_thread: unknown event %d",
611 pe->pe_type);
612 }
613 free(pe, M_TEMP);
614
615 mutex_exit(&sc->sc_pcic_lock);
616 }
617
618 h->event_thread = NULL;
619
620 /* In case parent is waiting for us to exit. */
621 wakeup(sc);
622
623 kthread_exit(0);
624 }
625
626 int
pcic_print(void * arg,const char * pnp)627 pcic_print(void *arg, const char *pnp)
628 {
629 struct pcmciabus_attach_args *paa = arg;
630 struct pcic_handle *h = (struct pcic_handle *) paa->pch;
631
632 /* Only "pcmcia"s can attach to "pcic"s... easy. */
633 if (pnp)
634 aprint_normal("pcmcia at %s", pnp);
635
636 aprint_normal(" controller %d socket %d", h->chip, h->socket);
637
638 return UNCONF;
639 }
640
641 void
pcic_poll_intr(void * arg)642 pcic_poll_intr(void *arg)
643 {
644 struct pcic_softc *sc;
645 int i, s;
646
647 s = spltty();
648 sc = arg;
649 for (i = 0; i < __arraycount(sc->handle); i++)
650 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
651 (void)pcic_intr_socket(&sc->handle[i]);
652 callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc);
653 splx(s);
654 }
655
656 int
pcic_intr(void * arg)657 pcic_intr(void *arg)
658 {
659 struct pcic_softc *sc = arg;
660 int i, ret = 0;
661
662 DPRINTF(("%s: intr\n", device_xname(sc->dev)));
663
664 for (i = 0; i < __arraycount(sc->handle); i++)
665 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
666 ret += pcic_intr_socket(&sc->handle[i]);
667
668 return ret ? 1 : 0;
669 }
670
671 int
pcic_intr_socket(struct pcic_handle * h)672 pcic_intr_socket(struct pcic_handle *h)
673 {
674 int cscreg;
675
676 cscreg = pcic_read(h, PCIC_CSC);
677
678 cscreg &= (PCIC_CSC_GPI |
679 PCIC_CSC_CD |
680 PCIC_CSC_READY |
681 PCIC_CSC_BATTWARN |
682 PCIC_CSC_BATTDEAD);
683
684 if (cscreg & PCIC_CSC_GPI) {
685 DPRINTF(("%s: %02x GPI\n",
686 device_xname(h->ph_parent), h->sock));
687 }
688 if (cscreg & PCIC_CSC_CD) {
689 int statreg;
690
691 statreg = pcic_read(h, PCIC_IF_STATUS);
692
693 DPRINTF(("%s: %02x CD %x\n", device_xname(h->ph_parent),
694 h->sock, statreg));
695
696 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
697 PCIC_IF_STATUS_CARDDETECT_PRESENT) {
698 if (h->laststate != PCIC_LASTSTATE_PRESENT) {
699 DPRINTF(("%s: enqueing INSERTION event\n",
700 device_xname(h->ph_parent)));
701 pcic_queue_event(h, PCIC_EVENT_INSERTION);
702 }
703 h->laststate = PCIC_LASTSTATE_PRESENT;
704 } else {
705 if (h->laststate == PCIC_LASTSTATE_PRESENT) {
706 /* Deactivate the card now. */
707 DPRINTF(("%s: deactivating card\n",
708 device_xname(h->ph_parent)));
709 pcic_deactivate_card(h);
710
711 DPRINTF(("%s: enqueing REMOVAL event\n",
712 device_xname(h->ph_parent)));
713 pcic_queue_event(h, PCIC_EVENT_REMOVAL);
714 }
715 h->laststate = PCIC_LASTSTATE_EMPTY;
716 }
717 }
718 if (cscreg & PCIC_CSC_READY) {
719 DPRINTF(("%s: %02x READY\n", device_xname(h->ph_parent),
720 h->sock));
721 /* shouldn't happen */
722 }
723 if (cscreg & PCIC_CSC_BATTWARN) {
724 DPRINTF(("%s: %02x BATTWARN\n", device_xname(h->ph_parent),
725 h->sock));
726 }
727 if (cscreg & PCIC_CSC_BATTDEAD) {
728 DPRINTF(("%s: %02x BATTDEAD\n", device_xname(h->ph_parent),
729 h->sock));
730 }
731 return cscreg ? 1 : 0;
732 }
733
734 void
pcic_queue_event(struct pcic_handle * h,int event)735 pcic_queue_event(struct pcic_handle *h, int event)
736 {
737 struct pcic_event *pe;
738 int s;
739
740 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
741 if (pe == NULL)
742 panic("pcic_queue_event: can't allocate event");
743
744 pe->pe_type = event;
745 s = splhigh();
746 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
747 splx(s);
748 wakeup(&h->events);
749 }
750
751 void
pcic_attach_card(struct pcic_handle * h)752 pcic_attach_card(struct pcic_handle *h)
753 {
754
755 if ((h->flags & PCIC_FLAG_CARDP) == 0) {
756 /* call the MI attach function */
757 pcmcia_card_attach(h->pcmcia);
758
759 h->flags |= PCIC_FLAG_CARDP;
760 } else {
761 DPRINTF(("pcic_attach_card: already attached"));
762 }
763 }
764
765 void
pcic_detach_card(struct pcic_handle * h,int flags)766 pcic_detach_card(struct pcic_handle *h, int flags)
767 /* flags: DETACH_* */
768 {
769
770 if (h->flags & PCIC_FLAG_CARDP) {
771 h->flags &= ~PCIC_FLAG_CARDP;
772
773 /* call the MI detach function */
774 pcmcia_card_detach(h->pcmcia, flags);
775 } else {
776 DPRINTF(("pcic_detach_card: already detached"));
777 }
778 }
779
780 void
pcic_deactivate_card(struct pcic_handle * h)781 pcic_deactivate_card(struct pcic_handle *h)
782 {
783 int intr;
784
785 /* call the MI deactivate function */
786 pcmcia_card_deactivate(h->pcmcia);
787
788 /* reset the socket */
789 intr = pcic_read(h, PCIC_INTR);
790 intr &= PCIC_INTR_ENABLE;
791 pcic_write(h, PCIC_INTR, intr);
792
793 /* power down the socket */
794 pcic_write(h, PCIC_PWRCTL, 0);
795 }
796
797 int
pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch,bus_size_t size,struct pcmcia_mem_handle * pcmhp)798 pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
799 struct pcmcia_mem_handle *pcmhp)
800 {
801 struct pcic_handle *h = (struct pcic_handle *) pch;
802 bus_space_handle_t memh;
803 bus_addr_t addr;
804 bus_size_t sizepg;
805 int i, mask, mhandle;
806 struct pcic_softc *sc = device_private(h->ph_parent);
807
808 /* out of sc->memh, allocate as many pages as necessary */
809
810 /* convert size to PCIC pages */
811 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN;
812 if (sizepg > PCIC_MAX_MEM_PAGES)
813 return 1;
814
815 mask = (1 << sizepg) - 1;
816
817 addr = 0; /* XXX gcc -Wuninitialized */
818 mhandle = 0; /* XXX gcc -Wuninitialized */
819
820 for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) {
821 if ((sc->subregionmask & (mask << i)) == (mask << i)) {
822 if (bus_space_subregion(sc->memt, sc->memh,
823 i * PCIC_MEM_PAGESIZE,
824 sizepg * PCIC_MEM_PAGESIZE, &memh))
825 return 1;
826 mhandle = mask << i;
827 addr = sc->membase + (i * PCIC_MEM_PAGESIZE);
828 sc->subregionmask &= ~(mhandle);
829 pcmhp->memt = sc->memt;
830 pcmhp->memh = memh;
831 pcmhp->addr = addr;
832 pcmhp->size = size;
833 pcmhp->mhandle = mhandle;
834 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
835 return 0;
836 }
837 }
838
839 return 1;
840 }
841
842 void
pcic_chip_mem_free(pcmcia_chipset_handle_t pch,struct pcmcia_mem_handle * pcmhp)843 pcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp)
844 {
845 struct pcic_handle *h = (struct pcic_handle *) pch;
846 struct pcic_softc *sc = device_private(h->ph_parent);
847
848 sc->subregionmask |= pcmhp->mhandle;
849 }
850
851 static const struct mem_map_index_st {
852 int sysmem_start_lsb;
853 int sysmem_start_msb;
854 int sysmem_stop_lsb;
855 int sysmem_stop_msb;
856 int cardmem_lsb;
857 int cardmem_msb;
858 int memenable;
859 } mem_map_index[] = {
860 {
861 PCIC_SYSMEM_ADDR0_START_LSB,
862 PCIC_SYSMEM_ADDR0_START_MSB,
863 PCIC_SYSMEM_ADDR0_STOP_LSB,
864 PCIC_SYSMEM_ADDR0_STOP_MSB,
865 PCIC_CARDMEM_ADDR0_LSB,
866 PCIC_CARDMEM_ADDR0_MSB,
867 PCIC_ADDRWIN_ENABLE_MEM0,
868 },
869 {
870 PCIC_SYSMEM_ADDR1_START_LSB,
871 PCIC_SYSMEM_ADDR1_START_MSB,
872 PCIC_SYSMEM_ADDR1_STOP_LSB,
873 PCIC_SYSMEM_ADDR1_STOP_MSB,
874 PCIC_CARDMEM_ADDR1_LSB,
875 PCIC_CARDMEM_ADDR1_MSB,
876 PCIC_ADDRWIN_ENABLE_MEM1,
877 },
878 {
879 PCIC_SYSMEM_ADDR2_START_LSB,
880 PCIC_SYSMEM_ADDR2_START_MSB,
881 PCIC_SYSMEM_ADDR2_STOP_LSB,
882 PCIC_SYSMEM_ADDR2_STOP_MSB,
883 PCIC_CARDMEM_ADDR2_LSB,
884 PCIC_CARDMEM_ADDR2_MSB,
885 PCIC_ADDRWIN_ENABLE_MEM2,
886 },
887 {
888 PCIC_SYSMEM_ADDR3_START_LSB,
889 PCIC_SYSMEM_ADDR3_START_MSB,
890 PCIC_SYSMEM_ADDR3_STOP_LSB,
891 PCIC_SYSMEM_ADDR3_STOP_MSB,
892 PCIC_CARDMEM_ADDR3_LSB,
893 PCIC_CARDMEM_ADDR3_MSB,
894 PCIC_ADDRWIN_ENABLE_MEM3,
895 },
896 {
897 PCIC_SYSMEM_ADDR4_START_LSB,
898 PCIC_SYSMEM_ADDR4_START_MSB,
899 PCIC_SYSMEM_ADDR4_STOP_LSB,
900 PCIC_SYSMEM_ADDR4_STOP_MSB,
901 PCIC_CARDMEM_ADDR4_LSB,
902 PCIC_CARDMEM_ADDR4_MSB,
903 PCIC_ADDRWIN_ENABLE_MEM4,
904 },
905 };
906
907 void
pcic_chip_do_mem_map(struct pcic_handle * h,int win)908 pcic_chip_do_mem_map(struct pcic_handle *h, int win)
909 {
910 int reg;
911 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
912 int mem8 =
913 (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8
914 || (kind == PCMCIA_MEM_ATTR);
915
916 DPRINTF(("mem8 %d\n", mem8));
917 /* mem8 = 1; */
918
919 pcic_write(h, mem_map_index[win].sysmem_start_lsb,
920 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
921 pcic_write(h, mem_map_index[win].sysmem_start_msb,
922 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
923 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) |
924 (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT));
925
926 pcic_write(h, mem_map_index[win].sysmem_stop_lsb,
927 ((h->mem[win].addr + h->mem[win].size) >>
928 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
929 pcic_write(h, mem_map_index[win].sysmem_stop_msb,
930 (((h->mem[win].addr + h->mem[win].size) >>
931 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
932 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) |
933 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2);
934
935 pcic_write(h, mem_map_index[win].cardmem_lsb,
936 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff);
937 pcic_write(h, mem_map_index[win].cardmem_msb,
938 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) &
939 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) |
940 ((kind == PCMCIA_MEM_ATTR) ?
941 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0));
942
943 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
944 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
945 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
946
947 delay(100);
948
949 #ifdef PCICDEBUG
950 {
951 int r1, r2, r3, r4, r5, r6;
952
953 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb);
954 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb);
955 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb);
956 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb);
957 r5 = pcic_read(h, mem_map_index[win].cardmem_msb);
958 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb);
959
960 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x "
961 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6));
962 }
963 #endif
964 }
965
966 int
pcic_chip_mem_map(pcmcia_chipset_handle_t pch,int kind,bus_addr_t card_addr,bus_size_t size,struct pcmcia_mem_handle * pcmhp,bus_size_t * offsetp,int * windowp)967 pcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr,
968 bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp,
969 int *windowp)
970 {
971 struct pcic_handle *h = (struct pcic_handle *) pch;
972 bus_addr_t busaddr;
973 long card_offset;
974 int i, win;
975
976 win = -1;
977 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0]));
978 i++) {
979 if ((h->memalloc & (1 << i)) == 0) {
980 win = i;
981 h->memalloc |= (1 << i);
982 break;
983 }
984 }
985
986 if (win == -1)
987 return 1;
988
989 *windowp = win;
990
991 /* XXX this is pretty gross */
992
993 {
994 struct pcic_softc *sc = device_private(h->ph_parent);
995 if (!bus_space_is_equal(sc->memt, pcmhp->memt))
996 panic("pcic_chip_mem_map memt is bogus");
997 }
998
999 busaddr = pcmhp->addr;
1000
1001 /*
1002 * compute the address offset to the pcmcia address space for the
1003 * pcic. this is intentionally signed. The masks and shifts below
1004 * will cause TRT to happen in the pcic registers. Deal with making
1005 * sure the address is aligned, and return the alignment offset.
1006 */
1007
1008 *offsetp = card_addr % PCIC_MEM_ALIGN;
1009 card_addr -= *offsetp;
1010
1011 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
1012 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
1013 (u_long) card_addr));
1014
1015 /*
1016 * include the offset in the size, and decrement size by one, since
1017 * the hw wants start/stop
1018 */
1019 size += *offsetp - 1;
1020
1021 card_offset = (((long) card_addr) - ((long) busaddr));
1022
1023 h->mem[win].addr = busaddr;
1024 h->mem[win].size = size;
1025 h->mem[win].offset = card_offset;
1026 h->mem[win].kind = kind;
1027
1028 pcic_chip_do_mem_map(h, win);
1029
1030 return 0;
1031 }
1032
1033 void
pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch,int window)1034 pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
1035 {
1036 struct pcic_handle *h = (struct pcic_handle *) pch;
1037 int reg;
1038
1039 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0])))
1040 panic("pcic_chip_mem_unmap: window out of range");
1041
1042 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1043 reg &= ~mem_map_index[window].memenable;
1044 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1045
1046 h->memalloc &= ~(1 << window);
1047 }
1048
1049 int
pcic_chip_io_alloc(pcmcia_chipset_handle_t pch,bus_addr_t start,bus_size_t size,bus_size_t align,struct pcmcia_io_handle * pcihp)1050 pcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
1051 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
1052 {
1053 struct pcic_handle *h = (struct pcic_handle *) pch;
1054 bus_space_tag_t iot;
1055 bus_space_handle_t ioh;
1056 bus_addr_t ioaddr;
1057 int flags = 0;
1058 struct pcic_softc *sc = device_private(h->ph_parent);
1059
1060 /*
1061 * Allocate some arbitrary I/O space.
1062 */
1063
1064 iot = sc->iot;
1065
1066 if (start) {
1067 ioaddr = start;
1068 if (bus_space_map(iot, start, size, 0, &ioh))
1069 return 1;
1070 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n",
1071 (u_long) ioaddr, (u_long) size));
1072 } else {
1073 flags |= PCMCIA_IO_ALLOCATED;
1074 if (bus_space_alloc(iot, sc->iobase,
1075 sc->iobase + sc->iosize, size, align, 0, 0,
1076 &ioaddr, &ioh))
1077 return 1;
1078 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
1079 (u_long) ioaddr, (u_long) size));
1080 }
1081
1082 pcihp->iot = iot;
1083 pcihp->ioh = ioh;
1084 pcihp->addr = ioaddr;
1085 pcihp->size = size;
1086 pcihp->flags = flags;
1087
1088 return 0;
1089 }
1090
1091 void
pcic_chip_io_free(pcmcia_chipset_handle_t pch,struct pcmcia_io_handle * pcihp)1092 pcic_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp)
1093 {
1094 bus_space_tag_t iot = pcihp->iot;
1095 bus_space_handle_t ioh = pcihp->ioh;
1096 bus_size_t size = pcihp->size;
1097
1098 if (pcihp->flags & PCMCIA_IO_ALLOCATED)
1099 bus_space_free(iot, ioh, size);
1100 else
1101 bus_space_unmap(iot, ioh, size);
1102 }
1103
1104
1105 static const struct io_map_index_st {
1106 int start_lsb;
1107 int start_msb;
1108 int stop_lsb;
1109 int stop_msb;
1110 int ioenable;
1111 int ioctlmask;
1112 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */
1113 } io_map_index[] = {
1114 {
1115 PCIC_IOADDR0_START_LSB,
1116 PCIC_IOADDR0_START_MSB,
1117 PCIC_IOADDR0_STOP_LSB,
1118 PCIC_IOADDR0_STOP_MSB,
1119 PCIC_ADDRWIN_ENABLE_IO0,
1120 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
1121 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK,
1122 {
1123 PCIC_IOCTL_IO0_IOCS16SRC_CARD,
1124 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
1125 PCIC_IOCTL_IO0_DATASIZE_8BIT,
1126 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
1127 PCIC_IOCTL_IO0_DATASIZE_16BIT,
1128 },
1129 },
1130 {
1131 PCIC_IOADDR1_START_LSB,
1132 PCIC_IOADDR1_START_MSB,
1133 PCIC_IOADDR1_STOP_LSB,
1134 PCIC_IOADDR1_STOP_MSB,
1135 PCIC_ADDRWIN_ENABLE_IO1,
1136 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
1137 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK,
1138 {
1139 PCIC_IOCTL_IO1_IOCS16SRC_CARD,
1140 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
1141 PCIC_IOCTL_IO1_DATASIZE_8BIT,
1142 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
1143 PCIC_IOCTL_IO1_DATASIZE_16BIT,
1144 },
1145 },
1146 };
1147
1148 void
pcic_chip_do_io_map(struct pcic_handle * h,int win)1149 pcic_chip_do_io_map(struct pcic_handle *h, int win)
1150 {
1151 int reg;
1152
1153 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
1154 win, (long) h->io[win].addr, (long) h->io[win].size,
1155 h->io[win].width * 8));
1156
1157 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff);
1158 pcic_write(h, io_map_index[win].start_msb,
1159 (h->io[win].addr >> 8) & 0xff);
1160
1161 pcic_write(h, io_map_index[win].stop_lsb,
1162 (h->io[win].addr + h->io[win].size - 1) & 0xff);
1163 pcic_write(h, io_map_index[win].stop_msb,
1164 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff);
1165
1166 reg = pcic_read(h, PCIC_IOCTL);
1167 reg &= ~io_map_index[win].ioctlmask;
1168 reg |= io_map_index[win].ioctlbits[h->io[win].width];
1169 pcic_write(h, PCIC_IOCTL, reg);
1170
1171 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1172 reg |= io_map_index[win].ioenable;
1173 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1174 }
1175
1176 int
pcic_chip_io_map(pcmcia_chipset_handle_t pch,int width,bus_addr_t offset,bus_size_t size,struct pcmcia_io_handle * pcihp,int * windowp)1177 pcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
1178 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
1179 {
1180 struct pcic_handle *h = (struct pcic_handle *) pch;
1181 bus_addr_t ioaddr = pcihp->addr + offset;
1182 int i, win;
1183 #ifdef PCICDEBUG
1184 static const char *width_names[] = { "auto", "io8", "io16" };
1185 #endif
1186 struct pcic_softc *sc = device_private(h->ph_parent);
1187
1188 /* XXX Sanity check offset/size. */
1189
1190 win = -1;
1191 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) {
1192 if ((h->ioalloc & (1 << i)) == 0) {
1193 win = i;
1194 h->ioalloc |= (1 << i);
1195 break;
1196 }
1197 }
1198
1199 if (win == -1)
1200 return 1;
1201
1202 *windowp = win;
1203
1204 /* XXX this is pretty gross */
1205
1206 if (!bus_space_is_equal(sc->iot, pcihp->iot))
1207 panic("pcic_chip_io_map iot is bogus");
1208
1209 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n",
1210 win, width_names[width], (u_long) ioaddr, (u_long) size));
1211
1212 /* XXX wtf is this doing here? */
1213
1214 printf("%s: port 0x%lx", device_xname(sc->dev), (u_long) ioaddr);
1215 if (size > 1)
1216 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
1217 printf("\n");
1218
1219 h->io[win].addr = ioaddr;
1220 h->io[win].size = size;
1221 h->io[win].width = width;
1222
1223 pcic_chip_do_io_map(h, win);
1224
1225 return 0;
1226 }
1227
1228 void
pcic_chip_io_unmap(pcmcia_chipset_handle_t pch,int window)1229 pcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window)
1230 {
1231 struct pcic_handle *h = (struct pcic_handle *) pch;
1232 int reg;
1233
1234 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0])))
1235 panic("pcic_chip_io_unmap: window out of range");
1236
1237 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
1238 reg &= ~io_map_index[window].ioenable;
1239 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
1240
1241 h->ioalloc &= ~(1 << window);
1242 }
1243
1244 static int
pcic_wait_ready(struct pcic_handle * h)1245 pcic_wait_ready(struct pcic_handle *h)
1246 {
1247 uint8_t stat;
1248 int i;
1249
1250 /* wait an initial 10ms for quick cards */
1251 stat = pcic_read(h, PCIC_IF_STATUS);
1252 if (stat & PCIC_IF_STATUS_READY)
1253 return 0;
1254 pcic_delay(h, 10, "pccwr0");
1255 for (i = 0; i < 50; i++) {
1256 stat = pcic_read(h, PCIC_IF_STATUS);
1257 if (stat & PCIC_IF_STATUS_READY)
1258 return 0;
1259 if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) !=
1260 PCIC_IF_STATUS_CARDDETECT_PRESENT)
1261 return ENXIO;
1262 /* wait .1s (100ms) each iteration now */
1263 pcic_delay(h, 100, "pccwr1");
1264 }
1265
1266 printf("pcic_wait_ready: ready never happened, status=%02x\n", stat);
1267 return EWOULDBLOCK;
1268 }
1269
1270 /*
1271 * Perform long (msec order) delay.
1272 */
1273 static void
pcic_delay(struct pcic_handle * h,int timo,const char * wmesg)1274 pcic_delay(struct pcic_handle *h, int timo, const char *wmesg)
1275 /* timo: in ms. must not be zero */
1276 {
1277
1278 #ifdef DIAGNOSTIC
1279 if (timo <= 0)
1280 panic("pcic_delay: called with timeout %d", timo);
1281 if (!curlwp)
1282 panic("pcic_delay: called in interrupt context");
1283 if (!h->event_thread)
1284 panic("pcic_delay: no event thread");
1285 #endif
1286 DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n",
1287 wmesg, h->event_thread, timo));
1288 if (doing_shutdown)
1289 delay(timo * 1000);
1290 else
1291 tsleep(pcic_delay, PWAIT, wmesg,
1292 roundup(timo * hz, 1000) / 1000);
1293 }
1294
1295 void
pcic_chip_socket_enable(pcmcia_chipset_handle_t pch)1296 pcic_chip_socket_enable(pcmcia_chipset_handle_t pch)
1297 {
1298 struct pcic_handle *h = (struct pcic_handle *) pch;
1299 int win;
1300 uint8_t power, intr;
1301 #ifdef DIAGNOSTIC
1302 int reg;
1303 #endif
1304
1305 #ifdef DIAGNOSTIC
1306 if (h->flags & PCIC_FLAG_ENABLED)
1307 printf("pcic_chip_socket_enable: enabling twice\n");
1308 #endif
1309
1310 /* disable interrupts; assert RESET */
1311 intr = pcic_read(h, PCIC_INTR);
1312 intr &= PCIC_INTR_ENABLE;
1313 pcic_write(h, PCIC_INTR, intr);
1314
1315 /* zero out the address windows */
1316 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
1317
1318 /* power off; assert output enable bit */
1319 power = PCIC_PWRCTL_OE;
1320 pcic_write(h, PCIC_PWRCTL, power);
1321
1322 /*
1323 * power hack for RICOH RF5C[23]96
1324 */
1325 switch (h->vendor) {
1326 case PCIC_VENDOR_RICOH_5C296:
1327 case PCIC_VENDOR_RICOH_5C396:
1328 {
1329 int regtmp;
1330 regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2);
1331 #ifdef RICOH_POWER_HACK
1332 regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT;
1333 #else
1334 regtmp &=
1335 ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V);
1336 #endif
1337 pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp);
1338 }
1339 break;
1340 default:
1341 break;
1342 }
1343
1344 #ifdef VADEM_POWER_HACK
1345 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e);
1346 bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37);
1347 printf("prcr = %02x\n", pcic_read(h, 0x02));
1348 printf("cvsr = %02x\n", pcic_read(h, 0x2f));
1349 printf("DANGER WILL ROBINSON! Changing voltage select!\n");
1350 pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03);
1351 printf("cvsr = %02x\n", pcic_read(h, 0x2f));
1352 #endif
1353
1354 /* power up the socket */
1355 power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC;
1356 pcic_write(h, PCIC_PWRCTL, power);
1357
1358 /*
1359 * Table 4-18 and figure 4-6 of the PC Card specifiction say:
1360 * Vcc Rising Time (Tpr) = 100ms
1361 * RESET Width (Th (Hi-z RESET)) = 1ms
1362 * RESET Width (Tw (RESET)) = 10us
1363 *
1364 * some machines require some more time to be settled
1365 * (100ms is added here).
1366 */
1367 pcic_delay(h, 200 + 1, "pccen1");
1368
1369 /* negate RESET */
1370 intr |= PCIC_INTR_RESET;
1371 pcic_write(h, PCIC_INTR, intr);
1372
1373 /*
1374 * RESET Setup Time (Tsu (RESET)) = 20ms
1375 */
1376 pcic_delay(h, 20, "pccen2");
1377
1378 #ifdef DIAGNOSTIC
1379 reg = pcic_read(h, PCIC_IF_STATUS);
1380 if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0)
1381 printf("pcic_chip_socket_enable: no power, status=%x\n", reg);
1382 #endif
1383
1384 /* wait for the chip to finish initializing */
1385 if (pcic_wait_ready(h)) {
1386 /* XXX return a failure status?? */
1387 pcic_write(h, PCIC_PWRCTL, 0);
1388 return;
1389 }
1390
1391 /* reinstall all the memory and io mappings */
1392 for (win = 0; win < PCIC_MEM_WINS; win++)
1393 if (h->memalloc & (1 << win))
1394 pcic_chip_do_mem_map(h, win);
1395 for (win = 0; win < PCIC_IO_WINS; win++)
1396 if (h->ioalloc & (1 << win))
1397 pcic_chip_do_io_map(h, win);
1398
1399 h->flags |= PCIC_FLAG_ENABLED;
1400 }
1401
1402 void
pcic_chip_socket_disable(pcmcia_chipset_handle_t pch)1403 pcic_chip_socket_disable(pcmcia_chipset_handle_t pch)
1404 {
1405 struct pcic_handle *h = (struct pcic_handle *) pch;
1406 uint8_t intr;
1407
1408 DPRINTF(("pcic_chip_socket_disable\n"));
1409
1410 /* disable interrupts; assert RESET */
1411 intr = pcic_read(h, PCIC_INTR);
1412 intr &= PCIC_INTR_ENABLE;
1413 pcic_write(h, PCIC_INTR, intr);
1414
1415 /* zero out the address windows */
1416 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
1417
1418 /* disable socket: negate output enable bit and power off */
1419 pcic_write(h, PCIC_PWRCTL, 0);
1420
1421 /*
1422 * Vcc Falling Time (Tpf) = 300ms
1423 */
1424 pcic_delay(h, 300, "pccwr1");
1425
1426 h->flags &= ~PCIC_FLAG_ENABLED;
1427 }
1428
1429 void
pcic_chip_socket_settype(pcmcia_chipset_handle_t pch,int type)1430 pcic_chip_socket_settype(pcmcia_chipset_handle_t pch, int type)
1431 {
1432 struct pcic_handle *h = (struct pcic_handle *) pch;
1433 int intr;
1434
1435 intr = pcic_read(h, PCIC_INTR);
1436 intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK);
1437 if (type == PCMCIA_IFTYPE_IO) {
1438 intr |= PCIC_INTR_CARDTYPE_IO;
1439 intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT;
1440 } else
1441 intr |= PCIC_INTR_CARDTYPE_MEM;
1442 pcic_write(h, PCIC_INTR, intr);
1443
1444 DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n",
1445 device_xname(h->ph_parent), h->sock,
1446 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr));
1447 }
1448
1449 static uint8_t
st_pcic_read(struct pcic_handle * h,int idx)1450 st_pcic_read(struct pcic_handle *h, int idx)
1451 {
1452
1453 if (idx != -1)
1454 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
1455 h->sock + idx);
1456 return bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA);
1457 }
1458
1459 static void
st_pcic_write(struct pcic_handle * h,int idx,uint8_t data)1460 st_pcic_write(struct pcic_handle *h, int idx, uint8_t data)
1461 {
1462
1463 if (idx != -1)
1464 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX,
1465 h->sock + idx);
1466 bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data);
1467 }
1468