| /dports/sysutils/u-boot-rpi3/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_layerscape_gen4.c | 33 static int ls_pcie_g4_ltssm(struct ls_pcie_g4 *pcie) in ls_pcie_g4_ltssm()
42 static int ls_pcie_g4_link_up(struct ls_pcie_g4 *pcie) in ls_pcie_g4_link_up()
53 static void ls_pcie_g4_ep_enable_cfg(struct ls_pcie_g4 *pcie) in ls_pcie_g4_ep_enable_cfg()
122 static void ls_pcie_g4_dump_wins(struct ls_pcie_g4 *pcie, int wins) in ls_pcie_g4_dump_wins()
148 static void ls_pcie_g4_setup_wins(struct ls_pcie_g4 *pcie) in ls_pcie_g4_setup_wins()
236 struct ls_pcie_g4 *pcie = dev_get_priv(bus); in ls_pcie_g4_read_config() local
269 struct ls_pcie_g4 *pcie = dev_get_priv(bus); in ls_pcie_g4_write_config() local
292 static void ls_pcie_g4_setup_ctrl(struct ls_pcie_g4 *pcie) in ls_pcie_g4_setup_ctrl()
407 static void ls_pcie_g4_set_sriov(struct ls_pcie_g4 *pcie, int pf) in ls_pcie_g4_set_sriov()
423 static void ls_pcie_g4_setup_ep(struct ls_pcie_g4 *pcie) in ls_pcie_g4_setup_ep()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
[all …]
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/pci/ |
| H A D | pcie_intel_fpga.c | 41 #define RP_CFG_ADDR(pcie, reg) \ argument
43 #define RP_SECONDARY(pcie) \ argument
47 #define TLP_CFGRD_DW0(pcie, bus) \ argument
52 #define TLP_CFGWR_DW0(pcie, bus) \ argument
57 #define TLP_CFG_DW1(pcie, tag, be) \ argument
68 #define IS_ROOT_PORT(pcie, bdf) \ argument
233 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
253 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
334 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
356 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
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