1 /* $OpenBSD: pciecam.c,v 1.5 2024/02/03 10:37:26 kettenis Exp $ */
2 /*
3 * Copyright (c) 2013,2017 Patrick Wildt <patrick@blueri.se>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/queue.h>
21 #include <sys/malloc.h>
22 #include <sys/extent.h>
23 #include <sys/device.h>
24 #include <sys/evcount.h>
25 #include <sys/socket.h>
26 #include <sys/timeout.h>
27
28 #include <machine/intr.h>
29 #include <machine/bus.h>
30 #include <machine/fdt.h>
31
32 #include <dev/pci/pcivar.h>
33
34 #include <dev/ofw/fdt.h>
35 #include <dev/ofw/openfirm.h>
36 #include <dev/ofw/ofw_clock.h>
37 #include <dev/ofw/ofw_pinctrl.h>
38 #include <dev/ofw/ofw_misc.h>
39
40 /* Assembling ECAM Configuration Address */
41 #define PCIE_BUS_SHIFT 20
42 #define PCIE_SLOT_SHIFT 15
43 #define PCIE_FUNC_SHIFT 12
44 #define PCIE_BUS_MASK 0xff
45 #define PCIE_SLOT_MASK 0x1f
46 #define PCIE_FUNC_MASK 0x7
47 #define PCIE_REG_MASK 0xfff
48
49 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \
50 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \
51 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \
52 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
53 ((reg) & PCIE_REG_MASK))
54
55 #define HREAD4(sc, reg) \
56 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
57 #define HWRITE4(sc, reg, val) \
58 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
59 #define HSET4(sc, reg, bits) \
60 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
61 #define HCLR4(sc, reg, bits) \
62 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
63
64 struct pciecam_range {
65 uint32_t flags;
66 uint64_t pci_base;
67 uint64_t phys_base;
68 uint64_t size;
69 };
70
71 struct pciecam_softc {
72 struct device sc_dev;
73 int sc_node;
74 bus_space_tag_t sc_iot;
75 bus_space_handle_t sc_ioh;
76 bus_dma_tag_t sc_dmat;
77
78 int sc_dw_quirk;
79
80 int sc_acells;
81 int sc_scells;
82 int sc_pacells;
83 int sc_pscells;
84
85 struct bus_space sc_bus;
86 struct pciecam_range *sc_pciranges;
87 int sc_pcirangeslen;
88 struct extent *sc_ioex;
89 struct extent *sc_memex;
90 char sc_ioex_name[32];
91 char sc_memex_name[32];
92 struct machine_pci_chipset sc_pc;
93 };
94
95 struct pciecam_intr_handle {
96 struct machine_intr_handle pih_ih;
97 bus_dma_tag_t pih_dmat;
98 bus_dmamap_t pih_map;
99 };
100
101 int pciecam_match(struct device *, void *, void *);
102 void pciecam_attach(struct device *, struct device *, void *);
103 void pciecam_attach_hook(struct device *, struct device *, struct pcibus_attach_args *);
104 int pciecam_bus_maxdevs(void *, int);
105 pcitag_t pciecam_make_tag(void *, int, int, int);
106 void pciecam_decompose_tag(void *, pcitag_t, int *, int *, int *);
107 int pciecam_conf_size(void *, pcitag_t);
108 pcireg_t pciecam_conf_read(void *, pcitag_t, int);
109 void pciecam_conf_write(void *, pcitag_t, int, pcireg_t);
110 int pciecam_probe_device_hook(void *, struct pci_attach_args *);
111 int pciecam_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
112 const char *pciecam_intr_string(void *, pci_intr_handle_t);
113 void *pciecam_intr_establish(void *, pci_intr_handle_t, int,
114 struct cpu_info *, int (*func)(void *), void *, char *);
115 void pciecam_intr_disestablish(void *, void *);
116 int pciecam_bs_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, bus_space_handle_t *);
117 paddr_t pciecam_bs_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
118
119 struct interrupt_controller pciecam_ic = {
120 .ic_barrier = intr_barrier
121 };
122
123 const struct cfattach pciecam_ca = {
124 sizeof (struct pciecam_softc), pciecam_match, pciecam_attach
125 };
126
127 struct cfdriver pciecam_cd = {
128 NULL, "pciecam", DV_DULL
129 };
130
131 int
pciecam_match(struct device * parent,void * match,void * aux)132 pciecam_match(struct device *parent, void *match, void *aux)
133 {
134 struct fdt_attach_args *faa = aux;
135
136 return (OF_is_compatible(faa->fa_node, "pci-host-ecam-generic") ||
137 OF_is_compatible(faa->fa_node, "snps,dw-pcie-ecam"));
138 }
139
140 void
pciecam_attach(struct device * parent,struct device * self,void * aux)141 pciecam_attach(struct device *parent, struct device *self, void *aux)
142 {
143 struct fdt_attach_args *faa = aux;
144 struct pciecam_softc *sc = (struct pciecam_softc *) self;
145 struct pcibus_attach_args pba;
146 uint32_t *ranges;
147 int i, j, nranges, rangeslen;
148
149 sc->sc_node = faa->fa_node;
150 sc->sc_iot = faa->fa_iot;
151 sc->sc_dmat = faa->fa_dmat;
152
153 if (OF_is_compatible(faa->fa_node, "snps,dw-pcie-ecam"))
154 sc->sc_dw_quirk = 1;
155
156 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells",
157 faa->fa_acells);
158 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells",
159 faa->fa_scells);
160 sc->sc_pacells = faa->fa_acells;
161 sc->sc_pscells = faa->fa_scells;
162
163 rangeslen = OF_getproplen(sc->sc_node, "ranges");
164 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||
165 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells +
166 sc->sc_pacells + sc->sc_scells))
167 panic("pciecam_attach: invalid ranges property");
168
169 ranges = malloc(rangeslen, M_TEMP, M_WAITOK);
170 OF_getpropintarray(sc->sc_node, "ranges", ranges,
171 rangeslen);
172
173 nranges = (rangeslen / sizeof(uint32_t)) /
174 (sc->sc_acells + sc->sc_pacells + sc->sc_scells);
175 sc->sc_pciranges = mallocarray(nranges,
176 sizeof(struct pciecam_range), M_TEMP, M_WAITOK);
177 sc->sc_pcirangeslen = nranges;
178
179 for (i = 0, j = 0; i < nranges; i++) {
180 sc->sc_pciranges[i].flags = ranges[j++];
181 sc->sc_pciranges[i].pci_base = ranges[j++];
182 if (sc->sc_acells - 1 == 2) {
183 sc->sc_pciranges[i].pci_base <<= 32;
184 sc->sc_pciranges[i].pci_base |= ranges[j++];
185 }
186 sc->sc_pciranges[i].phys_base = ranges[j++];
187 if (sc->sc_pacells == 2) {
188 sc->sc_pciranges[i].phys_base <<= 32;
189 sc->sc_pciranges[i].phys_base |= ranges[j++];
190 }
191 sc->sc_pciranges[i].size = ranges[j++];
192 if (sc->sc_scells == 2) {
193 sc->sc_pciranges[i].size <<= 32;
194 sc->sc_pciranges[i].size |= ranges[j++];
195 }
196 }
197
198 free(ranges, M_TEMP, rangeslen);
199
200 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
201 faa->fa_reg[0].size, 0, &sc->sc_ioh))
202 panic("pciecam_attach: bus_space_map failed!");
203
204 printf("\n");
205
206 /*
207 * Map PCIe address space.
208 */
209 snprintf(sc->sc_ioex_name, sizeof(sc->sc_ioex_name),
210 "%s pciio", sc->sc_dev.dv_xname);
211 sc->sc_ioex = extent_create(sc->sc_ioex_name, 0, (u_long)-1L,
212 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
213
214 snprintf(sc->sc_memex_name, sizeof(sc->sc_memex_name),
215 "%s pcimem", sc->sc_dev.dv_xname);
216 sc->sc_memex = extent_create(sc->sc_memex_name, 0, (u_long)-1L,
217 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED);
218
219 for (i = 0; i < nranges; i++) {
220 if (sc->sc_pciranges[i].flags >> 24 == 0)
221 continue;
222 if (sc->sc_pciranges[i].flags >> 24 == 1)
223 extent_free(sc->sc_ioex, sc->sc_pciranges[i].pci_base,
224 sc->sc_pciranges[i].size, EX_NOWAIT);
225 else
226 extent_free(sc->sc_memex, sc->sc_pciranges[i].pci_base,
227 sc->sc_pciranges[i].size, EX_NOWAIT);
228 }
229
230 memcpy(&sc->sc_bus, sc->sc_iot, sizeof(sc->sc_bus));
231 sc->sc_bus.bus_private = sc;
232 sc->sc_bus._space_map = pciecam_bs_map;
233 sc->sc_bus._space_mmap = pciecam_bs_mmap;
234
235 sc->sc_pc.pc_conf_v = sc;
236 sc->sc_pc.pc_attach_hook = pciecam_attach_hook;
237 sc->sc_pc.pc_bus_maxdevs = pciecam_bus_maxdevs;
238 sc->sc_pc.pc_make_tag = pciecam_make_tag;
239 sc->sc_pc.pc_decompose_tag = pciecam_decompose_tag;
240 sc->sc_pc.pc_conf_size = pciecam_conf_size;
241 sc->sc_pc.pc_conf_read = pciecam_conf_read;
242 sc->sc_pc.pc_conf_write = pciecam_conf_write;
243 sc->sc_pc.pc_probe_device_hook = pciecam_probe_device_hook;
244
245 sc->sc_pc.pc_intr_v = sc;
246 sc->sc_pc.pc_intr_map = pciecam_intr_map;
247 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi;
248 sc->sc_pc.pc_intr_map_msivec = _pci_intr_map_msivec;
249 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix;
250 sc->sc_pc.pc_intr_string = pciecam_intr_string;
251 sc->sc_pc.pc_intr_establish = pciecam_intr_establish;
252 sc->sc_pc.pc_intr_disestablish = pciecam_intr_disestablish;
253
254 bzero(&pba, sizeof(pba));
255 pba.pba_dmat = sc->sc_dmat;
256
257 pba.pba_busname = "pci";
258 pba.pba_iot = &sc->sc_bus;
259 pba.pba_memt = &sc->sc_bus;
260 pba.pba_ioex = sc->sc_ioex;
261 pba.pba_memex = sc->sc_memex;
262 pba.pba_pmemex = sc->sc_memex;
263 pba.pba_pc = &sc->sc_pc;
264 pba.pba_domain = pci_ndomains++;
265 pba.pba_bus = 0;
266
267 if (OF_getproplen(sc->sc_node, "msi-map") > 0 ||
268 OF_getproplen(sc->sc_node, "msi-parent") > 0)
269 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED;
270
271 config_found(self, &pba, NULL);
272 }
273
274 void
pciecam_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)275 pciecam_attach_hook(struct device *parent, struct device *self,
276 struct pcibus_attach_args *pba)
277 {
278 }
279
280 int
pciecam_bus_maxdevs(void * v,int bus)281 pciecam_bus_maxdevs(void *v, int bus)
282 {
283 struct pciecam_softc *sc = (struct pciecam_softc *)v;
284
285 if (bus == 0 && sc->sc_dw_quirk)
286 return 1;
287 return 32;
288 }
289
290 #define BUS_SHIFT 24
291 #define DEVICE_SHIFT 19
292 #define FNC_SHIFT 16
293
294 pcitag_t
pciecam_make_tag(void * sc,int bus,int dev,int fnc)295 pciecam_make_tag(void *sc, int bus, int dev, int fnc)
296 {
297 return (bus << BUS_SHIFT) | (dev << DEVICE_SHIFT) | (fnc << FNC_SHIFT);
298 }
299
300 void
pciecam_decompose_tag(void * sc,pcitag_t tag,int * busp,int * devp,int * fncp)301 pciecam_decompose_tag(void *sc, pcitag_t tag, int *busp, int *devp, int *fncp)
302 {
303 if (busp != NULL)
304 *busp = (tag >> BUS_SHIFT) & 0xff;
305 if (devp != NULL)
306 *devp = (tag >> DEVICE_SHIFT) & 0x1f;
307 if (fncp != NULL)
308 *fncp = (tag >> FNC_SHIFT) & 0x7;
309 }
310
311 int
pciecam_conf_size(void * sc,pcitag_t tag)312 pciecam_conf_size(void *sc, pcitag_t tag)
313 {
314 return PCIE_CONFIG_SPACE_SIZE;
315 }
316
317 pcireg_t
pciecam_conf_read(void * v,pcitag_t tag,int reg)318 pciecam_conf_read(void *v, pcitag_t tag, int reg)
319 {
320 struct pciecam_softc *sc = (struct pciecam_softc *)v;
321 int bus, dev, fn;
322
323 pciecam_decompose_tag(sc, tag, &bus, &dev, &fn);
324
325 return HREAD4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3));
326 }
327
328 void
pciecam_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)329 pciecam_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
330 {
331 struct pciecam_softc *sc = (struct pciecam_softc *)v;
332 int bus, dev, fn;
333
334 pciecam_decompose_tag(sc, tag, &bus, &dev, &fn);
335
336 HWRITE4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3), data);
337 }
338
339 int
pciecam_probe_device_hook(void * v,struct pci_attach_args * pa)340 pciecam_probe_device_hook(void *v, struct pci_attach_args *pa)
341 {
342 struct pciecam_softc *sc = (struct pciecam_softc *)v;
343 uint16_t rid;
344 int i;
345
346 rid = pci_requester_id(pa->pa_pc, pa->pa_tag);
347 pa->pa_dmat = iommu_device_map_pci(sc->sc_node, rid, pa->pa_dmat);
348
349 for (i = 0; i < sc->sc_pcirangeslen; i++) {
350 if (sc->sc_pciranges[i].flags >> 24 == 0)
351 continue;
352 iommu_reserve_region_pci(sc->sc_node, rid,
353 sc->sc_pciranges[i].pci_base, sc->sc_pciranges[i].size);
354 }
355
356 return 0;
357 }
358
359 int
pciecam_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)360 pciecam_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
361 {
362 ihp->ih_pc = pa->pa_pc;
363 ihp->ih_tag = pa->pa_intrtag;
364 ihp->ih_intrpin = pa->pa_intrpin;
365 ihp->ih_type = PCI_INTX;
366
367 return 0;
368 }
369
370 const char *
pciecam_intr_string(void * sc,pci_intr_handle_t ih)371 pciecam_intr_string(void *sc, pci_intr_handle_t ih)
372 {
373 switch (ih.ih_type) {
374 case PCI_MSI:
375 return "msi";
376 case PCI_MSIX:
377 return "msix";
378 }
379
380 return "irq";
381 }
382
383 void *
pciecam_intr_establish(void * self,pci_intr_handle_t ih,int level,struct cpu_info * ci,int (* func)(void *),void * arg,char * name)384 pciecam_intr_establish(void *self, pci_intr_handle_t ih, int level,
385 struct cpu_info *ci, int (*func)(void *), void *arg, char *name)
386 {
387 struct pciecam_softc *sc = (struct pciecam_softc *)self;
388 struct pciecam_intr_handle *pih;
389 bus_dma_segment_t seg;
390 void *cookie;
391
392 KASSERT(ih.ih_type != PCI_NONE);
393
394 if (ih.ih_type != PCI_INTX) {
395 uint64_t addr = 0, data;
396
397 /* Assume hardware passes Requester ID as sideband data. */
398 data = pci_requester_id(ih.ih_pc, ih.ih_tag);
399 cookie = fdt_intr_establish_msi_cpu(sc->sc_node, &addr,
400 &data, level, ci, func, arg, (void *)name);
401 if (cookie == NULL)
402 return NULL;
403
404 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK);
405 pih->pih_ih.ih_ic = &pciecam_ic;
406 pih->pih_ih.ih_ih = cookie;
407 pih->pih_dmat = ih.ih_dmat;
408
409 if (bus_dmamap_create(pih->pih_dmat, sizeof(uint32_t), 1,
410 sizeof(uint32_t), 0, BUS_DMA_WAITOK, &pih->pih_map)) {
411 free(pih, M_DEVBUF, sizeof(*pih));
412 fdt_intr_disestablish(cookie);
413 return NULL;
414 }
415
416 memset(&seg, 0, sizeof(seg));
417 seg.ds_addr = addr;
418 seg.ds_len = sizeof(uint32_t);
419
420 if (bus_dmamap_load_raw(pih->pih_dmat, pih->pih_map,
421 &seg, 1, sizeof(uint32_t), BUS_DMA_WAITOK)) {
422 bus_dmamap_destroy(pih->pih_dmat, pih->pih_map);
423 free(pih, M_DEVBUF, sizeof(*pih));
424 fdt_intr_disestablish(cookie);
425 return NULL;
426 }
427
428 addr = pih->pih_map->dm_segs[0].ds_addr;
429 if (ih.ih_type == PCI_MSIX) {
430 pci_msix_enable(ih.ih_pc, ih.ih_tag,
431 &sc->sc_bus, ih.ih_intrpin, addr, data);
432 } else
433 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data);
434 } else {
435 int bus, dev, fn;
436 uint32_t reg[4];
437
438 pciecam_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn);
439
440 reg[0] = bus << 16 | dev << 11 | fn << 8;
441 reg[1] = reg[2] = 0;
442 reg[3] = ih.ih_intrpin;
443
444 cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
445 sizeof(reg), level, ci, func, arg, name);
446 if (cookie == NULL)
447 return NULL;
448
449 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK);
450 pih->pih_ih.ih_ic = &pciecam_ic;
451 pih->pih_ih.ih_ih = cookie;
452 pih->pih_dmat = NULL;
453 }
454
455 return pih;
456 }
457
458 void
pciecam_intr_disestablish(void * sc,void * cookie)459 pciecam_intr_disestablish(void *sc, void *cookie)
460 {
461 struct pciecam_intr_handle *pih = cookie;
462
463 fdt_intr_disestablish(pih->pih_ih.ih_ih);
464 if (pih->pih_dmat) {
465 bus_dmamap_unload(pih->pih_dmat, pih->pih_map);
466 bus_dmamap_destroy(pih->pih_dmat, pih->pih_map);
467 }
468 free(pih, M_DEVBUF, sizeof(*pih));
469 }
470
471 /*
472 * Translate memory address if needed.
473 */
474 int
pciecam_bs_map(bus_space_tag_t t,bus_addr_t bpa,bus_size_t size,int flag,bus_space_handle_t * bshp)475 pciecam_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size,
476 int flag, bus_space_handle_t *bshp)
477 {
478 struct pciecam_softc *sc = t->bus_private;
479 uint64_t physbase, pcibase, psize;
480 int i;
481
482 for (i = 0; i < sc->sc_pcirangeslen; i++) {
483 physbase = sc->sc_pciranges[i].phys_base;
484 pcibase = sc->sc_pciranges[i].pci_base;
485 psize = sc->sc_pciranges[i].size;
486
487 if (bpa >= pcibase && bpa + size <= pcibase + psize)
488 return bus_space_map(sc->sc_iot,
489 bpa - pcibase + physbase, size, flag, bshp);
490 }
491
492 return ENXIO;
493 }
494
495 paddr_t
pciecam_bs_mmap(bus_space_tag_t t,bus_addr_t bpa,off_t off,int prot,int flags)496 pciecam_bs_mmap(bus_space_tag_t t, bus_addr_t bpa, off_t off,
497 int prot, int flags)
498 {
499 struct pciecam_softc *sc = t->bus_private;
500 uint64_t physbase, pcibase, psize;
501 int i;
502
503 for (i = 0; i < sc->sc_pcirangeslen; i++) {
504 physbase = sc->sc_pciranges[i].phys_base;
505 pcibase = sc->sc_pciranges[i].pci_base;
506 psize = sc->sc_pciranges[i].size;
507
508 if (bpa >= pcibase && bpa < pcibase + psize)
509 return bus_space_mmap(sc->sc_iot,
510 bpa - pcibase + physbase, off, prot, flags);
511 }
512
513 return -1;
514 }
515