1 /*- 2 * Copyright (C) 2001-2003 by NBMK Encryption Technologies. 3 * All rights reserved. 4 * 5 * NBMK Encryption Technologies provides no support of any kind for 6 * this software. Questions or concerns about it may be addressed to 7 * the members of the relevant open-source community at 8 * <tech-crypto@netbsd.org>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 17 * 2. Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials provided 20 * with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /***************************************************************************** 36 * @(#) nsp2000_regs.h 1.9@(#) 37 *****************************************************************************/ 38 39 /*****************************************************************************/ 40 /** @file nsp2000_regs.h 41 * @brief NSP2000 Control Register Layout 42 * 43 * This header contains a structure that maps all NSP2000 control registers 44 * for the 4 major subcomponents - the AMBA controller, the PKE/PKH, 45 * the RNG/RNH, and the CCH/CC. 46 * 47 *****************************************************************************/ 48 49 /***************************************************************************** 50 * Revision history: 51 * 01/16/04 jpw Add N8_NO_64_BURST to prevent 64bit bursts to 32 bit regs 52 * during sequential slave io accesses. Certain chipsets 53 * need this for proper use with the PCI-X board. 54 * 03/01/02 brr Added register definition previously in n8_enqueue_common.h 55 * 01/15/02 dkm Added amba read pointer mirror register and fixed comment. 56 * BUG 413 57 * 11/12/01 msz Made uint32_t's vuint32_t's (volatile). Fix for BUG 281. 58 * 09/07/01 mmd Further elimination of "simon" except for line 155, which 59 * is there until the rest of the SDK has been updated to use 60 * NSP2000REGS_t instead of SIMON. 61 * 08/16/01 mmd Elimination of "simon" and relocation to driver/common. 62 * 08/01/01 mmd Migration to new common driver framework. 63 * 07/25/01 mmd Now including stdint.h for Linux, to get uint32_t types. 64 * 07/19/01 mmd Cleaned up the #include's at top of file. 65 * 06/27/01 jke changed #ifdef protections on #include bsdi_types.h so file 66 * can be included in both BSDi kernel and user-apps 67 * 06/21/01 jke added #include ../bsdi_types.h to ensure compile-ability in 68 * BSD 69 * 06/21/01 mmd Ensuring inttypes.h doesn't get included when building the 70 * Linux or BSDi drivers. One should, in either of these cases, 71 * define either the LINUXDRIVER or BSDIDRIVER symbol in the 72 * driver's makefile. 73 * 06/06/01 mmd Added missing amba_pci_timer_value register, and all CCH 74 * registers. Also reformatted. 75 * 01/03/01 jw Original version. 76 ****************************************************************************/ 77 /** @defgroup NSP2000Driver NSP2000 Control Register Layout. 78 */ 79 80 81 #ifndef NSP2000_REGS_H 82 #define NSP2000_REGS_H 83 84 #include "n8_pub_types.h" 85 86 typedef volatile uint8_t vuint8_t; 87 typedef volatile uint16_t vuint16_t; 88 typedef volatile uint32_t vuint32_t; 89 90 91 #define NSP_CORE_ENABLE 0x80000000 92 #define NSP_CORE_BUSY 0x40000000 93 94 /* This dummy write breaks up sequential register accesses */ 95 /* Sequential accesses may fail on the PCI-X board on some */ 96 /* chipsets if the system attempts to turn two 32 bit */ 97 /* register accesses into a single 64 byte burst. */ 98 #define N8_NO_64_BURST nsp->amba_pci_test=0xbadbeef; 99 100 /**************************************************** 101 * 64K of total address space * 102 * * 103 * In PCI BAR0 - Offset from hw pointer: * 104 * 0x0000 - 16K - AMBA-PCI Bridge * 105 * 0x4000 - 16K - Public Key Module * 106 * 0x8000 - 16K - Crypto Control Processor * 107 * 0xC000 - 16K - Random Number Generator * 108 ****************************************************/ 109 #define PKE_REG_OFFSET 0x4000 110 #define EA_REG_OFFSET 0x8000 111 #define RNG_REG_OFFSET 0xC000 112 113 typedef struct 114 { 115 /* AMBA CONTROLLER REGISTERS */ 116 vuint32_t amba_pci_endian_mode; /* 0000 */ 117 vuint32_t amba_pci_timer_preset; /* 0004 */ 118 vuint32_t amba_pci_status; /* 0008 */ 119 vuint32_t amba_pci_control; /* 000C */ 120 vuint32_t amba_pci_timer_value; /* 0010 */ 121 vuint32_t amba_pci_test; /* 0014 */ 122 vuint32_t amba_pci_read_ptr_mirror; /* 0018 */ 123 vuint32_t amba_pci_unused[4089]; /* 001C */ 124 125 126 /* PKH AND PKE REGISTERS */ 127 vuint32_t pkh_test0; /* 4000 */ 128 vuint32_t pkh_test1; /* 4004 */ 129 vuint32_t pkh_q_length; /* 4008 */ 130 vuint32_t pkh_q_ptr; /* 400C */ 131 vuint32_t pkh_q_bar1; /* 4010 */ 132 vuint32_t pkh_q_bar0; /* 4014 */ 133 vuint32_t pkh_intr_enable; /* 4018 */ 134 vuint32_t pkh_control_status; /* 401C */ 135 vuint32_t pkh_secure_key_storage_data; /* 4020 */ 136 vuint32_t pkh_secure_key_storage_control;/* 4024 */ 137 vuint32_t pkh_reserved[46]; /* 4028 */ 138 139 vuint32_t pke_command_block[8]; /* 40E0 */ 140 vuint32_t pkh_reserved1[960]; /* 4100 */ 141 vuint32_t pke_BN_cache[1024]; /* 5000 */ /* 256 "digits" */ 142 /* of 128 bits */ 143 vuint32_t pkh_reserved2[2048]; /* 6000 */ 144 145 146 /* CCH REGISTERS */ 147 vuint32_t cch_test0; /* 8000 */ 148 vuint32_t cch_test1; /* 8004 */ 149 vuint32_t cch_q_length; /* 8008 */ 150 vuint32_t cch_q_ptr; /* 800C */ 151 vuint32_t cch_q_bar1; /* 8010 */ 152 vuint32_t cch_q_bar0; /* 8014 */ 153 vuint32_t cch_intr_enable; /* 8018 */ 154 vuint32_t cch_control_status; /* 801C */ 155 vuint32_t cch_context_data1; /* 8020 */ 156 vuint32_t cch_context_data0; /* 8024 */ 157 vuint32_t cch_context_addr; /* 8028 */ 158 vuint32_t cch_reserved[4085]; /* 802C */ 159 160 161 /* RNG REGISTERS - RNG Buffer - RNH REGISTERS */ 162 /* 64-bit registers in the RNG must be read/written using the Most */ 163 /* Significant Word first, in order to access the full 64bit value. */ 164 vuint32_t rng_reserved0; /* C000 */ 165 vuint32_t rng_tod_seconds; /* C004 */ 166 vuint32_t rng_reserved1; /* C008 */ 167 vuint32_t rng_tod_prescale; /* C00C */ 168 vuint32_t rng_tod_msw; /* C010 */ 169 vuint32_t rng_tod_lsw; /* C014 */ 170 vuint32_t rng_key1_msw; /* C018 */ 171 vuint32_t rng_key1_lsw; /* C01C */ 172 vuint32_t rng_key2_msw; /* C020 */ 173 vuint32_t rng_key2_lsw; /* C024 */ 174 vuint32_t rng_hostseed_msw; /* C028 */ 175 vuint32_t rng_hostseed_lsw; /* C02C */ 176 vuint32_t rng_reserved2; /* C030 */ 177 vuint32_t rng_sample_interval; /* C034 */ 178 vuint32_t rng_reserved3; /* C038 */ 179 vuint32_t rng_external_clock_scalar; /* C03C */ 180 vuint32_t rng_reserved4; /* C040 */ 181 vuint32_t rng_buffer_write_ptr; /* C044 */ 182 vuint32_t rng_sample_seed_msw; /* C048 */ 183 vuint32_t rng_sample_seed_lsw; /* C04C */ 184 vuint32_t rng_reserved5; /* C050 */ 185 vuint32_t rng_lsfr_diag; /* C054 */ 186 vuint32_t rng_lsfr1_history_msw; /* C058 */ 187 vuint32_t rng_lsfr1_history_lsw; /* C05C */ 188 vuint32_t rng_lsfr2_history_msw; /* C060 */ 189 vuint32_t rng_lsfr2_history_lsw; /* C064 */ 190 vuint32_t rng_lsfr3_history_msw; /* C068 */ 191 vuint32_t rng_lsfr3_history_lsw; /* C06C */ 192 vuint32_t rng_lsfr4_history_msw; /* C070 */ 193 vuint32_t rng_lsfr4_history_lsw; /* C074 */ 194 vuint32_t rng_reserved6; /* C078 */ 195 vuint32_t rng_control_status; /* C07C */ 196 vuint32_t rng_reserved7[480]; /* C080 */ 197 198 vuint32_t rng_buffer[512]; /* This buffer is to be */ 199 /* interpreted as 256 64-bit */ 200 /* value. Software must */ 201 /* access MSB first - 0 then */ 202 /* 1. */ 203 204 vuint32_t rnh_test1; /* D000 */ 205 vuint32_t rnh_test0; /* D004 */ 206 vuint32_t rnh_q_length; /* D008 */ 207 vuint32_t rnh_q_ptr; /* D00C */ 208 vuint32_t rnh_q_bar1; /* D010 */ 209 vuint32_t rnh_q_bar0; /* D014 */ 210 vuint32_t rnh_control_status; /* D018 */ 211 vuint32_t rnh_reserved; /* D01C */ 212 vuint32_t rng_unused[3064]; /* D020 */ 213 } NSP2000REGS_t; 214 215 216 typedef NSP2000REGS_t SIMON; 217 218 typedef struct 219 { 220 /* Common Registers */ 221 volatile uint32_t test0; /* 0000 */ 222 volatile uint32_t test1; /* 0004 */ 223 volatile uint32_t q_length; /* 0008 */ 224 volatile uint32_t q_ptr; /* 000C */ 225 volatile uint32_t q_bar1; /* 0010 */ 226 volatile uint32_t q_bar0; /* 0014 */ 227 volatile uint32_t intr_enable; /* 0018 */ 228 volatile uint32_t control_status; /* 001C */ 229 } N8CommonRegs_t; 230 231 typedef struct 232 { 233 N8CommonRegs_t commonRegs; 234 volatile uint32_t pkh_secure_key_storage_data; /* 0020 */ 235 volatile uint32_t pkh_secure_key_storage_control;/* 0024 */ 236 volatile uint32_t pkh_reserved[46]; /* 0028 */ 237 238 volatile uint32_t pke_command_block[8]; /* 00E0 */ 239 volatile uint32_t pkh_reserved1[960]; /* 0100 */ 240 volatile uint32_t pke_BN_cache[1024]; /* 0000 */ /* 256 "digits" */ 241 /* of 128 bits */ 242 } N8PKERegs_t; 243 244 245 /* CCH REGISTERS */ 246 typedef struct 247 { 248 N8CommonRegs_t commonRegs; 249 volatile uint32_t cch_context_data1; /* 0020 */ 250 volatile uint32_t cch_context_data0; /* 0024 */ 251 volatile uint32_t cch_context_addr; /* 0028 */ 252 } N8EARegs_t; 253 254 255 #define N8_SetDebugRegister(x, y) {x->amba_pci_unused[58] = y;} 256 257 258 #endif /* NSP2000_REGS_H */ 259