1 /* fflas/fflas_memory.h 2 * Copyright (C) 2014 fflas-ffpack group 3 * 4 * Written by Clement Pernet <Clement.Pernet@imag.fr> 5 * 6 * The cache size detection has been copied from the Eigen library, 7 * a lightweight C++ template library for linear algebra, licensed under 8 * the Mozilla 9 * Public License v. 2.0. If a copy of the MPL was not distributed 10 * with this file, You can obtain one at http://mozilla.org/MPL/2.0/. 11 * Copyright (C) 2008-2010 Gael Guennebaud <gael.guennebaud@inria.fr> 12 * Copyright (C) 2008-2009 Benoit Jacob <jacob.benoit.1@gmail.com> 13 * Copyright (C) 2009 Kenneth Riddile <kfriddile@yahoo.com> 14 * Copyright (C) 2010 Hauke Heibel <hauke.heibel@gmail.com> 15 * Copyright (C) 2010 Thomas Capricelli <orzel@freehackers.org> 16 * 17 * 18 * ========LICENCE======== 19 * This file is part of the library FFLAS-FFPACK. 20 * 21 * FFLAS-FFPACK is free software: you can redistribute it and/or modify 22 * it under the terms of the GNU Lesser General Public 23 * License as published by the Free Software Foundation; either 24 * version 2.1 of the License, or (at your option) any later version. 25 * 26 * This library is distributed in the hope that it will be useful, 27 * but WITHOUT ANY WARRANTY; without even the implied warranty of 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 29 * Lesser General Public License for more details. 30 * 31 * You should have received a copy of the GNU Lesser General Public 32 * License along with this library; if not, write to the Free Software 33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 34 * ========LICENCE======== 35 *. 36 */ 37 38 #ifndef __FFLASFFPACK_memory_H 39 #define __FFLASFFPACK_memory_H 40 41 #include "fflas-ffpack/utils/align-allocator.h" 42 #include <givaro/givinteger.h> 43 44 namespace FFLAS{ 45 46 template<class Element> alignable()47 inline bool alignable() { 48 return true ; 49 } 50 51 // BB : segfault in Givaro::Integer::logcpy otherwise 52 template<> 53 inline bool alignable<Givaro::Integer*>() { 54 return false; 55 } 56 57 template<class Field> 58 inline typename Field::Element_ptr fflas_new (const Field& F, const size_t m, const Alignment align = Alignment::DEFAULT) 59 { 60 if (alignable<typename Field::Element_ptr>() ) { 61 return malloc_align<typename Field::Element>(m, align); 62 } 63 else { 64 return new typename Field::Element[m]; 65 } 66 } 67 68 template<class Field> 69 inline typename Field::Element_ptr fflas_new (const Field& F, const size_t m, const size_t n, const Alignment align = Alignment::DEFAULT) 70 { 71 return fflas_new(F, m*n, align); 72 } 73 74 template<class Element > 75 inline Element* fflas_new (const size_t m, const Alignment align = Alignment::DEFAULT) 76 { 77 if (alignable<Element*>() ) { 78 return malloc_align<Element>(m, align); 79 } 80 else { 81 return new Element[m]; 82 } 83 84 } 85 86 template<class Element_ptr> fflas_delete(Element_ptr A)87 inline void fflas_delete(Element_ptr A) 88 { 89 if (alignable<Element_ptr>() ) 90 free(A); 91 else 92 delete[] A; 93 } 94 95 template<class Ptr, class ...Args> fflas_delete(Ptr p,Args...args)96 inline void fflas_delete(Ptr p, Args ... args){ 97 fflas_delete(p); 98 fflas_delete(std::forward<Args>(args)...); 99 } 100 101 #ifdef __FFLASFFPACK_HAVE_SSE4_1_INSTRUCTIONS prefetch(const int64_t * addr)102 inline void prefetch(const int64_t* addr) { _mm_prefetch((const char*)(addr), _MM_HINT_T0); } 103 #else prefetch(const int64_t *)104 inline void prefetch(const int64_t*) {} 105 #endif 106 107 #if ( defined(__i386__) || defined(__x86_64__) ) 108 #define __CPUID(abcd,func,id) \ 109 __asm__ __volatile__ ("cpuid": "=a" (abcd[0]), "=b" (abcd[1]), "=c" (abcd[2]), "=d" (abcd[3]) : "a" (func), "c" (id) ); 110 getCacheSize(int & l1,int & l2,int & l3)111 inline void getCacheSize(int& l1, int& l2, int& l3) 112 { 113 int abcd[4]; 114 l1 = l2 = l3 = 0; 115 int cache_id = 0; 116 int cache_type = 0; 117 do { 118 abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0; 119 __CPUID(abcd,0x4,cache_id); 120 cache_type = (abcd[0] & 0x0F) >> 0; 121 if(cache_type==1||cache_type==3) // data or unified cache 122 { 123 int cache_level = (abcd[0] & 0xE0) >> 5; // A[7:5] 124 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22] 125 int partitions = (abcd[1] & 0x003FF000) >> 12; // B[21:12] 126 int line_size = (abcd[1] & 0x00000FFF) >> 0; // B[11:0] 127 int sets = (abcd[2]); // C[31:0] 128 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1); 129 switch(cache_level) 130 { 131 case 1: l1 = cache_size; break; 132 case 2: l2 = cache_size; break; 133 case 3: l3 = cache_size; break; 134 default: break; 135 } 136 } 137 cache_id++; 138 } while(cache_type>0 && cache_id<16); 139 } 140 getTLBSize(int & tlb)141 inline void getTLBSize(int& tlb) 142 { 143 int abcd[4]={}; 144 int sTLB=0; 145 int lTLB; 146 __CPUID(abcd,0x2,0); 147 unsigned char * bytes = reinterpret_cast<unsigned char *>(abcd)+2; 148 for(int i=0; i<14; ++i) 149 switch(bytes[i]){ 150 case 0x03: sTLB=64; break; 151 case 0x04: lTLB=8; break; 152 case 0x05: lTLB=32; break; 153 case 0x56: lTLB=16; break; 154 case 0x57: sTLB=16; break; 155 case 0x59: sTLB=16; break; 156 case 0x5A: lTLB=32; break; 157 case 0x5B: sTLB=lTLB=64; break; 158 case 0x5C: sTLB=lTLB=128; break; 159 case 0x5D: sTLB=lTLB=256; break; 160 case 0xB3: sTLB=128; break; 161 case 0xB4: sTLB=256; break; 162 case 0xBA: sTLB=64; break; 163 case 0xC0: sTLB=lTLB=8; break; 164 case 0xCA: sTLB=512; break; 165 default: break; 166 } 167 //cout<<"small TLB: "<<sTLB<<endl; 168 //cout<<"large TLB: "<<lTLB<<endl; 169 tlb=sTLB*4096; 170 } 171 #else getTLBSize(int & tlb)172 inline void getTLBSize(int& tlb){tlb = 0;} // not implemented in non x86 archs 173 #endif 174 //---------- Cache sizes ---------- 175 176 #if !defined(EIGEN_NO_CPUID) 177 # if defined(__GNUC__) && ( defined(__i386__) || defined(__x86_64__) ) 178 # if defined(__PIC__) && defined(__i386__) 179 // Case for x86 with PIC 180 # define EIGEN_CPUID(abcd,func,id) \ 181 __asm__ __volatile__ ("xchgl %%ebx, %%esi;cpuid; xchgl %%ebx,%%esi": "=a" (abcd[0]), "=S" (abcd[1]), "=c" (abcd[2]), "=d" (abcd[3]) : "a" (func), "c" (id)); 182 # else 183 // Case for x86_64 or x86 w/o PIC 184 # define EIGEN_CPUID(abcd,func,id) \ 185 __asm__ __volatile__ ("cpuid": "=a" (abcd[0]), "=b" (abcd[1]), "=c" (abcd[2]), "=d" (abcd[3]) : "a" (func), "c" (id) ); 186 # endif 187 # elif defined(_MSC_VER) 188 # if (_MSC_VER > 1500) && ( defined(_M_IX86) || defined(_M_X64) ) 189 # define EIGEN_CPUID(abcd,func,id) __cpuidex((int*)abcd,func,id) 190 # endif 191 # endif 192 #endif 193 194 195 #ifdef EIGEN_CPUID 196 cpuid_is_vendor(int abcd[4],const char * vendor)197 inline bool cpuid_is_vendor(int abcd[4], const char* vendor) 198 { 199 return abcd[1]==(reinterpret_cast<const int*>(vendor))[0] && abcd[3]==(reinterpret_cast<const int*>(vendor))[1] && abcd[2]==(reinterpret_cast<const int*>(vendor))[2]; 200 } 201 queryCacheSizes_intel_direct(int & l1,int & l2,int & l3)202 inline void queryCacheSizes_intel_direct(int& l1, int& l2, int& l3) 203 { 204 int abcd[4]; 205 l1 = l2 = l3 = 0; 206 int cache_id = 0; 207 int cache_type = 0; 208 do { 209 abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0; 210 EIGEN_CPUID(abcd,0x4,cache_id); 211 cache_type = (abcd[0] & 0x0F) >> 0; 212 if(cache_type==1||cache_type==3) // data or unified cache 213 { 214 int cache_level = (abcd[0] & 0xE0) >> 5; // A[7:5] 215 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22] 216 int partitions = (abcd[1] & 0x003FF000) >> 12; // B[21:12] 217 int line_size = (abcd[1] & 0x00000FFF) >> 0; // B[11:0] 218 int sets = (abcd[2]); // C[31:0] 219 220 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1); 221 222 switch(cache_level) 223 { 224 case 1: l1 = cache_size; break; 225 case 2: l2 = cache_size; break; 226 case 3: l3 = cache_size; break; 227 default: break; 228 } 229 } 230 cache_id++; 231 } while(cache_type>0 && cache_id<16); 232 } 233 queryCacheSizes_intel_codes(int & l1,int & l2,int & l3)234 inline void queryCacheSizes_intel_codes(int& l1, int& l2, int& l3) 235 { 236 int abcd[4]; 237 abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0; 238 l1 = l2 = l3 = 0; 239 EIGEN_CPUID(abcd,0x00000002,0); 240 unsigned char * bytes = reinterpret_cast<unsigned char *>(abcd)+2; 241 bool check_for_p2_core2 = false; 242 for(int i=0; i<14; ++i) 243 { 244 switch(bytes[i]) 245 { 246 case 0x0A: l1 = 8; break; // 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines 247 case 0x0C: l1 = 16; break; // 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines 248 case 0x0E: l1 = 24; break; // 0Eh data L1 cache, 24 KB, 6 ways, 64 byte lines 249 case 0x10: l1 = 16; break; // 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) 250 case 0x15: l1 = 16; break; // 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) 251 case 0x2C: l1 = 32; break; // 2Ch data L1 cache, 32 KB, 8 ways, 64 byte lines 252 case 0x30: l1 = 32; break; // 30h code L1 cache, 32 KB, 8 ways, 64 byte lines 253 case 0x60: l1 = 16; break; // 60h data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored 254 case 0x66: l1 = 8; break; // 66h data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored 255 case 0x67: l1 = 16; break; // 67h data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored 256 case 0x68: l1 = 32; break; // 68h data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored 257 case 0x1A: l2 = 96; break; // code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64) 258 case 0x22: l3 = 512; break; // code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored 259 case 0x23: l3 = 1024; break; // code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored 260 case 0x25: l3 = 2048; break; // code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored 261 case 0x29: l3 = 4096; break; // code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored 262 case 0x39: l2 = 128; break; // code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored 263 case 0x3A: l2 = 192; break; // code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored 264 case 0x3B: l2 = 128; break; // code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored 265 case 0x3C: l2 = 256; break; // code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored 266 case 0x3D: l2 = 384; break; // code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored 267 case 0x3E: l2 = 512; break; // code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored 268 case 0x40: l2 = 0; break; // no integrated L2 cache (P6 core) or L3 cache (P4 core) 269 case 0x41: l2 = 128; break; // code and data L2 cache, 128 KB, 4 ways, 32 byte lines 270 case 0x42: l2 = 256; break; // code and data L2 cache, 256 KB, 4 ways, 32 byte lines 271 case 0x43: l2 = 512; break; // code and data L2 cache, 512 KB, 4 ways, 32 byte lines 272 case 0x44: l2 = 1024; break; // code and data L2 cache, 1024 KB, 4 ways, 32 byte lines 273 case 0x45: l2 = 2048; break; // code and data L2 cache, 2048 KB, 4 ways, 32 byte lines 274 case 0x46: l3 = 4096; break; // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines 275 case 0x47: l3 = 8192; break; // code and data L3 cache, 8192 KB, 8 ways, 64 byte lines 276 case 0x48: l2 = 3072; break; // code and data L2 cache, 3072 KB, 12 ways, 64 byte lines 277 case 0x49: if(l2!=0) l3 = 4096; else {check_for_p2_core2=true; l3 = l2 = 4096;} break;// code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or L2 for core2 278 case 0x4A: l3 = 6144; break; // code and data L3 cache, 6144 KB, 12 ways, 64 byte lines 279 case 0x4B: l3 = 8192; break; // code and data L3 cache, 8192 KB, 16 ways, 64 byte lines 280 case 0x4C: l3 = 12288; break; // code and data L3 cache, 12288 KB, 12 ways, 64 byte lines 281 case 0x4D: l3 = 16384; break; // code and data L3 cache, 16384 KB, 16 ways, 64 byte lines 282 case 0x4E: l2 = 6144; break; // code and data L2 cache, 6144 KB, 24 ways, 64 byte lines 283 case 0x78: l2 = 1024; break; // code and data L2 cache, 1024 KB, 4 ways, 64 byte lines 284 case 0x79: l2 = 128; break; // code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored 285 case 0x7A: l2 = 256; break; // code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored 286 case 0x7B: l2 = 512; break; // code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored 287 case 0x7C: l2 = 1024; break; // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored 288 case 0x7D: l2 = 2048; break; // code and data L2 cache, 2048 KB, 8 ways, 64 byte lines 289 case 0x7E: l2 = 256; break; // code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64) 290 case 0x7F: l2 = 512; break; // code and data L2 cache, 512 KB, 2 ways, 64 byte lines 291 case 0x80: l2 = 512; break; // code and data L2 cache, 512 KB, 8 ways, 64 byte lines 292 case 0x81: l2 = 128; break; // code and data L2 cache, 128 KB, 8 ways, 32 byte lines 293 case 0x82: l2 = 256; break; // code and data L2 cache, 256 KB, 8 ways, 32 byte lines 294 case 0x83: l2 = 512; break; // code and data L2 cache, 512 KB, 8 ways, 32 byte lines 295 case 0x84: l2 = 1024; break; // code and data L2 cache, 1024 KB, 8 ways, 32 byte lines 296 case 0x85: l2 = 2048; break; // code and data L2 cache, 2048 KB, 8 ways, 32 byte lines 297 case 0x86: l2 = 512; break; // code and data L2 cache, 512 KB, 4 ways, 64 byte lines 298 case 0x87: l2 = 1024; break; // code and data L2 cache, 1024 KB, 8 ways, 64 byte lines 299 case 0x88: l3 = 2048; break; // code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64) 300 case 0x89: l3 = 4096; break; // code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64) 301 case 0x8A: l3 = 8192; break; // code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64) 302 case 0x8D: l3 = 3072; break; // code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64) 303 304 default: break; 305 } 306 } 307 if(check_for_p2_core2 && l2 == l3) 308 l3 = 0; 309 l1 *= 1024; 310 l2 *= 1024; 311 l3 *= 1024; 312 } 313 queryCacheSizes_intel(int & l1,int & l2,int & l3,int max_std_funcs)314 inline void queryCacheSizes_intel(int& l1, int& l2, int& l3, int max_std_funcs) 315 { 316 if(max_std_funcs>=4) 317 queryCacheSizes_intel_direct(l1,l2,l3); 318 else 319 queryCacheSizes_intel_codes(l1,l2,l3); 320 } 321 queryCacheSizes_amd(int & l1,int & l2,int & l3)322 inline void queryCacheSizes_amd(int& l1, int& l2, int& l3) 323 { 324 int abcd[4]; 325 abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0; 326 EIGEN_CPUID(abcd,0x80000005,0); 327 l1 = (abcd[2] >> 24) * 1024; // C[31:24] = L1 size in KB 328 abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0; 329 EIGEN_CPUID(abcd,0x80000006,0); 330 l2 = (abcd[2] >> 16) * 1024; // C[31;16] = l2 cache size in KB 331 l3 = ((abcd[3] & 0xFFFC000) >> 18) * 512 * 1024; // D[31;18] = l3 cache size in 512KB 332 } 333 #endif 334 335 /** \internal 336 * Queries and returns the cache sizes in Bytes of the L1, L2, and L3 data caches respectively */ queryCacheSizes(int & l1,int & l2,int & l3)337 inline void queryCacheSizes(int& l1, int& l2, int& l3) 338 { 339 #ifdef EIGEN_CPUID 340 int abcd[4]; 341 342 // identify the CPU vendor 343 EIGEN_CPUID(abcd,0x0,0); 344 int max_std_funcs = abcd[1]; 345 if(cpuid_is_vendor(abcd,"GenuineIntel")) 346 queryCacheSizes_intel(l1,l2,l3,max_std_funcs); 347 else if(cpuid_is_vendor(abcd,"AuthenticAMD") || cpuid_is_vendor(abcd,"AMDisbetter!") 348 || cpuid_is_vendor(abcd, "HygonGenuine")) 349 queryCacheSizes_amd(l1,l2,l3); 350 else 351 // by default let's use Intel's API 352 queryCacheSizes_intel(l1,l2,l3,max_std_funcs); 353 354 // here is the list of other vendors: 355 // ||cpuid_is_vendor(abcd,"VIA VIA VIA ") 356 // ||cpuid_is_vendor(abcd,"CyrixInstead") 357 // ||cpuid_is_vendor(abcd,"CentaurHauls") 358 // ||cpuid_is_vendor(abcd,"GenuineTMx86") 359 // ||cpuid_is_vendor(abcd,"TransmetaCPU") 360 // ||cpuid_is_vendor(abcd,"RiseRiseRise") 361 // ||cpuid_is_vendor(abcd,"Geode by NSC") 362 // ||cpuid_is_vendor(abcd,"SiS SiS SiS ") 363 // ||cpuid_is_vendor(abcd,"UMC UMC UMC ") 364 // ||cpuid_is_vendor(abcd,"NexGenDriven") 365 #else 366 l1 = l2 = l3 = -1; 367 #endif 368 } 369 370 /** \internal 371 * \returns the size in Bytes of the L1 data cache */ queryL1CacheSize()372 inline int queryL1CacheSize() 373 { 374 int l1(-1), l2, l3; 375 queryCacheSizes(l1,l2,l3); 376 return l1; 377 } 378 379 /** \internal 380 * \returns the size in Bytes of the L2 or L3 cache if this later is present */ queryTopLevelCacheSize()381 inline int queryTopLevelCacheSize() 382 { 383 int l1, l2(-1), l3(-1); 384 queryCacheSizes(l1,l2,l3); 385 return (std::max)(l2,l3); 386 } 387 388 } // namespace FFLAS 389 #endif // __FFLASFFPACK_memory_H 390 /* -*- mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- */ 391 // vim:sts=4:sw=4:ts=4:et:sr:cino=>s,f0,{0,g0,(0,\:0,t0,+0,=s 392