1 /* $OpenBSD: qwxvar.h,v 1.26 2024/05/28 08:34:52 stsp Exp $ */
2
3 /*
4 * Copyright (c) 2018-2019 The Linux Foundation.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted (subject to the limitations in the disclaimer
9 * below) provided that the following conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * * Neither the name of [Owner Organization] nor the names of its
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
21 *
22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY
23 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
24 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
25 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
26 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
27 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #ifdef QWX_DEBUG
37 #define DPRINTF(x...) do { if (qwx_debug) printf(x); } while(0)
38 #define DNPRINTF(n,x...) do { if (qwx_debug & n) printf(x); } while(0)
39 #define QWX_D_MISC 0x00000001
40 #define QWX_D_MHI 0x00000002
41 #define QWX_D_QMI 0x00000004
42 #define QWX_D_WMI 0x00000008
43 #define QWX_D_HTC 0x00000010
44 #define QWX_D_HTT 0x00000020
45 #define QWX_D_MAC 0x00000040
46 #define QWX_D_MGMT 0x00000080
47 #define QWX_D_CE 0x00000100
48 extern uint32_t qwx_debug;
49 #else
50 #define DPRINTF(x...)
51 #define DNPRINTF(n,x...)
52 #endif
53
54 struct qwx_softc;
55
56 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
57
58 struct ath11k_hw_ring_mask {
59 uint8_t tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
60 uint8_t rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
61 uint8_t rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
62 uint8_t rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
63 uint8_t rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
64 uint8_t reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
65 uint8_t rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
66 uint8_t host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
67 };
68
69 #define ATH11K_FW_DIR "qwx"
70
71 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"
72 #define ATH11K_BOARD_API2_FILE "board-2"
73 #define ATH11K_DEFAULT_BOARD_FILE "board"
74 #define ATH11K_DEFAULT_CAL_FILE "caldata"
75 #define ATH11K_AMSS_FILE "amss"
76 #define ATH11K_M3_FILE "m3"
77 #define ATH11K_REGDB_FILE "regdb"
78
79 #define QWX_FW_BUILD_ID_MASK "QC_IMAGE_VERSION_STRING="
80
81 struct ath11k_hw_tcl2wbm_rbm_map {
82 uint8_t tcl_ring_num;
83 uint8_t wbm_ring_num;
84 uint8_t rbm_id;
85 };
86
87 /**
88 * enum hal_rx_buf_return_buf_manager
89 *
90 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
91 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
92 * descriptor list.
93 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
94 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
95 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
96 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
97 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
98 */
99
100 enum hal_rx_buf_return_buf_manager {
101 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST,
102 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST,
103 HAL_RX_BUF_RBM_FW_BM,
104 HAL_RX_BUF_RBM_SW0_BM,
105 HAL_RX_BUF_RBM_SW1_BM,
106 HAL_RX_BUF_RBM_SW2_BM,
107 HAL_RX_BUF_RBM_SW3_BM,
108 HAL_RX_BUF_RBM_SW4_BM,
109 };
110
111 struct ath11k_hw_hal_params {
112 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
113 const struct ath11k_hw_tcl2wbm_rbm_map *tcl2wbm_rbm_map;
114 };
115
116 struct hal_tx_info {
117 uint16_t meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */
118 uint8_t ring_id;
119 uint32_t desc_id;
120 enum hal_tcl_desc_type type;
121 enum hal_tcl_encap_type encap_type;
122 uint64_t paddr;
123 uint32_t data_len;
124 uint32_t pkt_offset;
125 enum hal_encrypt_type encrypt_type;
126 uint32_t flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */
127 uint32_t flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */
128 uint16_t addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */
129 uint16_t bss_ast_hash;
130 uint16_t bss_ast_idx;
131 uint8_t tid;
132 uint8_t search_type; /* %HAL_TX_ADDR_SEARCH_ */
133 uint8_t lmac_id;
134 uint8_t dscp_tid_tbl_idx;
135 bool enable_mesh;
136 uint8_t rbm_id;
137 };
138
139 /* TODO: Check if the actual desc macros can be used instead */
140 #define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0)
141 #define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1)
142 #define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2)
143 #define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3)
144 #define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4)
145 #define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5)
146 #define HAL_TX_STATUS_FLAGS_OFDMA BIT(6)
147
148 #define HAL_TX_STATUS_DESC_LEN sizeof(struct hal_wbm_release_ring)
149
150 /* Tx status parsed from srng desc */
151 struct hal_tx_status {
152 enum hal_wbm_rel_src_module buf_rel_source;
153 enum hal_wbm_tqm_rel_reason status;
154 uint8_t ack_rssi;
155 uint32_t flags; /* %HAL_TX_STATUS_FLAGS_ */
156 uint32_t ppdu_id;
157 uint8_t try_cnt;
158 uint8_t tid;
159 uint16_t peer_id;
160 uint32_t rate_stats;
161 };
162
163 struct ath11k_hw_params {
164 const char *name;
165 uint16_t hw_rev;
166 uint8_t max_radios;
167 uint32_t bdf_addr;
168
169 struct {
170 const char *dir;
171 size_t board_size;
172 size_t cal_offset;
173 } fw;
174
175 const struct ath11k_hw_ops *hw_ops;
176 const struct ath11k_hw_ring_mask *ring_mask;
177
178 bool internal_sleep_clock;
179
180 const struct ath11k_hw_regs *regs;
181 uint32_t qmi_service_ins_id;
182 const struct ce_attr *host_ce_config;
183 uint32_t ce_count;
184 const struct ce_pipe_config *target_ce_config;
185 uint32_t target_ce_count;
186 const struct service_to_pipe *svc_to_ce_map;
187 uint32_t svc_to_ce_map_len;
188
189 bool single_pdev_only;
190
191 bool rxdma1_enable;
192 int num_rxmda_per_pdev;
193 bool rx_mac_buf_ring;
194 bool vdev_start_delay;
195 bool htt_peer_map_v2;
196 #if notyet
197 struct {
198 uint8_t fft_sz;
199 uint8_t fft_pad_sz;
200 uint8_t summary_pad_sz;
201 uint8_t fft_hdr_len;
202 uint16_t max_fft_bins;
203 bool fragment_160mhz;
204 } spectral;
205
206 uint16_t interface_modes;
207 bool supports_monitor;
208 bool full_monitor_mode;
209 #endif
210 bool supports_shadow_regs;
211 bool idle_ps;
212 bool supports_sta_ps;
213 bool cold_boot_calib;
214 bool cbcal_restart_fw;
215 int fw_mem_mode;
216 uint32_t num_vdevs;
217 uint32_t num_peers;
218 bool supports_suspend;
219 uint32_t hal_desc_sz;
220 bool supports_regdb;
221 bool fix_l1ss;
222 bool credit_flow;
223 uint8_t max_tx_ring;
224 const struct ath11k_hw_hal_params *hal_params;
225 #if notyet
226 bool supports_dynamic_smps_6ghz;
227 bool alloc_cacheable_memory;
228 bool supports_rssi_stats;
229 #endif
230 bool fw_wmi_diag_event;
231 bool current_cc_support;
232 bool dbr_debug_support;
233 bool global_reset;
234 #ifdef notyet
235 const struct cfg80211_sar_capa *bios_sar_capa;
236 #endif
237 bool m3_fw_support;
238 bool fixed_bdf_addr;
239 bool fixed_mem_region;
240 bool static_window_map;
241 bool hybrid_bus_type;
242 bool fixed_fw_mem;
243 #if notyet
244 bool support_off_channel_tx;
245 bool supports_multi_bssid;
246
247 struct {
248 uint32_t start;
249 uint32_t end;
250 } sram_dump;
251
252 bool tcl_ring_retry;
253 #endif
254 uint32_t tx_ring_size;
255 bool smp2p_wow_exit;
256 };
257
258 struct ath11k_hw_ops {
259 uint8_t (*get_hw_mac_from_pdev_id)(int pdev_id);
260 void (*wmi_init_config)(struct qwx_softc *sc,
261 struct target_resource_config *config);
262 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
263 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
264 #if notyet
265 void (*tx_mesh_enable)(struct ath11k_base *ab,
266 struct hal_tcl_data_cmd *tcl_cmd);
267 #endif
268 int (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
269 #if notyet
270 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
271 #endif
272 uint8_t (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
273 uint8_t *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
274 int (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
275 uint32_t (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
276 uint8_t (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
277 #ifdef notyet
278 uint8_t (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
279 bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);
280 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
281 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
282 uint16_t (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
283 #endif
284 uint16_t (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
285 #ifdef notyet
286 uint8_t (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
287 uint8_t (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
288 uint8_t (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
289 #endif
290 uint32_t (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
291 #ifdef notyet
292 uint8_t (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
293 uint8_t (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
294 uint8_t (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
295 uint16_t (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
296 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
297 struct hal_rx_desc *ldesc);
298 uint32_t (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
299 uint32_t (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
300 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, uint16_t len);
301 #endif
302 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
303 #ifdef notyet
304 uint8_t *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
305 #endif
306 void (*reo_setup)(struct qwx_softc *);
307 #ifdef notyet
308 uint16_t (*mpdu_info_get_peerid)(uint8_t *tlv_data);
309 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
310 uint8_t* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
311 uint32_t (*get_ring_selector)(struct sk_buff *skb);
312 #endif
313 };
314
315 extern const struct ath11k_hw_ops ipq8074_ops;
316 extern const struct ath11k_hw_ops ipq6018_ops;
317 extern const struct ath11k_hw_ops qca6390_ops;
318 extern const struct ath11k_hw_ops qcn9074_ops;
319 extern const struct ath11k_hw_ops wcn6855_ops;
320 extern const struct ath11k_hw_ops wcn6750_ops;
321
322 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
323 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
324 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
325 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750;
326
327 struct ath11k_hw_regs {
328 uint32_t hal_tcl1_ring_base_lsb;
329 uint32_t hal_tcl1_ring_base_msb;
330 uint32_t hal_tcl1_ring_id;
331 uint32_t hal_tcl1_ring_misc;
332 uint32_t hal_tcl1_ring_tp_addr_lsb;
333 uint32_t hal_tcl1_ring_tp_addr_msb;
334 uint32_t hal_tcl1_ring_consumer_int_setup_ix0;
335 uint32_t hal_tcl1_ring_consumer_int_setup_ix1;
336 uint32_t hal_tcl1_ring_msi1_base_lsb;
337 uint32_t hal_tcl1_ring_msi1_base_msb;
338 uint32_t hal_tcl1_ring_msi1_data;
339 uint32_t hal_tcl2_ring_base_lsb;
340 uint32_t hal_tcl_ring_base_lsb;
341
342 uint32_t hal_tcl_status_ring_base_lsb;
343
344 uint32_t hal_reo1_ring_base_lsb;
345 uint32_t hal_reo1_ring_base_msb;
346 uint32_t hal_reo1_ring_id;
347 uint32_t hal_reo1_ring_misc;
348 uint32_t hal_reo1_ring_hp_addr_lsb;
349 uint32_t hal_reo1_ring_hp_addr_msb;
350 uint32_t hal_reo1_ring_producer_int_setup;
351 uint32_t hal_reo1_ring_msi1_base_lsb;
352 uint32_t hal_reo1_ring_msi1_base_msb;
353 uint32_t hal_reo1_ring_msi1_data;
354 uint32_t hal_reo2_ring_base_lsb;
355 uint32_t hal_reo1_aging_thresh_ix_0;
356 uint32_t hal_reo1_aging_thresh_ix_1;
357 uint32_t hal_reo1_aging_thresh_ix_2;
358 uint32_t hal_reo1_aging_thresh_ix_3;
359
360 uint32_t hal_reo1_ring_hp;
361 uint32_t hal_reo1_ring_tp;
362 uint32_t hal_reo2_ring_hp;
363
364 uint32_t hal_reo_tcl_ring_base_lsb;
365 uint32_t hal_reo_tcl_ring_hp;
366
367 uint32_t hal_reo_status_ring_base_lsb;
368 uint32_t hal_reo_status_hp;
369
370 uint32_t hal_reo_cmd_ring_base_lsb;
371 uint32_t hal_reo_cmd_ring_hp;
372
373 uint32_t hal_sw2reo_ring_base_lsb;
374 uint32_t hal_sw2reo_ring_hp;
375
376 uint32_t hal_seq_wcss_umac_ce0_src_reg;
377 uint32_t hal_seq_wcss_umac_ce0_dst_reg;
378 uint32_t hal_seq_wcss_umac_ce1_src_reg;
379 uint32_t hal_seq_wcss_umac_ce1_dst_reg;
380
381 uint32_t hal_wbm_idle_link_ring_base_lsb;
382 uint32_t hal_wbm_idle_link_ring_misc;
383
384 uint32_t hal_wbm_release_ring_base_lsb;
385
386 uint32_t hal_wbm0_release_ring_base_lsb;
387 uint32_t hal_wbm1_release_ring_base_lsb;
388
389 uint32_t pcie_qserdes_sysclk_en_sel;
390 uint32_t pcie_pcs_osc_dtct_config_base;
391
392 uint32_t hal_shadow_base_addr;
393 uint32_t hal_reo1_misc_ctl;
394 };
395
396 extern const struct ath11k_hw_regs ipq8074_regs;
397 extern const struct ath11k_hw_regs qca6390_regs;
398 extern const struct ath11k_hw_regs qcn9074_regs;
399 extern const struct ath11k_hw_regs wcn6855_regs;
400 extern const struct ath11k_hw_regs wcn6750_regs;
401
402 enum ath11k_dev_flags {
403 ATH11K_CAC_RUNNING,
404 ATH11K_FLAG_CORE_REGISTERED,
405 ATH11K_FLAG_CRASH_FLUSH,
406 ATH11K_FLAG_RAW_MODE,
407 ATH11K_FLAG_HW_CRYPTO_DISABLED,
408 ATH11K_FLAG_BTCOEX,
409 ATH11K_FLAG_RECOVERY,
410 ATH11K_FLAG_UNREGISTERING,
411 ATH11K_FLAG_REGISTERED,
412 ATH11K_FLAG_QMI_FAIL,
413 ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
414 ATH11K_FLAG_CE_IRQ_ENABLED,
415 ATH11K_FLAG_EXT_IRQ_ENABLED,
416 ATH11K_FLAG_FIXED_MEM_RGN,
417 ATH11K_FLAG_DEVICE_INIT_DONE,
418 ATH11K_FLAG_MULTI_MSI_VECTORS,
419 };
420
421 enum ath11k_scan_state {
422 ATH11K_SCAN_IDLE,
423 ATH11K_SCAN_STARTING,
424 ATH11K_SCAN_RUNNING,
425 ATH11K_SCAN_ABORTING,
426 };
427
428 enum ath11k_11d_state {
429 ATH11K_11D_IDLE,
430 ATH11K_11D_PREPARING,
431 ATH11K_11D_RUNNING,
432 };
433
434 /* enum ath11k_spectral_mode:
435 *
436 * @SPECTRAL_DISABLED: spectral mode is disabled
437 * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
438 * something else.
439 * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
440 * is performed manually.
441 */
442 enum ath11k_spectral_mode {
443 ATH11K_SPECTRAL_DISABLED = 0,
444 ATH11K_SPECTRAL_BACKGROUND,
445 ATH11K_SPECTRAL_MANUAL,
446 };
447
448 #define QWX_SCAN_11D_INTERVAL 600000
449 #define QWX_11D_INVALID_VDEV_ID 0xFFFF
450
451 struct qwx_ops {
452 uint32_t (*read32)(struct qwx_softc *, uint32_t);
453 void (*write32)(struct qwx_softc *, uint32_t, uint32_t);
454 int (*start)(struct qwx_softc *);
455 void (*stop)(struct qwx_softc *);
456 int (*power_up)(struct qwx_softc *);
457 void (*power_down)(struct qwx_softc *);
458 int (*submit_xfer)(struct qwx_softc *, struct mbuf *);
459 void (*irq_enable)(struct qwx_softc *sc);
460 void (*irq_disable)(struct qwx_softc *sc);
461 int (*map_service_to_pipe)(struct qwx_softc *, uint16_t,
462 uint8_t *, uint8_t *);
463 int (*get_user_msi_vector)(struct qwx_softc *, char *,
464 int *, uint32_t *, uint32_t *);
465 };
466
467 struct qwx_dmamem {
468 bus_dmamap_t map;
469 bus_dma_segment_t seg;
470 size_t size;
471 caddr_t kva;
472 };
473
474 struct qwx_dmamem *qwx_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t);
475 void qwx_dmamem_free(bus_dma_tag_t, struct qwx_dmamem *);
476
477 #define QWX_DMA_MAP(_adm) ((_adm)->map)
478 #define QWX_DMA_LEN(_adm) ((_adm)->size)
479 #define QWX_DMA_DVA(_adm) ((_adm)->map->dm_segs[0].ds_addr)
480 #define QWX_DMA_KVA(_adm) ((void *)(_adm)->kva)
481
482 struct hal_srng_params {
483 bus_addr_t ring_base_paddr;
484 uint32_t *ring_base_vaddr;
485 int num_entries;
486 uint32_t intr_batch_cntr_thres_entries;
487 uint32_t intr_timer_thres_us;
488 uint32_t flags;
489 uint32_t max_buffer_len;
490 uint32_t low_threshold;
491 uint64_t msi_addr;
492 uint32_t msi_data;
493
494 /* Add more params as needed */
495 };
496
497 enum hal_srng_dir {
498 HAL_SRNG_DIR_SRC,
499 HAL_SRNG_DIR_DST
500 };
501
502 /* srng flags */
503 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
504 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
505 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
506 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
507 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
508 #define HAL_SRNG_FLAGS_CACHED 0x20000000
509 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
510 #define HAL_SRNG_FLAGS_REMAP_CE_RING 0x10000000
511
512 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
513 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
514
515 /* Common SRNG ring structure for source and destination rings */
516 struct hal_srng {
517 /* Unique SRNG ring ID */
518 uint8_t ring_id;
519
520 /* Ring initialization done */
521 uint8_t initialized;
522
523 /* Interrupt/MSI value assigned to this ring */
524 int irq;
525
526 /* Physical base address of the ring */
527 bus_addr_t ring_base_paddr;
528
529 /* Virtual base address of the ring */
530 uint32_t *ring_base_vaddr;
531
532 /* Number of entries in ring */
533 uint32_t num_entries;
534
535 /* Ring size */
536 uint32_t ring_size;
537
538 /* Ring size mask */
539 uint32_t ring_size_mask;
540
541 /* Size of ring entry */
542 uint32_t entry_size;
543
544 /* Interrupt timer threshold - in micro seconds */
545 uint32_t intr_timer_thres_us;
546
547 /* Interrupt batch counter threshold - in number of ring entries */
548 uint32_t intr_batch_cntr_thres_entries;
549
550 /* MSI Address */
551 bus_addr_t msi_addr;
552
553 /* MSI data */
554 uint32_t msi_data;
555
556 /* Misc flags */
557 uint32_t flags;
558 #ifdef notyet
559 /* Lock for serializing ring index updates */
560 spinlock_t lock;
561 #endif
562 /* Start offset of SRNG register groups for this ring
563 * TBD: See if this is required - register address can be derived
564 * from ring ID
565 */
566 uint32_t hwreg_base[HAL_SRNG_NUM_REG_GRP];
567
568 uint64_t timestamp;
569
570 /* Source or Destination ring */
571 enum hal_srng_dir ring_dir;
572
573 union {
574 struct {
575 /* SW tail pointer */
576 uint32_t tp;
577
578 /* Shadow head pointer location to be updated by HW */
579 volatile uint32_t *hp_addr;
580
581 /* Cached head pointer */
582 uint32_t cached_hp;
583
584 /* Tail pointer location to be updated by SW - This
585 * will be a register address and need not be
586 * accessed through SW structure
587 */
588 uint32_t *tp_addr;
589
590 /* Current SW loop cnt */
591 uint32_t loop_cnt;
592
593 /* max transfer size */
594 uint16_t max_buffer_length;
595
596 /* head pointer at access end */
597 uint32_t last_hp;
598 } dst_ring;
599
600 struct {
601 /* SW head pointer */
602 uint32_t hp;
603
604 /* SW reap head pointer */
605 uint32_t reap_hp;
606
607 /* Shadow tail pointer location to be updated by HW */
608 uint32_t *tp_addr;
609
610 /* Cached tail pointer */
611 uint32_t cached_tp;
612
613 /* Head pointer location to be updated by SW - This
614 * will be a register address and need not be accessed
615 * through SW structure
616 */
617 uint32_t *hp_addr;
618
619 /* Low threshold - in number of ring entries */
620 uint32_t low_threshold;
621
622 /* tail pointer at access end */
623 uint32_t last_tp;
624 } src_ring;
625 } u;
626 };
627
628 enum hal_ring_type {
629 HAL_REO_DST,
630 HAL_REO_EXCEPTION,
631 HAL_REO_REINJECT,
632 HAL_REO_CMD,
633 HAL_REO_STATUS,
634 HAL_TCL_DATA,
635 HAL_TCL_CMD,
636 HAL_TCL_STATUS,
637 HAL_CE_SRC,
638 HAL_CE_DST,
639 HAL_CE_DST_STATUS,
640 HAL_WBM_IDLE_LINK,
641 HAL_SW2WBM_RELEASE,
642 HAL_WBM2SW_RELEASE,
643 HAL_RXDMA_BUF,
644 HAL_RXDMA_DST,
645 HAL_RXDMA_MONITOR_BUF,
646 HAL_RXDMA_MONITOR_STATUS,
647 HAL_RXDMA_MONITOR_DST,
648 HAL_RXDMA_MONITOR_DESC,
649 HAL_RXDMA_DIR_BUF,
650 HAL_MAX_RING_TYPES,
651 };
652
653 /* HW SRNG configuration table */
654 struct hal_srng_config {
655 int start_ring_id;
656 uint16_t max_rings;
657 uint16_t entry_size;
658 uint32_t reg_start[HAL_SRNG_NUM_REG_GRP];
659 uint16_t reg_size[HAL_SRNG_NUM_REG_GRP];
660 uint8_t lmac_ring;
661 enum hal_srng_dir ring_dir;
662 uint32_t max_size;
663 };
664
665 #define QWX_NUM_SRNG_CFG 21
666
667 struct hal_reo_status_header {
668 uint16_t cmd_num;
669 enum hal_reo_cmd_status cmd_status;
670 uint16_t cmd_exe_time;
671 uint32_t timestamp;
672 };
673
674 struct hal_reo_status_queue_stats {
675 uint16_t ssn;
676 uint16_t curr_idx;
677 uint32_t pn[4];
678 uint32_t last_rx_queue_ts;
679 uint32_t last_rx_dequeue_ts;
680 uint32_t rx_bitmap[8]; /* Bitmap from 0-255 */
681 uint32_t curr_mpdu_cnt;
682 uint32_t curr_msdu_cnt;
683 uint16_t fwd_due_to_bar_cnt;
684 uint16_t dup_cnt;
685 uint32_t frames_in_order_cnt;
686 uint32_t num_mpdu_processed_cnt;
687 uint32_t num_msdu_processed_cnt;
688 uint32_t total_num_processed_byte_cnt;
689 uint32_t late_rx_mpdu_cnt;
690 uint32_t reorder_hole_cnt;
691 uint8_t timeout_cnt;
692 uint8_t bar_rx_cnt;
693 uint8_t num_window_2k_jump_cnt;
694 };
695
696 struct hal_reo_status_flush_queue {
697 bool err_detected;
698 };
699
700 enum hal_reo_status_flush_cache_err_code {
701 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS,
702 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE,
703 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND,
704 };
705
706 struct hal_reo_status_flush_cache {
707 bool err_detected;
708 enum hal_reo_status_flush_cache_err_code err_code;
709 bool cache_controller_flush_status_hit;
710 uint8_t cache_controller_flush_status_desc_type;
711 uint8_t cache_controller_flush_status_client_id;
712 uint8_t cache_controller_flush_status_err;
713 uint8_t cache_controller_flush_status_cnt;
714 };
715
716 enum hal_reo_status_unblock_cache_type {
717 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE,
718 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE,
719 };
720
721 struct hal_reo_status_unblock_cache {
722 bool err_detected;
723 enum hal_reo_status_unblock_cache_type unblock_type;
724 };
725
726 struct hal_reo_status_flush_timeout_list {
727 bool err_detected;
728 bool list_empty;
729 uint16_t release_desc_cnt;
730 uint16_t fwd_buf_cnt;
731 };
732
733 enum hal_reo_threshold_idx {
734 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0,
735 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1,
736 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2,
737 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM,
738 };
739
740 struct hal_reo_status_desc_thresh_reached {
741 enum hal_reo_threshold_idx threshold_idx;
742 uint32_t link_desc_counter0;
743 uint32_t link_desc_counter1;
744 uint32_t link_desc_counter2;
745 uint32_t link_desc_counter_sum;
746 };
747
748 struct hal_reo_status {
749 struct hal_reo_status_header uniform_hdr;
750 uint8_t loop_cnt;
751 union {
752 struct hal_reo_status_queue_stats queue_stats;
753 struct hal_reo_status_flush_queue flush_queue;
754 struct hal_reo_status_flush_cache flush_cache;
755 struct hal_reo_status_unblock_cache unblock_cache;
756 struct hal_reo_status_flush_timeout_list timeout_list;
757 struct hal_reo_status_desc_thresh_reached desc_thresh_reached;
758 } u;
759 };
760
761 /* HAL context to be used to access SRNG APIs (currently used by data path
762 * and transport (CE) modules)
763 */
764 struct ath11k_hal {
765 /* HAL internal state for all SRNG rings.
766 */
767 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX];
768
769 /* SRNG configuration table */
770 struct hal_srng_config srng_config[QWX_NUM_SRNG_CFG];
771
772 /* Remote pointer memory for HW/FW updates */
773 struct qwx_dmamem *rdpmem;
774 struct {
775 uint32_t *vaddr;
776 bus_addr_t paddr;
777 } rdp;
778
779 /* Shared memory for ring pointer updates from host to FW */
780 struct qwx_dmamem *wrpmem;
781 struct {
782 uint32_t *vaddr;
783 bus_addr_t paddr;
784 } wrp;
785
786 /* Available REO blocking resources bitmap */
787 uint8_t avail_blk_resource;
788
789 uint8_t current_blk_index;
790
791 /* shadow register configuration */
792 uint32_t shadow_reg_addr[HAL_SHADOW_NUM_REGS];
793 int num_shadow_reg_configured;
794 #ifdef notyet
795 struct lock_class_key srng_key[HAL_SRNG_RING_ID_MAX];
796 #endif
797 };
798
799 enum hal_pn_type {
800 HAL_PN_TYPE_NONE,
801 HAL_PN_TYPE_WPA,
802 HAL_PN_TYPE_WAPI_EVEN,
803 HAL_PN_TYPE_WAPI_UNEVEN,
804 };
805
806 enum hal_ce_desc {
807 HAL_CE_DESC_SRC,
808 HAL_CE_DESC_DST,
809 HAL_CE_DESC_DST_STATUS,
810 };
811
812 struct ce_ie_addr {
813 uint32_t ie1_reg_addr;
814 uint32_t ie2_reg_addr;
815 uint32_t ie3_reg_addr;
816 };
817
818 struct ce_remap {
819 uint32_t base;
820 uint32_t size;
821 };
822
823 struct ce_attr {
824 /* CE_ATTR_* values */
825 unsigned int flags;
826
827 /* #entries in source ring - Must be a power of 2 */
828 unsigned int src_nentries;
829
830 /*
831 * Max source send size for this CE.
832 * This is also the minimum size of a destination buffer.
833 */
834 unsigned int src_sz_max;
835
836 /* #entries in destination ring - Must be a power of 2 */
837 unsigned int dest_nentries;
838
839 void (*recv_cb)(struct qwx_softc *, struct mbuf *);
840 void (*send_cb)(struct qwx_softc *, struct mbuf *);
841 };
842
843 #define CE_DESC_RING_ALIGN 8
844
845 struct qwx_rx_msdu {
846 TAILQ_ENTRY(qwx_rx_msdu) entry;
847 struct mbuf *m;
848 struct ieee80211_rxinfo rxi;
849 int is_first_msdu;
850 int is_last_msdu;
851 int is_continuation;
852 int is_mcbc;
853 int is_eapol;
854 struct hal_rx_desc *rx_desc;
855 uint8_t err_rel_src;
856 uint8_t err_code;
857 uint8_t mac_id;
858 uint8_t unmapped;
859 uint8_t is_frag;
860 uint8_t tid;
861 uint16_t peer_id;
862 uint16_t seq_no;
863 };
864
865 TAILQ_HEAD(qwx_rx_msdu_list, qwx_rx_msdu);
866
867 struct qwx_rx_data {
868 struct mbuf *m;
869 bus_dmamap_t map;
870 struct qwx_rx_msdu rx_msdu;
871 };
872
873 struct qwx_tx_data {
874 struct ieee80211_node *ni;
875 struct mbuf *m;
876 bus_dmamap_t map;
877 uint8_t eid;
878 uint8_t flags;
879 uint32_t cipher;
880 };
881
882 struct qwx_ce_ring {
883 /* Number of entries in this ring; must be power of 2 */
884 unsigned int nentries;
885 unsigned int nentries_mask;
886
887 /* For dest ring, this is the next index to be processed
888 * by software after it was/is received into.
889 *
890 * For src ring, this is the last descriptor that was sent
891 * and completion processed by software.
892 *
893 * Regardless of src or dest ring, this is an invariant
894 * (modulo ring size):
895 * write index >= read index >= sw_index
896 */
897 unsigned int sw_index;
898 /* cached copy */
899 unsigned int write_index;
900
901 /* Start of DMA-coherent area reserved for descriptors */
902 /* Host address space */
903 caddr_t base_addr;
904
905 /* DMA map for Tx/Rx descriptors. */
906 bus_dmamap_t dmap;
907 bus_dma_segment_t dsegs;
908 int nsegs;
909 size_t desc_sz;
910
911 /* HAL ring id */
912 uint32_t hal_ring_id;
913
914 /*
915 * Per-transfer data.
916 * Size and type of this data depends on how the ring is used.
917 *
918 * For transfers using DMA, the context contains pointers to
919 * struct qwx_rx_data if this ring is a dest ring, or struct
920 * qwx_tx_data if this ring is a src ring. DMA maps are allocated
921 * when the device is started via sc->ops.start, and will be used
922 * to load mbufs for DMA transfers.
923 * In this case, the pointers MUST NOT be cleared until the device
924 * is stopped. Otherwise we'd lose track of our DMA mappings!
925 * The Linux ath11k driver works differently because it can store
926 * DMA mapping information in a Linux socket buffer structure, which
927 * is not possible with mbufs.
928 *
929 * Keep last.
930 */
931 void *per_transfer_context[0];
932 };
933
934 void qwx_htc_tx_completion_handler(struct qwx_softc *, struct mbuf *);
935 void qwx_htc_rx_completion_handler(struct qwx_softc *, struct mbuf *);
936 void qwx_dp_htt_htc_t2h_msg_handler(struct qwx_softc *, struct mbuf *);
937
938 struct qwx_dp;
939
940 struct qwx_dp_htt_wbm_tx_status {
941 uint32_t msdu_id;
942 int acked;
943 int ack_rssi;
944 uint16_t peer_id;
945 };
946
947 #define DP_NUM_CLIENTS_MAX 64
948 #define DP_AVG_TIDS_PER_CLIENT 2
949 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
950 #define DP_AVG_MSDUS_PER_FLOW 128
951 #define DP_AVG_FLOWS_PER_TID 2
952 #define DP_AVG_MPDUS_PER_TID_MAX 128
953 #define DP_AVG_MSDUS_PER_MPDU 4
954
955 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */
956
957 #define DP_BA_WIN_SZ_MAX 256
958
959 #define DP_TCL_NUM_RING_MAX 3
960 #define DP_TCL_NUM_RING_MAX_QCA6390 1
961
962 #define DP_IDLE_SCATTER_BUFS_MAX 16
963
964 #define DP_WBM_RELEASE_RING_SIZE 64
965 #define DP_TCL_DATA_RING_SIZE 512
966 #define DP_TCL_DATA_RING_SIZE_WCN6750 2048
967 #define DP_TX_COMP_RING_SIZE 32768
968 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE
969 #define DP_TCL_CMD_RING_SIZE 32
970 #define DP_TCL_STATUS_RING_SIZE 32
971 #define DP_REO_DST_RING_MAX 4
972 #define DP_REO_DST_RING_SIZE 2048
973 #define DP_REO_REINJECT_RING_SIZE 32
974 #define DP_RX_RELEASE_RING_SIZE 1024
975 #define DP_REO_EXCEPTION_RING_SIZE 128
976 #define DP_REO_CMD_RING_SIZE 256
977 #define DP_REO_STATUS_RING_SIZE 2048
978 #define DP_RXDMA_BUF_RING_SIZE 4096
979 #define DP_RXDMA_REFILL_RING_SIZE 2048
980 #define DP_RXDMA_ERR_DST_RING_SIZE 1024
981 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024
982 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
983 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
984 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
985
986 #define DP_RX_RELEASE_RING_NUM 3
987
988 #define DP_RX_BUFFER_SIZE 2048
989 #define DP_RX_BUFFER_SIZE_LITE 1024
990 #define DP_RX_BUFFER_ALIGN_SIZE 128
991
992 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0)
993 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18)
994
995 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
996 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
997
998 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
999 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
1000 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
1001
1002 struct qwx_hp_update_timer {
1003 struct timeout timer;
1004 int started;
1005 int init;
1006 uint32_t tx_num;
1007 uint32_t timer_tx_num;
1008 uint32_t ring_id;
1009 uint32_t interval;
1010 struct qwx_softc *sc;
1011 };
1012
1013 struct dp_rx_tid {
1014 uint8_t tid;
1015 struct qwx_dmamem *mem;
1016 uint32_t *vaddr;
1017 uint64_t paddr;
1018 uint32_t size;
1019 uint32_t ba_win_sz;
1020 int active;
1021
1022 /* Info related to rx fragments */
1023 uint32_t cur_sn;
1024 uint16_t last_frag_no;
1025 uint16_t rx_frag_bitmap;
1026 #if 0
1027 struct sk_buff_head rx_frags;
1028 struct hal_reo_dest_ring *dst_ring_desc;
1029
1030 /* Timer info related to fragments */
1031 struct timer_list frag_timer;
1032 struct ath11k_base *ab;
1033 #endif
1034 };
1035
1036 #define DP_REO_DESC_FREE_THRESHOLD 64
1037 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
1038 #define DP_MON_PURGE_TIMEOUT_MS 100
1039 #define DP_MON_SERVICE_BUDGET 128
1040
1041 struct dp_reo_cache_flush_elem {
1042 TAILQ_ENTRY(dp_reo_cache_flush_elem) entry;
1043 struct dp_rx_tid data;
1044 uint64_t ts;
1045 };
1046
1047 TAILQ_HEAD(dp_reo_cmd_cache_flush_head, dp_reo_cache_flush_elem);
1048
1049 struct dp_reo_cmd {
1050 TAILQ_ENTRY(dp_reo_cmd) entry;
1051 struct dp_rx_tid data;
1052 int cmd_num;
1053 void (*handler)(struct qwx_dp *, void *,
1054 enum hal_reo_cmd_status status);
1055 };
1056
1057 TAILQ_HEAD(dp_reo_cmd_head, dp_reo_cmd);
1058
1059 struct dp_srng {
1060 struct qwx_dmamem *mem;
1061 uint32_t *vaddr;
1062 bus_addr_t paddr;
1063 int size;
1064 uint32_t ring_id;
1065 uint8_t cached;
1066 };
1067
1068 struct dp_tx_ring {
1069 uint8_t tcl_data_ring_id;
1070 struct dp_srng tcl_data_ring;
1071 struct dp_srng tcl_comp_ring;
1072 int cur;
1073 int queued;
1074 struct qwx_tx_data *data;
1075 struct hal_wbm_release_ring *tx_status;
1076 int tx_status_head;
1077 int tx_status_tail;
1078 };
1079
1080
1081 struct dp_link_desc_bank {
1082 struct qwx_dmamem *mem;
1083 caddr_t *vaddr;
1084 bus_addr_t paddr;
1085 uint32_t size;
1086 };
1087
1088 /* Size to enforce scatter idle list mode */
1089 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
1090 #define DP_LINK_DESC_BANKS_MAX 8
1091
1092 struct hal_wbm_idle_scatter_list {
1093 struct qwx_dmamem *mem;
1094 bus_addr_t paddr;
1095 struct hal_wbm_link_desc *vaddr;
1096 };
1097
1098 struct qwx_dp {
1099 struct qwx_softc *sc;
1100 enum ath11k_htc_ep_id eid;
1101 int htt_tgt_version_received;
1102 uint8_t htt_tgt_ver_major;
1103 uint8_t htt_tgt_ver_minor;
1104 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
1105 struct dp_srng wbm_idle_ring;
1106 struct dp_srng wbm_desc_rel_ring;
1107 struct dp_srng tcl_cmd_ring;
1108 struct dp_srng tcl_status_ring;
1109 struct dp_srng reo_reinject_ring;
1110 struct dp_srng rx_rel_ring;
1111 struct dp_srng reo_except_ring;
1112 struct dp_srng reo_cmd_ring;
1113 struct dp_srng reo_status_ring;
1114 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
1115 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
1116 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
1117 struct dp_reo_cmd_head reo_cmd_list;
1118 struct dp_reo_cmd_cache_flush_head reo_cmd_cache_flush_list;
1119 #if 0
1120 struct list_head dp_full_mon_mpdu_list;
1121 #endif
1122 uint32_t reo_cmd_cache_flush_count;
1123 #if 0
1124 /**
1125 * protects access to below fields,
1126 * - reo_cmd_list
1127 * - reo_cmd_cache_flush_list
1128 * - reo_cmd_cache_flush_count
1129 */
1130 spinlock_t reo_cmd_lock;
1131 #endif
1132 struct qwx_hp_update_timer reo_cmd_timer;
1133 struct qwx_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
1134 };
1135
1136 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
1137 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
1138
1139 struct qwx_ce_pipe {
1140 struct qwx_softc *sc;
1141 uint16_t pipe_num;
1142 unsigned int attr_flags;
1143 unsigned int buf_sz;
1144 unsigned int rx_buf_needed;
1145
1146 void (*send_cb)(struct qwx_softc *, struct mbuf *);
1147 void (*recv_cb)(struct qwx_softc *, struct mbuf *);
1148
1149 #ifdef notyet
1150 struct tasklet_struct intr_tq;
1151 #endif
1152 struct qwx_ce_ring *src_ring;
1153 struct qwx_ce_ring *dest_ring;
1154 struct qwx_ce_ring *status_ring;
1155 uint64_t timestamp;
1156 };
1157
1158 struct qwx_ce {
1159 struct qwx_ce_pipe ce_pipe[CE_COUNT_MAX];
1160 #ifdef notyet
1161 /* Protects rings of all ce pipes */
1162 spinlock_t ce_lock;
1163 #endif
1164 struct qwx_hp_update_timer hp_timer[CE_COUNT_MAX];
1165 };
1166
1167
1168 /* XXX This may be non-zero on AHB but is always zero on PCI. */
1169 #define ATH11K_CE_OFFSET(sc) (0)
1170
1171 struct qwx_qmi_ce_cfg {
1172 const uint8_t *shadow_reg;
1173 int shadow_reg_len;
1174 uint32_t *shadow_reg_v2;
1175 uint32_t shadow_reg_v2_len;
1176 };
1177
1178 struct qwx_qmi_target_info {
1179 uint32_t chip_id;
1180 uint32_t chip_family;
1181 uint32_t board_id;
1182 uint32_t soc_id;
1183 uint32_t fw_version;
1184 uint32_t eeprom_caldata;
1185 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
1186 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
1187 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH];
1188 };
1189
1190 enum ath11k_bdf_search {
1191 ATH11K_BDF_SEARCH_DEFAULT,
1192 ATH11K_BDF_SEARCH_BUS_AND_BOARD,
1193 };
1194
1195 struct qwx_device_id {
1196 enum ath11k_bdf_search bdf_search;
1197 uint32_t vendor;
1198 uint32_t device;
1199 uint32_t subsystem_vendor;
1200 uint32_t subsystem_device;
1201 };
1202
1203 struct qwx_wmi_base;
1204
1205 struct qwx_pdev_wmi {
1206 struct qwx_wmi_base *wmi;
1207 enum ath11k_htc_ep_id eid;
1208 const struct wmi_peer_flags_map *peer_flags;
1209 uint32_t rx_decap_mode;
1210 int tx_ce_desc;
1211 };
1212
1213 #define QWX_MAX_RADIOS 3
1214
1215 struct qwx_wmi_base {
1216 struct qwx_softc *sc;
1217 struct qwx_pdev_wmi wmi[QWX_MAX_RADIOS];
1218 enum ath11k_htc_ep_id wmi_endpoint_id[QWX_MAX_RADIOS];
1219 uint32_t max_msg_len[QWX_MAX_RADIOS];
1220 int service_ready;
1221 int unified_ready;
1222 uint8_t svc_map[howmany(WMI_MAX_EXT2_SERVICE, 8)];
1223 int tx_credits;
1224 const struct wmi_peer_flags_map *peer_flags;
1225 uint32_t num_mem_chunks;
1226 uint32_t rx_decap_mode;
1227 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
1228 enum wmi_host_hw_mode_config_type preferred_hw_mode;
1229 struct target_resource_config wlan_resource_config;
1230 struct ath11k_targ_cap *targ_cap;
1231 };
1232
1233 struct wmi_tlv_policy {
1234 size_t min_len;
1235 };
1236
1237 struct wmi_tlv_svc_ready_parse {
1238 int wmi_svc_bitmap_done;
1239 };
1240
1241 struct wmi_tlv_dma_ring_caps_parse {
1242 struct wmi_dma_ring_capabilities *dma_ring_caps;
1243 uint32_t n_dma_ring_caps;
1244 };
1245
1246 struct wmi_tlv_svc_rdy_ext_parse {
1247 struct ath11k_service_ext_param param;
1248 struct wmi_soc_mac_phy_hw_mode_caps *hw_caps;
1249 struct wmi_hw_mode_capabilities *hw_mode_caps;
1250 uint32_t n_hw_mode_caps;
1251 uint32_t tot_phy_id;
1252 struct wmi_hw_mode_capabilities pref_hw_mode_caps;
1253 struct wmi_mac_phy_capabilities *mac_phy_caps;
1254 size_t mac_phy_caps_size;
1255 uint32_t n_mac_phy_caps;
1256 struct wmi_soc_hal_reg_capabilities *soc_hal_reg_caps;
1257 struct wmi_hal_reg_capabilities_ext *ext_hal_reg_caps;
1258 uint32_t n_ext_hal_reg_caps;
1259 struct wmi_tlv_dma_ring_caps_parse dma_caps_parse;
1260 int hw_mode_done;
1261 int mac_phy_done;
1262 int ext_hal_reg_done;
1263 int mac_phy_chainmask_combo_done;
1264 int mac_phy_chainmask_cap_done;
1265 int oem_dma_ring_cap_done;
1266 int dma_ring_cap_done;
1267 };
1268
1269 struct wmi_tlv_svc_rdy_ext2_parse {
1270 struct wmi_tlv_dma_ring_caps_parse dma_caps_parse;
1271 bool dma_ring_cap_done;
1272 };
1273
1274 struct wmi_tlv_rdy_parse {
1275 uint32_t num_extra_mac_addr;
1276 };
1277
1278 struct wmi_tlv_dma_buf_release_parse {
1279 struct ath11k_wmi_dma_buf_release_fixed_param fixed;
1280 struct wmi_dma_buf_release_entry *buf_entry;
1281 struct wmi_dma_buf_release_meta_data *meta_data;
1282 uint32_t num_buf_entry;
1283 uint32_t num_meta;
1284 bool buf_entry_done;
1285 bool meta_data_done;
1286 };
1287
1288 struct wmi_tlv_fw_stats_parse {
1289 const struct wmi_stats_event *ev;
1290 const struct wmi_per_chain_rssi_stats *rssi;
1291 struct ath11k_fw_stats *stats;
1292 int rssi_num;
1293 bool chain_rssi_done;
1294 };
1295
1296 struct wmi_tlv_mgmt_rx_parse {
1297 const struct wmi_mgmt_rx_hdr *fixed;
1298 const uint8_t *frame_buf;
1299 bool frame_buf_done;
1300 };
1301
1302 struct qwx_htc;
1303
1304 struct qwx_htc_ep_ops {
1305 void (*ep_tx_complete)(struct qwx_softc *, struct mbuf *);
1306 void (*ep_rx_complete)(struct qwx_softc *, struct mbuf *);
1307 void (*ep_tx_credits)(struct qwx_softc *);
1308 };
1309
1310 /* service connection information */
1311 struct qwx_htc_svc_conn_req {
1312 uint16_t service_id;
1313 struct qwx_htc_ep_ops ep_ops;
1314 int max_send_queue_depth;
1315 };
1316
1317 /* service connection response information */
1318 struct qwx_htc_svc_conn_resp {
1319 uint8_t buffer_len;
1320 uint8_t actual_len;
1321 enum ath11k_htc_ep_id eid;
1322 unsigned int max_msg_len;
1323 uint8_t connect_resp_code;
1324 };
1325
1326 #define ATH11K_NUM_CONTROL_TX_BUFFERS 2
1327 #define ATH11K_HTC_MAX_LEN 4096
1328 #define ATH11K_HTC_MAX_CTRL_MSG_LEN 256
1329 #define ATH11K_HTC_WAIT_TIMEOUT_HZ (1 * HZ)
1330 #define ATH11K_HTC_CONTROL_BUFFER_SIZE (ATH11K_HTC_MAX_CTRL_MSG_LEN + \
1331 sizeof(struct ath11k_htc_hdr))
1332 #define ATH11K_HTC_CONN_SVC_TIMEOUT_HZ (1 * HZ)
1333 #define ATH11K_HTC_MAX_SERVICE_ALLOC_ENTRIES 8
1334
1335 struct qwx_htc_ep {
1336 struct qwx_htc *htc;
1337 enum ath11k_htc_ep_id eid;
1338 enum ath11k_htc_svc_id service_id;
1339 struct qwx_htc_ep_ops ep_ops;
1340
1341 int max_tx_queue_depth;
1342 int max_ep_message_len;
1343 uint8_t ul_pipe_id;
1344 uint8_t dl_pipe_id;
1345
1346 uint8_t seq_no; /* for debugging */
1347 int tx_credits;
1348 bool tx_credit_flow_enabled;
1349 };
1350
1351 struct qwx_htc_svc_tx_credits {
1352 uint16_t service_id;
1353 uint8_t credit_allocation;
1354 };
1355
1356 struct qwx_htc {
1357 struct qwx_softc *sc;
1358 struct qwx_htc_ep endpoint[ATH11K_HTC_EP_COUNT];
1359 #ifdef notyet
1360 /* protects endpoints */
1361 spinlock_t tx_lock;
1362 #endif
1363 uint8_t control_resp_buffer[ATH11K_HTC_MAX_CTRL_MSG_LEN];
1364 int control_resp_len;
1365
1366 int ctl_resp;
1367
1368 int total_transmit_credits;
1369 struct qwx_htc_svc_tx_credits
1370 service_alloc_table[ATH11K_HTC_MAX_SERVICE_ALLOC_ENTRIES];
1371 int target_credit_size;
1372 uint8_t wmi_ep_count;
1373 };
1374
1375 struct qwx_msi_user {
1376 char *name;
1377 int num_vectors;
1378 uint32_t base_vector;
1379 };
1380
1381 struct qwx_msi_config {
1382 int total_vectors;
1383 int total_users;
1384 struct qwx_msi_user *users;
1385 uint16_t hw_rev;
1386 };
1387
1388 struct ath11k_band_cap {
1389 uint32_t phy_id;
1390 uint32_t max_bw_supported;
1391 uint32_t ht_cap_info;
1392 uint32_t he_cap_info[2];
1393 uint32_t he_mcs;
1394 uint32_t he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
1395 struct ath11k_ppe_threshold he_ppet;
1396 uint16_t he_6ghz_capa;
1397 };
1398
1399 struct ath11k_pdev_cap {
1400 uint32_t supported_bands;
1401 uint32_t ampdu_density;
1402 uint32_t vht_cap;
1403 uint32_t vht_mcs;
1404 uint32_t he_mcs;
1405 uint32_t tx_chain_mask;
1406 uint32_t rx_chain_mask;
1407 uint32_t tx_chain_mask_shift;
1408 uint32_t rx_chain_mask_shift;
1409 struct ath11k_band_cap band[WMI_NUM_SUPPORTED_BAND_MAX];
1410 int nss_ratio_enabled;
1411 uint8_t nss_ratio_info;
1412 };
1413
1414 struct qwx_pdev {
1415 struct qwx_softc *sc;
1416 uint32_t pdev_id;
1417 struct ath11k_pdev_cap cap;
1418 uint8_t mac_addr[IEEE80211_ADDR_LEN];
1419 };
1420
1421 struct qwx_dbring_cap {
1422 uint32_t pdev_id;
1423 enum wmi_direct_buffer_module id;
1424 uint32_t min_elem;
1425 uint32_t min_buf_sz;
1426 uint32_t min_buf_align;
1427 };
1428
1429 struct dp_rxdma_ring {
1430 struct dp_srng refill_buf_ring;
1431 #if 0
1432 struct idr bufs_idr;
1433 /* Protects bufs_idr */
1434 spinlock_t idr_lock;
1435 #else
1436 struct qwx_rx_data *rx_data;
1437 #endif
1438 int bufs_max;
1439 uint8_t freemap[howmany(DP_RXDMA_BUF_RING_SIZE, 8)];
1440 };
1441
1442 enum hal_rx_mon_status {
1443 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
1444 HAL_RX_MON_STATUS_PPDU_DONE,
1445 HAL_RX_MON_STATUS_BUF_DONE,
1446 };
1447
1448 struct hal_rx_user_status {
1449 uint32_t mcs:4,
1450 nss:3,
1451 ofdma_info_valid:1,
1452 dl_ofdma_ru_start_index:7,
1453 dl_ofdma_ru_width:7,
1454 dl_ofdma_ru_size:8;
1455 uint32_t ul_ofdma_user_v0_word0;
1456 uint32_t ul_ofdma_user_v0_word1;
1457 uint32_t ast_index;
1458 uint32_t tid;
1459 uint16_t tcp_msdu_count;
1460 uint16_t udp_msdu_count;
1461 uint16_t other_msdu_count;
1462 uint16_t frame_control;
1463 uint8_t frame_control_info_valid;
1464 uint8_t data_sequence_control_info_valid;
1465 uint16_t first_data_seq_ctrl;
1466 uint32_t preamble_type;
1467 uint16_t ht_flags;
1468 uint16_t vht_flags;
1469 uint16_t he_flags;
1470 uint8_t rs_flags;
1471 uint32_t mpdu_cnt_fcs_ok;
1472 uint32_t mpdu_cnt_fcs_err;
1473 uint32_t mpdu_fcs_ok_bitmap[8];
1474 uint32_t mpdu_ok_byte_count;
1475 uint32_t mpdu_err_byte_count;
1476 };
1477
1478 struct hal_rx_wbm_rel_info {
1479 uint32_t cookie;
1480 enum hal_wbm_rel_src_module err_rel_src;
1481 enum hal_reo_dest_ring_push_reason push_reason;
1482 uint32_t err_code;
1483 int first_msdu;
1484 int last_msdu;
1485 };
1486
1487 #define HAL_INVALID_PEERID 0xffff
1488 #define VHT_SIG_SU_NSS_MASK 0x7
1489
1490 #define HAL_RX_MAX_MCS 12
1491 #define HAL_RX_MAX_NSS 8
1492
1493 #define HAL_TLV_STATUS_PPDU_NOT_DONE HAL_RX_MON_STATUS_PPDU_NOT_DONE
1494 #define HAL_TLV_STATUS_PPDU_DONE HAL_RX_MON_STATUS_PPDU_DONE
1495 #define HAL_TLV_STATUS_BUF_DONE HAL_RX_MON_STATUS_BUF_DONE
1496
1497 struct hal_rx_mon_ppdu_info {
1498 uint32_t ppdu_id;
1499 uint32_t ppdu_ts;
1500 uint32_t num_mpdu_fcs_ok;
1501 uint32_t num_mpdu_fcs_err;
1502 uint32_t preamble_type;
1503 uint16_t chan_num;
1504 uint16_t tcp_msdu_count;
1505 uint16_t tcp_ack_msdu_count;
1506 uint16_t udp_msdu_count;
1507 uint16_t other_msdu_count;
1508 uint16_t peer_id;
1509 uint8_t rate;
1510 uint8_t mcs;
1511 uint8_t nss;
1512 uint8_t bw;
1513 uint8_t vht_flag_values1;
1514 uint8_t vht_flag_values2;
1515 uint8_t vht_flag_values3[4];
1516 uint8_t vht_flag_values4;
1517 uint8_t vht_flag_values5;
1518 uint16_t vht_flag_values6;
1519 uint8_t is_stbc;
1520 uint8_t gi;
1521 uint8_t ldpc;
1522 uint8_t beamformed;
1523 uint8_t rssi_comb;
1524 uint8_t rssi_chain_pri20[HAL_RX_MAX_NSS];
1525 uint8_t tid;
1526 uint16_t ht_flags;
1527 uint16_t vht_flags;
1528 uint16_t he_flags;
1529 uint16_t he_mu_flags;
1530 uint8_t dcm;
1531 uint8_t ru_alloc;
1532 uint8_t reception_type;
1533 uint64_t tsft;
1534 uint64_t rx_duration;
1535 uint16_t frame_control;
1536 uint32_t ast_index;
1537 uint8_t rs_fcs_err;
1538 uint8_t rs_flags;
1539 uint8_t cck_flag;
1540 uint8_t ofdm_flag;
1541 uint8_t ulofdma_flag;
1542 uint8_t frame_control_info_valid;
1543 uint16_t he_per_user_1;
1544 uint16_t he_per_user_2;
1545 uint8_t he_per_user_position;
1546 uint8_t he_per_user_known;
1547 uint16_t he_flags1;
1548 uint16_t he_flags2;
1549 uint8_t he_RU[4];
1550 uint16_t he_data1;
1551 uint16_t he_data2;
1552 uint16_t he_data3;
1553 uint16_t he_data4;
1554 uint16_t he_data5;
1555 uint16_t he_data6;
1556 uint32_t ppdu_len;
1557 uint32_t prev_ppdu_id;
1558 uint32_t device_id;
1559 uint16_t first_data_seq_ctrl;
1560 uint8_t monitor_direct_used;
1561 uint8_t data_sequence_control_info_valid;
1562 uint8_t ltf_size;
1563 uint8_t rxpcu_filter_pass;
1564 char rssi_chain[8][8];
1565 struct hal_rx_user_status userstats;
1566 };
1567
1568 enum dp_mon_status_buf_state {
1569 /* PPDU id matches in dst ring and status ring */
1570 DP_MON_STATUS_MATCH,
1571 /* status ring dma is not done */
1572 DP_MON_STATUS_NO_DMA,
1573 /* status ring is lagging, reap status ring */
1574 DP_MON_STATUS_LAG,
1575 /* status ring is leading, reap dst ring and drop */
1576 DP_MON_STATUS_LEAD,
1577 /* replinish monitor status ring */
1578 DP_MON_STATUS_REPLINISH,
1579 };
1580
1581 struct qwx_pdev_mon_stats {
1582 uint32_t status_ppdu_state;
1583 uint32_t status_ppdu_start;
1584 uint32_t status_ppdu_end;
1585 uint32_t status_ppdu_compl;
1586 uint32_t status_ppdu_start_mis;
1587 uint32_t status_ppdu_end_mis;
1588 uint32_t status_ppdu_done;
1589 uint32_t dest_ppdu_done;
1590 uint32_t dest_mpdu_done;
1591 uint32_t dest_mpdu_drop;
1592 uint32_t dup_mon_linkdesc_cnt;
1593 uint32_t dup_mon_buf_cnt;
1594 uint32_t dest_mon_stuck;
1595 uint32_t dest_mon_not_reaped;
1596 };
1597
1598 struct qwx_mon_data {
1599 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
1600 struct hal_rx_mon_ppdu_info mon_ppdu_info;
1601
1602 uint32_t mon_ppdu_status;
1603 uint32_t mon_last_buf_cookie;
1604 uint64_t mon_last_linkdesc_paddr;
1605 uint16_t chan_noise_floor;
1606 bool hold_mon_dst_ring;
1607 enum dp_mon_status_buf_state buf_state;
1608 bus_addr_t mon_status_paddr;
1609 struct dp_full_mon_mpdu *mon_mpdu;
1610 #ifdef notyet
1611 struct hal_sw_mon_ring_entries sw_mon_entries;
1612 #endif
1613 struct qwx_pdev_mon_stats rx_mon_stats;
1614 #ifdef notyet
1615 /* lock for monitor data */
1616 spinlock_t mon_lock;
1617 struct sk_buff_head rx_status_q;
1618 #endif
1619 };
1620
1621
1622 #define MAX_RXDMA_PER_PDEV 2
1623
1624 struct qwx_pdev_dp {
1625 uint32_t mac_id;
1626 uint32_t mon_dest_ring_stuck_cnt;
1627 #if 0
1628 atomic_t num_tx_pending;
1629 wait_queue_head_t tx_empty_waitq;
1630 #endif
1631 struct dp_rxdma_ring rx_refill_buf_ring;
1632 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
1633 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
1634 struct dp_srng rxdma_mon_dst_ring;
1635 struct dp_srng rxdma_mon_desc_ring;
1636 struct dp_rxdma_ring rxdma_mon_buf_ring;
1637 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
1638 #if 0
1639 struct ieee80211_rx_status rx_status;
1640 #endif
1641 struct qwx_mon_data mon_data;
1642 };
1643
1644 struct qwx_txmgmt_queue {
1645 struct qwx_tx_data data[8];
1646 int cur;
1647 int queued;
1648 };
1649
1650 struct qwx_vif {
1651 uint32_t vdev_id;
1652 enum wmi_vdev_type vdev_type;
1653 enum wmi_vdev_subtype vdev_subtype;
1654 uint32_t beacon_interval;
1655 uint32_t dtim_period;
1656 uint16_t ast_hash;
1657 uint16_t ast_idx;
1658 uint16_t tcl_metadata;
1659 uint8_t hal_addr_search_flags;
1660 uint8_t search_type;
1661
1662 struct qwx_softc *sc;
1663
1664 uint16_t tx_seq_no;
1665 struct wmi_wmm_params_all_arg wmm_params;
1666 TAILQ_ENTRY(qwx_vif) entry;
1667 union {
1668 struct {
1669 uint32_t uapsd;
1670 } sta;
1671 struct {
1672 /* 127 stations; wmi limit */
1673 uint8_t tim_bitmap[16];
1674 uint8_t tim_len;
1675 uint32_t ssid_len;
1676 uint8_t ssid[IEEE80211_NWID_LEN];
1677 bool hidden_ssid;
1678 /* P2P_IE with NoA attribute for P2P_GO case */
1679 uint32_t noa_len;
1680 uint8_t *noa_data;
1681 } ap;
1682 } u;
1683
1684 bool is_started;
1685 bool is_up;
1686 bool ftm_responder;
1687 bool spectral_enabled;
1688 bool ps;
1689 uint32_t aid;
1690 uint8_t bssid[IEEE80211_ADDR_LEN];
1691 #if 0
1692 struct cfg80211_bitrate_mask bitrate_mask;
1693 struct delayed_work connection_loss_work;
1694 #endif
1695 int num_legacy_stations;
1696 int rtscts_prot_mode;
1697 int txpower;
1698 bool rsnie_present;
1699 bool wpaie_present;
1700 bool bcca_zero_sent;
1701 bool do_not_send_tmpl;
1702 struct ieee80211_channel *chan;
1703 #if 0
1704 struct ath11k_arp_ns_offload arp_ns_offload;
1705 struct ath11k_rekey_data rekey_data;
1706 #endif
1707 #ifdef CONFIG_ATH11K_DEBUGFS
1708 struct dentry *debugfs_twt;
1709 #endif /* CONFIG_ATH11K_DEBUGFS */
1710
1711 struct qwx_txmgmt_queue txmgmt;
1712 };
1713
1714 TAILQ_HEAD(qwx_vif_list, qwx_vif);
1715
1716 struct qwx_survey_info {
1717 int8_t noise;
1718 uint64_t time;
1719 uint64_t time_busy;
1720 };
1721
1722 #define ATH11K_IRQ_NUM_MAX 52
1723 #define ATH11K_EXT_IRQ_NUM_MAX 16
1724
1725 struct qwx_ext_irq_grp {
1726 struct qwx_softc *sc;
1727 uint32_t irqs[ATH11K_EXT_IRQ_NUM_MAX];
1728 uint32_t num_irq;
1729 uint32_t grp_id;
1730 uint64_t timestamp;
1731 #if 0
1732 bool napi_enabled;
1733 struct napi_struct napi;
1734 struct net_device napi_ndev;
1735 #endif
1736 };
1737
1738 struct qwx_rx_radiotap_header {
1739 struct ieee80211_radiotap_header wr_ihdr;
1740 } __packed;
1741
1742 #define IWX_RX_RADIOTAP_PRESENT 0 /* TODO add more information */
1743
1744 struct qwx_tx_radiotap_header {
1745 struct ieee80211_radiotap_header wt_ihdr;
1746 } __packed;
1747
1748 #define IWX_TX_RADIOTAP_PRESENT 0 /* TODO add more information */
1749
1750 struct qwx_setkey_task_arg {
1751 struct ieee80211_node *ni;
1752 struct ieee80211_key *k;
1753 int cmd;
1754 #define QWX_ADD_KEY 1
1755 #define QWX_DEL_KEY 2
1756 };
1757
1758 struct qwx_softc {
1759 struct device sc_dev;
1760 struct ieee80211com sc_ic;
1761 uint32_t sc_flags;
1762 int sc_node;
1763
1764 int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int);
1765
1766 struct rwlock ioctl_rwl;
1767
1768 struct task init_task; /* NB: not reference-counted */
1769 struct refcnt task_refs;
1770 struct taskq *sc_nswq;
1771 struct task newstate_task;
1772 enum ieee80211_state ns_nstate;
1773 int ns_arg;
1774
1775 /* Task for setting encryption keys and its arguments. */
1776 struct task setkey_task;
1777 /*
1778 * At present we need to process at most two keys at once:
1779 * Our pairwise key and a group key.
1780 * When hostap mode is implemented this array needs to grow or
1781 * it might become a bottleneck for associations that occur at
1782 * roughly the same time.
1783 */
1784 struct qwx_setkey_task_arg setkey_arg[2];
1785 int setkey_cur;
1786 int setkey_tail;
1787 int setkey_nkeys;
1788
1789 int install_key_done;
1790 int install_key_status;
1791
1792 enum ath11k_11d_state state_11d;
1793 int completed_11d_scan;
1794 uint32_t vdev_id_11d_scan;
1795 struct {
1796 int started;
1797 int completed;
1798 int on_channel;
1799 struct timeout timeout;
1800 enum ath11k_scan_state state;
1801 int vdev_id;
1802 int is_roc;
1803 int roc_freq;
1804 int roc_notify;
1805 } scan;
1806 u_int scan_channel;
1807 struct qwx_survey_info survey[IEEE80211_CHAN_MAX];
1808
1809 int attached;
1810 struct {
1811 u_char *data;
1812 size_t size;
1813 } fw_img[4];
1814 #define QWX_FW_AMSS 0
1815 #define QWX_FW_BOARD 1
1816 #define QWX_FW_M3 2
1817 #define QWX_FW_REGDB 3
1818
1819 int sc_tx_timer;
1820 uint32_t qfullmsk;
1821 #define QWX_MGMT_QUEUE_ID 31
1822
1823 bus_addr_t mem;
1824 struct ath11k_hw_params hw_params;
1825 struct ath11k_hal hal;
1826 struct qwx_ce ce;
1827 struct qwx_dp dp;
1828 struct qwx_pdev_dp pdev_dp;
1829 struct qwx_wmi_base wmi;
1830 struct qwx_htc htc;
1831
1832 enum ath11k_firmware_mode fw_mode;
1833 enum ath11k_crypt_mode crypto_mode;
1834 enum ath11k_hw_txrx_mode frame_mode;
1835
1836 struct qwx_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
1837
1838 uint16_t qmi_txn_id;
1839 int qmi_cal_done;
1840 struct qwx_qmi_ce_cfg qmi_ce_cfg;
1841 struct qwx_qmi_target_info qmi_target;
1842 struct ath11k_targ_cap target_caps;
1843 int num_radios;
1844 uint32_t cc_freq_hz;
1845 uint32_t cfg_tx_chainmask;
1846 uint32_t cfg_rx_chainmask;
1847 int num_tx_chains;
1848 int num_rx_chains;
1849 int num_created_vdevs;
1850 int num_started_vdevs;
1851 uint32_t allocated_vdev_map;
1852 uint32_t free_vdev_map;
1853 int num_peers;
1854 int peer_mapped;
1855 int peer_delete_done;
1856 int vdev_setup_done;
1857 int peer_assoc_done;
1858
1859 struct qwx_dbring_cap *db_caps;
1860 uint32_t num_db_cap;
1861
1862 uint8_t mac_addr[IEEE80211_ADDR_LEN];
1863 int wmi_ready;
1864 uint32_t wlan_init_status;
1865
1866 uint32_t pktlog_defs_checksum;
1867
1868 struct qwx_vif_list vif_list;
1869 struct qwx_pdev pdevs[MAX_RADIOS];
1870 struct {
1871 enum WMI_HOST_WLAN_BAND supported_bands;
1872 uint32_t pdev_id;
1873 } target_pdev_ids[MAX_RADIOS];
1874 uint8_t target_pdev_count;
1875 uint32_t pdevs_active;
1876 int pdevs_macaddr_valid;
1877 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
1878
1879 struct {
1880 uint32_t service;
1881 uint32_t instance;
1882 uint32_t node;
1883 uint32_t port;
1884 } qrtr_server;
1885
1886 struct qmi_response_type_v01 qmi_resp;
1887
1888 struct qwx_dmamem *fwmem;
1889 int expect_fwmem_req;
1890 int fwmem_ready;
1891 int fw_init_done;
1892
1893 int ctl_resp;
1894
1895 struct qwx_dmamem *m3_mem;
1896
1897 struct timeout mon_reap_timer;
1898 #define ATH11K_MON_TIMER_INTERVAL 10
1899
1900 /* Provided by attachment driver: */
1901 struct qwx_ops ops;
1902 bus_dma_tag_t sc_dmat;
1903 enum ath11k_hw_rev sc_hw_rev;
1904 struct qwx_device_id id;
1905 char sc_bus_str[4]; /* "pci" or "ahb" */
1906 int num_msivec;
1907 uint32_t msi_addr_lo;
1908 uint32_t msi_addr_hi;
1909 uint32_t msi_data_start;
1910 const struct qwx_msi_config *msi_cfg;
1911 uint32_t msi_ce_irqmask;
1912
1913 struct qmi_wlanfw_request_mem_ind_msg_v01 *sc_req_mem_ind;
1914
1915 caddr_t sc_drvbpf;
1916
1917 union {
1918 struct qwx_rx_radiotap_header th;
1919 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
1920 } sc_rxtapu;
1921 #define sc_rxtap sc_rxtapu.th
1922 int sc_rxtap_len;
1923
1924 union {
1925 struct qwx_tx_radiotap_header th;
1926 uint8_t pad[IEEE80211_RADIOTAP_HDRLEN];
1927 } sc_txtapu;
1928 #define sc_txtap sc_txtapu.th
1929 int sc_txtap_len;
1930 };
1931
1932 int qwx_ce_intr(void *);
1933 int qwx_ext_intr(void *);
1934 int qwx_dp_service_srng(struct qwx_softc *, int);
1935
1936 int qwx_init_hw_params(struct qwx_softc *);
1937 int qwx_attach(struct qwx_softc *);
1938 void qwx_detach(struct qwx_softc *);
1939 int qwx_activate(struct device *, int);
1940
1941 void qwx_core_deinit(struct qwx_softc *);
1942 void qwx_ce_cleanup_pipes(struct qwx_softc *);
1943
1944 int qwx_ioctl(struct ifnet *, u_long, caddr_t);
1945 void qwx_start(struct ifnet *);
1946 void qwx_watchdog(struct ifnet *);
1947 int qwx_media_change(struct ifnet *);
1948 void qwx_init_task(void *);
1949 int qwx_newstate(struct ieee80211com *, enum ieee80211_state, int);
1950 void qwx_newstate_task(void *);
1951
1952 struct ath11k_peer {
1953 #if 0
1954 struct list_head list;
1955 struct ieee80211_sta *sta;
1956 #endif
1957 int vdev_id;
1958 #if 0
1959 u8 addr[ETH_ALEN];
1960 #endif
1961 int peer_id;
1962 uint16_t ast_hash;
1963 uint8_t pdev_id;
1964 uint16_t hw_peer_id;
1965 #if 0
1966 /* protected by ab->data_lock */
1967 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
1968 #endif
1969 struct dp_rx_tid rx_tid[IEEE80211_NUM_TID + 1];
1970 #if 0
1971 /* peer id based rhashtable list pointer */
1972 struct rhash_head rhash_id;
1973 /* peer addr based rhashtable list pointer */
1974 struct rhash_head rhash_addr;
1975
1976 /* Info used in MMIC verification of
1977 * RX fragments
1978 */
1979 struct crypto_shash *tfm_mmic;
1980 u8 mcast_keyidx;
1981 u8 ucast_keyidx;
1982 u16 sec_type;
1983 u16 sec_type_grp;
1984 bool is_authorized;
1985 bool dp_setup_done;
1986 #endif
1987 };
1988
1989 struct qwx_node {
1990 struct ieee80211_node ni;
1991 struct ath11k_peer peer;
1992 unsigned int flags;
1993 #define QWX_NODE_FLAG_HAVE_PAIRWISE_KEY 0x01
1994 #define QWX_NODE_FLAG_HAVE_GROUP_KEY 0x02
1995 };
1996
1997 struct ieee80211_node *qwx_node_alloc(struct ieee80211com *);
1998 int qwx_set_key(struct ieee80211com *, struct ieee80211_node *,
1999 struct ieee80211_key *);
2000 void qwx_delete_key(struct ieee80211com *, struct ieee80211_node *,
2001 struct ieee80211_key *);
2002
2003 void qwx_qrtr_recv_msg(struct qwx_softc *, struct mbuf *);
2004
2005 int qwx_hal_srng_init(struct qwx_softc *);
2006
2007 int qwx_ce_alloc_pipes(struct qwx_softc *);
2008 void qwx_ce_free_pipes(struct qwx_softc *);
2009 void qwx_ce_rx_post_buf(struct qwx_softc *);
2010 void qwx_ce_get_shadow_config(struct qwx_softc *, uint32_t **, uint32_t *);
2011
2012 static inline unsigned int
qwx_roundup_pow_of_two(unsigned int i)2013 qwx_roundup_pow_of_two(unsigned int i)
2014 {
2015 return (powerof2(i) ? i : (1 << (fls(i) - 1)));
2016 }
2017
2018 static inline unsigned int
qwx_ce_get_attr_flags(struct qwx_softc * sc,int ce_id)2019 qwx_ce_get_attr_flags(struct qwx_softc *sc, int ce_id)
2020 {
2021 KASSERT(ce_id < sc->hw_params.ce_count);
2022 return sc->hw_params.host_ce_config[ce_id].flags;
2023 }
2024
qwx_tid_to_ac(uint32_t tid)2025 static inline enum ieee80211_edca_ac qwx_tid_to_ac(uint32_t tid)
2026 {
2027 return (((tid == 0) || (tid == 3)) ? EDCA_AC_BE :
2028 ((tid == 1) || (tid == 2)) ? EDCA_AC_BK :
2029 ((tid == 4) || (tid == 5)) ? EDCA_AC_VI :
2030 EDCA_AC_VO);
2031 }
2032