Home
last modified time | relevance | path

Searched defs:rFPGA0_TxGainStage (Results 1 – 15 of 15) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h9 #define rFPGA0_TxGainStage 0x80c macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h9 #define rFPGA0_TxGainStage 0x80c macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h9 #define rFPGA0_TxGainStage 0x80c macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8188eu/include/
H A Dhal8188e_phy_reg.h21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8188eu/include/
H A Dhal8188e_phy_reg.h21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8188eu/include/
H A Dhal8188e_phy_reg.h21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h50 #define rFPGA0_TxGainStage 0x80c macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h50 #define rFPGA0_TxGainStage 0x80c macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h50 #define rFPGA0_TxGainStage 0x80c macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h90 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h90 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h90 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h97 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h97 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h97 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro