1 /* radare - LGPL - Copyright 2011-2015 -- pancake */
2
3 #include <string.h>
4
5 #include <r_types.h>
6 #include <r_lib.h>
7 #include <r_asm.h>
8 #include <r_anal.h>
9
10 enum {
11 GPR_G0 = 0,
12 GPR_G1 = 1,
13 GPR_G2 = 2,
14 GPR_G3 = 3,
15 GPR_G4 = 4,
16 GPR_G5 = 5,
17 GPR_G6 = 6,
18 GPR_G7 = 7,
19 GPR_O0 = 8,
20 GPR_O1 = 9,
21 GPR_O2 = 10,
22 GPR_O3 = 11,
23 GPR_O4 = 12,
24 GPR_O5 = 13,
25 GPR_O6 = 14,
26 GPR_O7 = 15,
27 GPR_L0 = 16,
28 GPR_L1 = 17,
29 GPR_L2 = 18,
30 GPR_L3 = 19,
31 GPR_L4 = 20,
32 GPR_L5 = 21,
33 GPR_L6 = 22,
34 GPR_L7 = 23,
35 GPR_I0 = 24,
36 GPR_I1 = 25,
37 GPR_I2 = 26,
38 GPR_I3 = 27,
39 GPR_I4 = 28,
40 GPR_I5 = 29,
41 GPR_I6 = 30,
42 GPR_I7 = 31,
43 };
44
45 const char * gpr_regs[] = {"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
46 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
47 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
48 "i0", "i1", "i2", "i3", "i4", "i5", "i6","i7"};
49
50 enum {
51 ICC_A = 0x8,
52 ICC_CC = 0xd,
53 ICC_CS = 0x5,
54 ICC_E = 0x1,
55 ICC_G = 0xa,
56 ICC_GE = 0xb,
57 ICC_GU = 0xc,
58 ICC_L = 0x3,
59 ICC_LE = 0x2,
60 ICC_LEU = 0x4,
61 ICC_N = 0x0,
62 ICC_NE = 0x9,
63 ICC_NEG = 0x6,
64 ICC_POS = 0xe,
65 ICC_VC = 0xf,
66 ICC_VS = 0x7,
67 };
68
69 enum {
70 FCC_A = 0x8,
71 FCC_E = 0x9,
72 FCC_G = 0x6,
73 FCC_GE = 0xb,
74 FCC_L = 0x4,
75 FCC_LE = 0xd,
76 FCC_LG = 0x2,
77 FCC_N = 0x0,
78 FCC_NE = 0x1,
79 FCC_O = 0xf,
80 FCC_U = 0x7,
81 FCC_UE = 0xa,
82 FCC_UG = 0x5,
83 FCC_UGE = 0xc,
84 FCC_UL = 0x3,
85 FCC_ULE = 0xe,
86 };
87 /* Define some additional conditions that are nor mappable to
88 the existing R_ANAL_COND* ones and need to be handled in a
89 special way. */
90 enum {
91 R_ANAL_COND_ALWAYS = -1,
92 R_ANAL_COND_NEVER = -2,
93 R_ANAL_COND_UNKNOWN = -3,
94 };
95
icc_to_r_cond(const int cond)96 static int icc_to_r_cond(const int cond) {
97 /* we treat signed and unsigned the same here */
98 switch(cond) {
99 case ICC_A: return R_ANAL_COND_ALWAYS;
100 case ICC_CC: return R_ANAL_COND_GE;
101 case ICC_CS: return R_ANAL_COND_LT;
102 case ICC_E: return R_ANAL_COND_EQ;
103 case ICC_G: return R_ANAL_COND_GT;
104 case ICC_GE: return R_ANAL_COND_GE;
105 case ICC_GU: return R_ANAL_COND_GT;
106 case ICC_L: return R_ANAL_COND_LT;
107 case ICC_LE: return R_ANAL_COND_LE;
108 case ICC_LEU: return R_ANAL_COND_LE;
109 case ICC_N: return R_ANAL_COND_NEVER;
110 case ICC_NE: return R_ANAL_COND_NE;
111 case ICC_NEG:
112 case ICC_POS:
113 case ICC_VC:
114 case ICC_VS:
115 default: return R_ANAL_COND_UNKNOWN;
116 }
117 }
118
fcc_to_r_cond(const int cond)119 static int fcc_to_r_cond(const int cond) {
120 switch (cond) {
121 case FCC_A: return R_ANAL_COND_ALWAYS;
122 case FCC_E: return R_ANAL_COND_EQ;
123 case FCC_G: return R_ANAL_COND_GT;
124 case FCC_GE: return R_ANAL_COND_GE;
125 case FCC_L: return R_ANAL_COND_LT;
126 case FCC_LE: return R_ANAL_COND_LE;
127 case FCC_LG: return R_ANAL_COND_NE;
128 case FCC_N: return R_ANAL_COND_NEVER;
129 case FCC_NE: return R_ANAL_COND_NE;
130 case FCC_O:
131 case FCC_U:
132 case FCC_UE:
133 case FCC_UG:
134 case FCC_UGE:
135 case FCC_UL:
136 case FCC_ULE:
137 default:
138 return R_ANAL_COND_UNKNOWN;
139 }
140 }
141
142 #define X_OP(i) (((i) >> 30) & 0x3)
143 #define X_OP2(i) (((i) >> 22) & 0x7)
144 #define X_OP3(i) (((i) >> 19) & 0x3f)
145 #define X_COND(i) (((i) >> 25) & 0x1f)
146
147 #define X_RD(i) (((i) >> 25) & 0x1f)
148 #define X_RS1(i) (((i) >> 14) & 0x1f)
149 #define X_LDST_I(i) (((i) >> 13) & 1)
150 #define X_ASI(i) (((i) >> 5) & 0xff)
151 #define X_RS2(i) (((i) >> 0) & 0x1f)
152 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
153 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
154 #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
155 #define X_IMM22(i) X_DISP22 (i)
156 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
157
158 /* These are for v9. */
159 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
160 #define X_DISP19(i) (((i) >> 0) & 0x7ffff)
161 #define X_MEMBAR(i) ((i) & 0x7f)
162
163 enum {
164 OP_0 = 0,
165 OP_1 = 1,
166 OP_2 = 2,
167 OP_3 = 3,
168 };
169
170 enum {
171 OP2_ILLTRAP = 0,
172 OP2_BPcc = 1,
173 OP2_Bicc = 2,
174 OP2_BPr = 3,
175 OP2_SETHI = 4,
176 OP2_FBPfcc = 5,
177 OP2_FBfcc = 6,
178 OP2_INV = 7,
179 };
180
181 enum {
182 OP32_ADD = 0x00,
183 OP32_ADDcc = 0x10,
184 OP32_TADDcc = 0x20,
185 OP32_WRY = 0x30, /* or WRCCR WRASI WRASR WRFPRS SIR */
186 OP32_AND = 0x01,
187 OP32_ANDcc = 0x11,
188 OP32_TSUBcc = 0x21,
189 OP32_SAVED = 0x31, /* or RESTORED */
190 OP32_OR = 0x02,
191 OP32_ORcc = 0x12,
192 OP32_TADDccTV = 0x22,
193 OP32_WRPR = 0x32,
194 OP32_XOR = 0x03,
195 OP32_XORcc = 0x13,
196 OP32_TSUBccTV = 0x23,
197 OP32_SUB = 0x04,
198 OP32_SUBcc = 0x14,
199 OP32_MULSccD = 0x24,
200 OP32_FPop1 = 0x34,
201 OP32_ANDN = 0x05,
202 OP32_ANDNcc = 0x15,
203 OP32_SLL = 0x25, /* or SLLX */
204 OP32_FPop2 = 0x35,
205 OP32_ORN = 0x06,
206 OP32_ORNcc = 0x16,
207 OP32_SRL = 0x26, /* or SLRX */
208 OP32_XNOR = 0x07,
209 OP32_XNORcc = 0x17,
210 OP32_SRA = 0x27, /* or SRAX */
211 OP32_ADDC = 0x08,
212 OP32_ADDCcc = 0x18,
213 OP32_RDY = 0x28, /* or RDCCR RDASI RDTICK RDPC RDFPRS RDASR
214 MEMBAR STBAR */
215 OP32_JMPL = 0x38,
216 OP32_MULX = 0x09,
217 OP32_RETURN = 0x39,
218 OP32_UMUL = 0x0a,
219 OP32_UMULcc = 0x1a,
220 OP32_RDPR = 0x2a,
221 OP32_Tcc = 0x3a,
222 OP32_SMULD = 0x0b,
223 OP32_SMULcc = 0x1b,
224 OP32_FLUSHW = 0x2b,
225 OP32_FLUSH = 0x3b,
226 OP32_SUBC = 0x0c,
227 OP32_SUBCcc = 0x1c,
228 OP32_MOVcc = 0x2c,
229 OP32_SAVE = 0x3c,
230 OP32_UDIVX = 0x0d,
231 OP32_SDIVX = 0x2d,
232 OP32_RESTORE = 0x3d,
233 OP32_UDIV = 0x0e,
234 OP32_UDIVcc = 0x1e,
235 OP32_POPC = 0x2e,
236 OP32_DONE = 0x3e, /* or RETRY */
237 OP32_SDIV = 0x0f,
238 OP32_SDIVcc = 0x1f,
239 OP32_MOVr = 0x2f,
240 /* always invalid */
241 OP32_INV1 = 0x33,
242 OP32_INV2 = 0x19,
243 OP32_INV3 = 0x29,
244 OP32_INV4 = 0x1d,
245 OP32_INV5 = 0x3f,
246 /* invalid under certain conditions */
247 OP32_CONDINV1 = 0x30,
248 OP32_CONDINV2 = 0x28,
249 OP32_CONDINV3 = 0x2e,
250 };
251
252 enum {
253 OP33_INV1 = 0x31,
254 OP33_INV2 = 0x35,
255 OP33_INV3 = 0x28,
256 OP33_INV4 = 0x38,
257 OP33_INV5 = 0x29,
258 OP33_INV6 = 0x39,
259 OP33_INV7 = 0x2a,
260 OP33_INV8 = 0x3a,
261 OP33_INV9 = 0x2b,
262 OP33_INV10 = 0x3b,
263 OP33_INV11 = 0x0c,
264 OP33_INV12 = 0x1c,
265 OP33_INV13 = 0x2c,
266 OP33_INV14 = 0x2e,
267 OP33_INV15 = 0x2f,
268 OP33_INV16 = 0x3f,
269 };
270
get_immed_sgnext(const ut64 insn,const ut8 nbit)271 static st64 get_immed_sgnext(const ut64 insn, const ut8 nbit) {
272 const ut64 mask = ~(((ut64)1 << (nbit + 1)) - 1);
273 return (st64) ((insn & ~mask)
274 | (((insn & ((ut64)1 << nbit)) >> nbit) * mask));
275 }
276
value_fill_addr_pc_disp(const ut64 addr,const st64 disp)277 static RAnalValue * value_fill_addr_pc_disp(const ut64 addr, const st64 disp) {
278 RAnalValue *val = r_anal_value_new();
279 val->base = addr + disp;
280 return val;
281 }
282
value_fill_addr_reg_regdelta(RAnal const * const anal,const int ireg,const int iregdelta)283 static RAnalValue * value_fill_addr_reg_regdelta(RAnal const * const anal, const int ireg, const int iregdelta) {
284 RAnalValue *val = r_anal_value_new();
285 val->reg = r_reg_get(anal->reg, gpr_regs[ireg], R_REG_TYPE_GPR);
286 val->reg = r_reg_get(anal->reg, gpr_regs[iregdelta], R_REG_TYPE_GPR);
287 return val;
288 }
289
value_fill_addr_reg_disp(RAnal const * const anal,const int ireg,const st64 disp)290 static RAnalValue * value_fill_addr_reg_disp(RAnal const * const anal, const int ireg, const st64 disp) {
291 RAnalValue *val = r_anal_value_new();
292 val->reg = r_reg_get(anal->reg, gpr_regs[ireg], R_REG_TYPE_GPR);
293 val->delta = disp;
294 return val;
295 }
296
anal_call(RAnalOp * op,const ut32 insn,const ut64 addr)297 static void anal_call(RAnalOp *op, const ut32 insn, const ut64 addr) {
298 const st64 disp = (get_immed_sgnext(insn, 29) * 4);
299 op->type = R_ANAL_OP_TYPE_CALL;
300 op->dst = value_fill_addr_pc_disp(addr, disp);
301 op->jump = addr + disp;
302 op->fail = addr + 4;
303 }
304
anal_jmpl(RAnal const * const anal,RAnalOp * op,const ut32 insn,const ut64 addr)305 static void anal_jmpl(RAnal const * const anal, RAnalOp *op, const ut32 insn, const ut64 addr) {
306 st64 disp = 0;
307 if (X_LDST_I (insn)) {
308 disp = get_immed_sgnext (insn, 12);
309 }
310
311 if (X_RD(insn) == GPR_O7) {
312 op->type = R_ANAL_OP_TYPE_UCALL;
313 op->fail = addr + 4;
314 } else if (X_RD(insn) == GPR_G0
315 && X_LDST_I(insn) == 1
316 && (X_RS1(insn) == GPR_I7 || X_RS1(insn) == GPR_O7)
317 && disp == 8) {
318 op->type = R_ANAL_OP_TYPE_RET;
319 op->eob = true;
320 return;
321 }
322 else {
323 op->type = R_ANAL_OP_TYPE_UJMP;
324 op->eob = true;
325 }
326
327 if(X_LDST_I(insn)) {
328 op->dst = value_fill_addr_reg_disp(anal, X_RS1(insn), disp);
329 } else {
330 op->dst = value_fill_addr_reg_regdelta(anal, X_RS1(insn), X_RS2(insn));
331 }
332 }
333
anal_branch(RAnalOp * op,const ut32 insn,const ut64 addr)334 static void anal_branch(RAnalOp *op, const ut32 insn, const ut64 addr) {
335 st64 disp = 0;
336 int r_cond = 0;
337 op->eob = true;
338
339 /* handle the conditions */
340 if(X_OP2(insn) == OP2_Bicc || X_OP2(insn) == OP2_BPcc) {
341 r_cond = icc_to_r_cond (X_COND(insn));
342 } else if(X_OP2(insn) == OP2_FBfcc || X_OP2(insn) == OP2_FBPfcc) {
343 r_cond = fcc_to_r_cond (X_COND(insn));
344 } else if(X_OP2(insn) == OP2_BPr) {
345 r_cond = R_ANAL_COND_UNKNOWN;
346 }
347
348 if (r_cond == R_ANAL_COND_ALWAYS) {
349 op->type = R_ANAL_OP_TYPE_JMP;
350 } else if (r_cond == R_ANAL_COND_NEVER) {
351 op->type = R_ANAL_OP_TYPE_NOP;
352 return;
353 } else {
354 op->type = R_ANAL_OP_TYPE_CJMP;
355 op->fail = addr + 4;
356 }
357
358
359 /* handle displacement */
360 if (X_OP2 (insn) == OP2_Bicc || X_OP2 (insn) == OP2_FBfcc) {
361 disp = get_immed_sgnext(insn, 21) * 4;
362 } else if (X_OP2(insn) == OP2_BPcc || X_OP2 (insn) == OP2_FBPfcc) {
363 disp = get_immed_sgnext (insn, 18) * 4;
364 } else if (X_OP2(insn) == OP2_BPr) {
365 disp = get_immed_sgnext (X_DISP16 (insn), 15) * 4;
366 }
367 op->dst = value_fill_addr_pc_disp (addr, disp);
368 op->jump = addr + disp;
369 }
370
371 // TODO: this implementation is just a fast hack. needs to be rewritten and completed
sparc_op(RAnal * anal,RAnalOp * op,ut64 addr,const ut8 * data,int len,RAnalOpMask mask)372 static int sparc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len, RAnalOpMask mask) {
373 int sz = 4;
374 ut32 insn;
375
376 op->family = R_ANAL_OP_FAMILY_CPU;
377 op->addr = addr;
378 op->size = sz;
379
380 if(!anal->big_endian) {
381 ((char*)&insn)[0] = data[3];
382 ((char*)&insn)[1] = data[2];
383 ((char*)&insn)[2] = data[1];
384 ((char*)&insn)[3] = data[0];
385 } else {
386 memcpy(&insn, data, sz);
387 }
388
389 if (X_OP(insn) == OP_0) {
390 switch(X_OP2(insn)) {
391 case OP2_ILLTRAP:
392 case OP2_INV:
393 op->type = R_ANAL_OP_TYPE_ILL;
394 sz = 0; /* make r_core_anal_bb stop */
395 break;
396 case OP2_BPcc:
397 case OP2_Bicc:
398 case OP2_BPr:
399 case OP2_FBPfcc:
400 case OP2_FBfcc:
401 anal_branch(op, insn, addr);
402 break;
403 }
404 } else if(X_OP(insn) == OP_1) {
405 anal_call(op, insn, addr);
406 } else if(X_OP(insn) == OP_2) {
407 switch(X_OP3(insn))
408 {
409 case OP32_INV1:
410 case OP32_INV2:
411 case OP32_INV3:
412 case OP32_INV4:
413 case OP32_INV5:
414 op->type = R_ANAL_OP_TYPE_ILL;
415 sz = 0; /* make r_core_anal_bb stop */
416 break;
417 case OP32_CONDINV1:
418 if(X_RD(insn) == 1) {
419 op->type = R_ANAL_OP_TYPE_ILL;
420 sz = 0; /* make r_core_anal_bb stop */
421 }
422 break;
423 case OP32_CONDINV2:
424 if(X_RS1(insn) == 1) {
425 op->type = R_ANAL_OP_TYPE_ILL;
426 sz = 0; /* make r_core_anal_bb stop */
427 }
428 break;
429 case OP32_CONDINV3:
430 if(X_RS1(insn) != 0) {
431 op->type = R_ANAL_OP_TYPE_ILL;
432 sz = 0; /* make r_core_anal_bb stop */
433 }
434 break;
435
436 case OP32_JMPL:
437 anal_jmpl(anal, op, insn, addr);
438 break;
439 }
440 } else if (X_OP(insn) == OP_3) {
441 switch(X_OP3(insn)) {
442 case OP33_INV1:
443 case OP33_INV2:
444 case OP33_INV3:
445 case OP33_INV4:
446 case OP33_INV5:
447 case OP33_INV6:
448 case OP33_INV7:
449 case OP33_INV8:
450 case OP33_INV9:
451 case OP33_INV10:
452 case OP33_INV11:
453 case OP33_INV12:
454 case OP33_INV13:
455 case OP33_INV14:
456 case OP33_INV15:
457 case OP33_INV16:
458 op->type = R_ANAL_OP_TYPE_ILL;
459 sz = 0; /* make r_core_anal_bb stop */
460 break;
461 }
462 }
463
464 return sz;
465 }
466
set_reg_profile(RAnal * anal)467 static bool set_reg_profile(RAnal *anal) {
468 /* As far as I can see, sparc v9 register and instruction set
469 don't depened on bits of the running application.
470 But: They depend on the bits of the consuming application,
471 that is the bits radare had been compiled with.
472 See sys/procfs_isa.h on a Solaris10 Sparc machine and
473 'man 4 core' for reference.
474 */
475 const char *p =
476 "=PC pc\n"
477 "=SP o6\n"
478 "=BP i6\n"
479 "=A0 g0\n"
480 "=A1 g1\n"
481 /* prgregset_t for _LP64 */
482 "gpr g0 .64 0 0\n"
483 "gpr g1 .64 8 0\n"
484 "gpr g2 .64 16 0\n"
485 "gpr g3 .64 24 0\n"
486 "gpr g4 .64 32 0\n"
487 "gpr g5 .64 40 0\n"
488 "gpr g6 .64 48 0\n"
489 "gpr g7 .64 56 0\n"
490 "gpr o0 .64 64 0\n"
491 "gpr o1 .64 72 0\n"
492 "gpr o2 .64 80 0\n"
493 "gpr o3 .64 88 0\n"
494 "gpr o4 .64 96 0\n"
495 "gpr o5 .64 104 0\n"
496 "gpr o6 .64 112 0\n"
497 "gpr o7 .64 120 0\n"
498 "gpr l0 .64 128 0\n"
499 "gpr l1 .64 136 0\n"
500 "gpr l2 .64 144 0\n"
501 "gpr l3 .64 152 0\n"
502 "gpr l4 .64 160 0\n"
503 "gpr l5 .64 168 0\n"
504 "gpr l6 .64 176 0\n"
505 "gpr l7 .64 184 0\n"
506 "gpr i0 .64 192 0\n"
507 "gpr i1 .64 200 0\n"
508 "gpr i2 .64 208 0\n"
509 "gpr i3 .64 216 0\n"
510 "gpr i4 .64 224 0\n"
511 "gpr i5 .64 232 0\n"
512 "gpr i6 .64 240 0\n"
513 "gpr i7 .64 248 0\n"
514 "gpr ccr .64 256 0\n"
515 "gpr pc .64 264 0\n"
516 "gpr ncp .64 272 0\n"
517 "gpr y .64 280 0\n"
518 "gpr asi .64 288 0\n"
519 "gpr fprs .64 296 0\n"
520 /* beginning of prfpregset_t for __sparcv9 */
521 "fpu sf0 .32 304 0\n"
522 "fpu sf1 .32 308 0\n"
523 "fpu sf2 .32 312 0\n"
524 "fpu sf3 .32 316 0\n"
525 "fpu sf4 .32 320 0\n"
526 "fpu sf5 .32 324 0\n"
527 "fpu sf6 .32 328 0\n"
528 "fpu sf7 .32 332 0\n"
529 "fpu sf8 .32 336 0\n"
530 "fpu sf9 .32 340 0\n"
531 "fpu sf10 .32 344 0\n"
532 "fpu sf11 .32 348 0\n"
533 "fpu sf12 .32 352 0\n"
534 "fpu sf13 .32 356 0\n"
535 "fpu sf14 .32 360 0\n"
536 "fpu sf15 .32 364 0\n"
537 "fpu sf16 .32 368 0\n"
538 "fpu sf17 .32 372 0\n"
539 "fpu sf18 .32 376 0\n"
540 "fpu sf19 .32 380 0\n"
541 "fpu sf20 .32 384 0\n"
542 "fpu sf21 .32 388 0\n"
543 "fpu sf22 .32 392 0\n"
544 "fpu sf23 .32 396 0\n"
545 "fpu sf24 .32 400 0\n"
546 "fpu sf25 .32 404 0\n"
547 "fpu sf26 .32 408 0\n"
548 "fpu sf27 .32 412 0\n"
549 "fpu sf28 .32 416 0\n"
550 "fpu sf29 .32 420 0\n"
551 "fpu sf30 .32 424 0\n"
552 "fpu sf31 .32 428 0\n"
553 "fpu df0 .64 304 0\n" /* sf0 sf1 */
554 "fpu df2 .64 312 0\n" /* sf2 sf3 */
555 "fpu df4 .64 320 0\n" /* sf4 sf5 */
556 "fpu df6 .64 328 0\n" /* sf6 sf7 */
557 "fpu df8 .64 336 0\n" /* sf8 sf9 */
558 "fpu df10 .64 344 0\n" /* sf10 sf11 */
559 "fpu df12 .64 352 0\n" /* sf12 sf13 */
560 "fpu df14 .64 360 0\n" /* sf14 sf15 */
561 "fpu df16 .64 368 0\n" /* sf16 sf17 */
562 "fpu df18 .64 376 0\n" /* sf18 sf19 */
563 "fpu df20 .64 384 0\n" /* sf20 sf21 */
564 "fpu df22 .64 392 0\n" /* sf22 sf23 */
565 "fpu df24 .64 400 0\n" /* sf24 sf25 */
566 "fpu df26 .64 408 0\n" /* sf26 sf27 */
567 "fpu df28 .64 416 0\n" /* sf28 sf29 */
568 "fpu df30 .64 424 0\n" /* sf30 sf31 */
569 "fpu df32 .64 432 0\n"
570 "fpu df34 .64 440 0\n"
571 "fpu df36 .64 448 0\n"
572 "fpu df38 .64 456 0\n"
573 "fpu df40 .64 464 0\n"
574 "fpu df42 .64 472 0\n"
575 "fpu df44 .64 480 0\n"
576 "fpu df46 .64 488 0\n"
577 "fpu df48 .64 496 0\n"
578 "fpu df50 .64 504 0\n"
579 "fpu df52 .64 512 0\n"
580 "fpu df54 .64 520 0\n"
581 "fpu df56 .64 528 0\n"
582 "fpu df58 .64 536 0\n"
583 "fpu df60 .64 544 0\n"
584 "fpu df62 .64 552 0\n"
585 "fpu qf0 .128 304 0\n" /* sf0 sf1 sf2 sf3 */
586 "fpu qf4 .128 320 0\n" /* sf4 sf5 sf6 sf7 */
587 "fpu qf8 .128 336 0\n" /* sf8 sf9 sf10 sf11 */
588 "fpu qf12 .128 352 0\n" /* sf12 sf13 sf14 sf15 */
589 "fpu qf16 .128 368 0\n" /* sf16 sf17 sf18 sf19 */
590 "fpu qf20 .128 384 0\n" /* sf20 sf21 sf22 sf23 */
591 "fpu qf24 .128 400 0\n" /* sf24 sf25 sf26 sf27 */
592 "fpu qf28 .128 416 0\n" /* sf28 sf29 sf30 sf31 */
593 "fpu qf32 .128 432 0\n" /* df32 df34 */
594 "fpu qf36 .128 448 0\n" /* df36 df38 */
595 "fpu qf40 .128 464 0\n" /* df40 df42 */
596 "fpu qf44 .128 480 0\n" /* df44 df46 */
597 "fpu qf48 .128 496 0\n" /* df48 df50 */
598 "fpu qf52 .128 512 0\n" /* df52 df54 */
599 "fpu qf56 .128 528 0\n" /* df56 df68 */
600 "fpu qf60 .128 544 0\n" /* df60 df62 */
601 "gpr fsr .64 560 0\n"; /* note that
602 we've left out the filler */
603 return r_reg_set_profile_string (anal->reg, p);
604 }
605
archinfo(RAnal * anal,int q)606 static int archinfo(RAnal *anal, int q) {
607 return 4; /* :D */
608 }
609
610 RAnalPlugin r_anal_plugin_sparc_gnu = {
611 .name = "sparc.gnu",
612 .desc = "SPARC analysis plugin",
613 .license = "LGPL3",
614 .arch = "sparc",
615 .bits = 32 | 64,
616 .op = &sparc_op,
617 .archinfo = archinfo,
618 .set_reg_profile = set_reg_profile,
619 };
620
621 #ifndef R2_PLUGIN_INCORE
622 R_API RLibStruct radare_plugin = {
623 .type = R_LIB_TYPE_ANAL,
624 .data = &r_anal_plugin_sparc_gnu,
625 .version = R2_VERSION
626 };
627 #endif
628