1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28
29 #include <drm/drm_device.h>
30 #include <drm/radeon_drm.h>
31
32 #include "radeon.h"
33
34 #include "atom.h"
35 #include "atom-bits.h"
36 #include "radeon_asic.h"
37 #include "radeon_atombios.h"
38 #include "radeon_legacy_encoders.h"
39
40 union atom_supported_devices {
41 struct _ATOM_SUPPORTED_DEVICES_INFO info;
42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
44 };
45
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
47 ATOM_GPIO_I2C_ASSIGMENT *gpio,
48 u8 index)
49 {
50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
51 if ((rdev->family == CHIP_R420) ||
52 (rdev->family == CHIP_R423) ||
53 (rdev->family == CHIP_RV410)) {
54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
57 gpio->ucClkMaskShift = 0x19;
58 gpio->ucDataMaskShift = 0x18;
59 }
60 }
61
62 /* some evergreen boards have bad data for this entry */
63 if (ASIC_IS_DCE4(rdev)) {
64 if ((index == 7) &&
65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
66 (gpio->sucI2cId.ucAccess == 0)) {
67 gpio->sucI2cId.ucAccess = 0x97;
68 gpio->ucDataMaskShift = 8;
69 gpio->ucDataEnShift = 8;
70 gpio->ucDataY_Shift = 8;
71 gpio->ucDataA_Shift = 8;
72 }
73 }
74
75 /* some DCE3 boards have bad data for this entry */
76 if (ASIC_IS_DCE3(rdev)) {
77 if ((index == 4) &&
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
79 (gpio->sucI2cId.ucAccess == 0x94))
80 gpio->sucI2cId.ucAccess = 0x14;
81 }
82 }
83
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
85 {
86 struct radeon_i2c_bus_rec i2c;
87
88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
89
90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
101 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
106
107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
108 i2c.hw_capable = true;
109 else
110 i2c.hw_capable = false;
111
112 if (gpio->sucI2cId.ucAccess == 0xa0)
113 i2c.mm_i2c = true;
114 else
115 i2c.mm_i2c = false;
116
117 i2c.i2c_id = gpio->sucI2cId.ucAccess;
118
119 if (i2c.mask_clk_reg)
120 i2c.valid = true;
121 else
122 i2c.valid = false;
123
124 return i2c;
125 }
126
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
128 uint8_t id)
129 {
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137
138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
139 i2c.valid = false;
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 gpio = &i2c_info->asGPIO_Info[0];
148 for (i = 0; i < num_indices; i++) {
149
150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
151
152 if (gpio->sucI2cId.ucAccess == id) {
153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
154 break;
155 }
156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
158 }
159 }
160
161 return i2c;
162 }
163
radeon_atombios_i2c_init(struct radeon_device * rdev)164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
165 {
166 struct atom_context *ctx = rdev->mode_info.atom_context;
167 ATOM_GPIO_I2C_ASSIGMENT *gpio;
168 struct radeon_i2c_bus_rec i2c;
169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
170 struct _ATOM_GPIO_I2C_INFO *i2c_info;
171 uint16_t data_offset, size;
172 int i, num_indices;
173 char stmp[32];
174
175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
177
178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
179 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
180
181 gpio = &i2c_info->asGPIO_Info[0];
182 for (i = 0; i < num_indices; i++) {
183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
184
185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
186
187 if (i2c.valid) {
188 snprintf(stmp, sizeof(stmp), "0x%x", i2c.i2c_id);
189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
190 }
191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
193 }
194 }
195 }
196
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
198 u8 id)
199 {
200 struct atom_context *ctx = rdev->mode_info.atom_context;
201 struct radeon_gpio_rec gpio;
202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
203 struct _ATOM_GPIO_PIN_LUT *gpio_info;
204 ATOM_GPIO_PIN_ASSIGNMENT *pin;
205 u16 data_offset, size;
206 int i, num_indices;
207
208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
209 gpio.valid = false;
210
211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
213
214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
216
217 pin = gpio_info->asGPIO_Pin;
218 for (i = 0; i < num_indices; i++) {
219 if (id == pin->ucGPIO_ID) {
220 gpio.id = pin->ucGPIO_ID;
221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
222 gpio.shift = pin->ucGpioPinBitShift;
223 gpio.mask = (1 << pin->ucGpioPinBitShift);
224 gpio.valid = true;
225 break;
226 }
227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
229 }
230 }
231
232 return gpio;
233 }
234
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
236 struct radeon_gpio_rec *gpio)
237 {
238 struct radeon_hpd hpd;
239 u32 reg;
240
241 memset(&hpd, 0, sizeof(struct radeon_hpd));
242
243 if (ASIC_IS_DCE6(rdev))
244 reg = SI_DC_GPIO_HPD_A;
245 else if (ASIC_IS_DCE4(rdev))
246 reg = EVERGREEN_DC_GPIO_HPD_A;
247 else
248 reg = AVIVO_DC_GPIO_HPD_A;
249
250 hpd.gpio = *gpio;
251 if (gpio->reg == reg) {
252 switch(gpio->mask) {
253 case (1 << 0):
254 hpd.hpd = RADEON_HPD_1;
255 break;
256 case (1 << 8):
257 hpd.hpd = RADEON_HPD_2;
258 break;
259 case (1 << 16):
260 hpd.hpd = RADEON_HPD_3;
261 break;
262 case (1 << 24):
263 hpd.hpd = RADEON_HPD_4;
264 break;
265 case (1 << 26):
266 hpd.hpd = RADEON_HPD_5;
267 break;
268 case (1 << 28):
269 hpd.hpd = RADEON_HPD_6;
270 break;
271 default:
272 hpd.hpd = RADEON_HPD_NONE;
273 break;
274 }
275 } else
276 hpd.hpd = RADEON_HPD_NONE;
277 return hpd;
278 }
279
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)280 static bool radeon_atom_apply_quirks(struct drm_device *dev,
281 uint32_t supported_device,
282 int *connector_type,
283 struct radeon_i2c_bus_rec *i2c_bus,
284 uint16_t *line_mux,
285 struct radeon_hpd *hpd)
286 {
287 #ifdef __linux__
288 struct pci_dev *pdev = to_pci_dev(dev->dev);
289 #else
290 struct pci_dev *pdev = dev->pdev;
291 #endif
292
293 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
294 if ((pdev->device == 0x791e) &&
295 (pdev->subsystem_vendor == 0x1043) &&
296 (pdev->subsystem_device == 0x826d)) {
297 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
298 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
299 *connector_type = DRM_MODE_CONNECTOR_DVID;
300 }
301
302 /* Asrock RS600 board lists the DVI port as HDMI */
303 if ((pdev->device == 0x7941) &&
304 (pdev->subsystem_vendor == 0x1849) &&
305 (pdev->subsystem_device == 0x7941)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
309 }
310
311 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
312 if ((pdev->device == 0x796e) &&
313 (pdev->subsystem_vendor == 0x1462) &&
314 (pdev->subsystem_device == 0x7302)) {
315 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
316 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
317 return false;
318 }
319
320 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
321 if ((pdev->device == 0x7941) &&
322 (pdev->subsystem_vendor == 0x147b) &&
323 (pdev->subsystem_device == 0x2412)) {
324 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
325 return false;
326 }
327
328 /* Falcon NW laptop lists vga ddc line for LVDS */
329 if ((pdev->device == 0x5653) &&
330 (pdev->subsystem_vendor == 0x1462) &&
331 (pdev->subsystem_device == 0x0291)) {
332 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
333 i2c_bus->valid = false;
334 *line_mux = 53;
335 }
336 }
337
338 /* HIS X1300 is DVI+VGA, not DVI+DVI */
339 if ((pdev->device == 0x7146) &&
340 (pdev->subsystem_vendor == 0x17af) &&
341 (pdev->subsystem_device == 0x2058)) {
342 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
343 return false;
344 }
345
346 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
347 if ((pdev->device == 0x7142) &&
348 (pdev->subsystem_vendor == 0x1458) &&
349 (pdev->subsystem_device == 0x2134)) {
350 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
351 return false;
352 }
353
354
355 /* Funky macbooks */
356 if ((pdev->device == 0x71C5) &&
357 (pdev->subsystem_vendor == 0x106b) &&
358 (pdev->subsystem_device == 0x0080)) {
359 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
360 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
361 return false;
362 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
363 *line_mux = 0x90;
364 }
365
366 /* mac rv630, rv730, others */
367 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
368 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
369 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
370 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
371 }
372
373 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
374 if ((pdev->device == 0x9598) &&
375 (pdev->subsystem_vendor == 0x1043) &&
376 (pdev->subsystem_device == 0x01da)) {
377 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
378 *connector_type = DRM_MODE_CONNECTOR_DVII;
379 }
380 }
381
382 /* ASUS HD 3600 board lists the DVI port as HDMI */
383 if ((pdev->device == 0x9598) &&
384 (pdev->subsystem_vendor == 0x1043) &&
385 (pdev->subsystem_device == 0x01e4)) {
386 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
387 *connector_type = DRM_MODE_CONNECTOR_DVII;
388 }
389 }
390
391 /* ASUS HD 3450 board lists the DVI port as HDMI */
392 if ((pdev->device == 0x95C5) &&
393 (pdev->subsystem_vendor == 0x1043) &&
394 (pdev->subsystem_device == 0x01e2)) {
395 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
396 *connector_type = DRM_MODE_CONNECTOR_DVII;
397 }
398 }
399
400 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
401 * HDMI + VGA reporting as HDMI
402 */
403 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
404 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
405 *connector_type = DRM_MODE_CONNECTOR_VGA;
406 *line_mux = 0;
407 }
408 }
409
410 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
411 * on the laptop and a DVI port on the docking station and
412 * both share the same encoder, hpd pin, and ddc line.
413 * So while the bios table is technically correct,
414 * we drop the DVI port here since xrandr has no concept of
415 * encoders and will try and drive both connectors
416 * with different crtcs which isn't possible on the hardware
417 * side and leaves no crtcs for LVDS or VGA.
418 */
419 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
420 (pdev->subsystem_vendor == 0x1025) &&
421 (pdev->subsystem_device == 0x013c)) {
422 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
423 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
424 /* actually it's a DVI-D port not DVI-I */
425 *connector_type = DRM_MODE_CONNECTOR_DVID;
426 return false;
427 }
428 }
429
430 /* XFX Pine Group device rv730 reports no VGA DDC lines
431 * even though they are wired up to record 0x93
432 */
433 if ((pdev->device == 0x9498) &&
434 (pdev->subsystem_vendor == 0x1682) &&
435 (pdev->subsystem_device == 0x2452) &&
436 (i2c_bus->valid == false) &&
437 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
438 struct radeon_device *rdev = dev->dev_private;
439 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
440 }
441
442 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
443 if (((pdev->device == 0x9802) ||
444 (pdev->device == 0x9805) ||
445 (pdev->device == 0x9806)) &&
446 (pdev->subsystem_vendor == 0x1734) &&
447 (pdev->subsystem_device == 0x11bd)) {
448 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
449 *connector_type = DRM_MODE_CONNECTOR_DVII;
450 *line_mux = 0x3103;
451 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
452 *connector_type = DRM_MODE_CONNECTOR_DVII;
453 }
454 }
455
456 return true;
457 }
458
459 static const int supported_devices_connector_convert[] = {
460 DRM_MODE_CONNECTOR_Unknown,
461 DRM_MODE_CONNECTOR_VGA,
462 DRM_MODE_CONNECTOR_DVII,
463 DRM_MODE_CONNECTOR_DVID,
464 DRM_MODE_CONNECTOR_DVIA,
465 DRM_MODE_CONNECTOR_SVIDEO,
466 DRM_MODE_CONNECTOR_Composite,
467 DRM_MODE_CONNECTOR_LVDS,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_HDMIA,
471 DRM_MODE_CONNECTOR_HDMIB,
472 DRM_MODE_CONNECTOR_Unknown,
473 DRM_MODE_CONNECTOR_Unknown,
474 DRM_MODE_CONNECTOR_9PinDIN,
475 DRM_MODE_CONNECTOR_DisplayPort
476 };
477
478 static const uint16_t supported_devices_connector_object_id_convert[] = {
479 CONNECTOR_OBJECT_ID_NONE,
480 CONNECTOR_OBJECT_ID_VGA,
481 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
482 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
483 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
484 CONNECTOR_OBJECT_ID_COMPOSITE,
485 CONNECTOR_OBJECT_ID_SVIDEO,
486 CONNECTOR_OBJECT_ID_LVDS,
487 CONNECTOR_OBJECT_ID_9PIN_DIN,
488 CONNECTOR_OBJECT_ID_9PIN_DIN,
489 CONNECTOR_OBJECT_ID_DISPLAYPORT,
490 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
491 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
492 CONNECTOR_OBJECT_ID_SVIDEO
493 };
494
495 static const int object_connector_convert[] = {
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_DVII,
498 DRM_MODE_CONNECTOR_DVII,
499 DRM_MODE_CONNECTOR_DVID,
500 DRM_MODE_CONNECTOR_DVID,
501 DRM_MODE_CONNECTOR_VGA,
502 DRM_MODE_CONNECTOR_Composite,
503 DRM_MODE_CONNECTOR_SVIDEO,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_Unknown,
506 DRM_MODE_CONNECTOR_9PinDIN,
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_HDMIA,
509 DRM_MODE_CONNECTOR_HDMIB,
510 DRM_MODE_CONNECTOR_LVDS,
511 DRM_MODE_CONNECTOR_9PinDIN,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_Unknown,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_DisplayPort,
516 DRM_MODE_CONNECTOR_eDP,
517 DRM_MODE_CONNECTOR_Unknown
518 };
519
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)520 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
521 {
522 struct radeon_device *rdev = dev->dev_private;
523 struct radeon_mode_info *mode_info = &rdev->mode_info;
524 struct atom_context *ctx = mode_info->atom_context;
525 int index = GetIndexIntoMasterTable(DATA, Object_Header);
526 u16 size, data_offset;
527 u8 frev, crev;
528 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
529 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
530 ATOM_OBJECT_TABLE *router_obj;
531 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
532 ATOM_OBJECT_HEADER *obj_header;
533 int i, j, k, path_size, device_support;
534 int connector_type;
535 u16 igp_lane_info, conn_id, connector_object_id;
536 struct radeon_i2c_bus_rec ddc_bus;
537 struct radeon_router router;
538 struct radeon_gpio_rec gpio;
539 struct radeon_hpd hpd;
540
541 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
542 return false;
543
544 if (crev < 2)
545 return false;
546
547 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
548 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
549 (ctx->bios + data_offset +
550 le16_to_cpu(obj_header->usDisplayPathTableOffset));
551 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
554 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
557 router_obj = (ATOM_OBJECT_TABLE *)
558 (ctx->bios + data_offset +
559 le16_to_cpu(obj_header->usRouterObjectTableOffset));
560 device_support = le16_to_cpu(obj_header->usDeviceSupport);
561
562 path_size = 0;
563 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
564 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
565 ATOM_DISPLAY_OBJECT_PATH *path;
566 addr += path_size;
567 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
568 path_size += le16_to_cpu(path->usSize);
569
570 if (device_support & le16_to_cpu(path->usDeviceTag)) {
571 uint8_t con_obj_id, con_obj_num;
572
573 con_obj_id =
574 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
575 >> OBJECT_ID_SHIFT;
576 con_obj_num =
577 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
578 >> ENUM_ID_SHIFT;
579
580 /* TODO CV support */
581 if (le16_to_cpu(path->usDeviceTag) ==
582 ATOM_DEVICE_CV_SUPPORT)
583 continue;
584
585 /* IGP chips */
586 if ((rdev->flags & RADEON_IS_IGP) &&
587 (con_obj_id ==
588 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
589 uint16_t igp_offset = 0;
590 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
591
592 index =
593 GetIndexIntoMasterTable(DATA,
594 IntegratedSystemInfo);
595
596 if (atom_parse_data_header(ctx, index, &size, &frev,
597 &crev, &igp_offset)) {
598
599 if (crev >= 2) {
600 igp_obj =
601 (ATOM_INTEGRATED_SYSTEM_INFO_V2
602 *) (ctx->bios + igp_offset);
603
604 if (igp_obj) {
605 uint32_t slot_config, ct;
606
607 if (con_obj_num == 1)
608 slot_config =
609 igp_obj->
610 ulDDISlot1Config;
611 else
612 slot_config =
613 igp_obj->
614 ulDDISlot2Config;
615
616 ct = (slot_config >> 16) & 0xff;
617 connector_type =
618 object_connector_convert
619 [ct];
620 connector_object_id = ct;
621 igp_lane_info =
622 slot_config & 0xffff;
623 } else
624 continue;
625 } else
626 continue;
627 } else {
628 igp_lane_info = 0;
629 connector_type =
630 object_connector_convert[con_obj_id];
631 connector_object_id = con_obj_id;
632 }
633 } else {
634 igp_lane_info = 0;
635 connector_type =
636 object_connector_convert[con_obj_id];
637 connector_object_id = con_obj_id;
638 }
639
640 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
641 continue;
642
643 router.ddc_valid = false;
644 router.cd_valid = false;
645 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
646 uint8_t grph_obj_type =
647 (le16_to_cpu(path->usGraphicObjIds[j]) &
648 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
649
650 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
651 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
652 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
653 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
654 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
655 (ctx->bios + data_offset +
656 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
657 ATOM_ENCODER_CAP_RECORD *cap_record;
658 u16 caps = 0;
659
660 while (record->ucRecordSize > 0 &&
661 record->ucRecordType > 0 &&
662 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
663 switch (record->ucRecordType) {
664 case ATOM_ENCODER_CAP_RECORD_TYPE:
665 cap_record =(ATOM_ENCODER_CAP_RECORD *)
666 record;
667 caps = le16_to_cpu(cap_record->usEncoderCap);
668 break;
669 }
670 record = (ATOM_COMMON_RECORD_HEADER *)
671 ((char *)record + record->ucRecordSize);
672 }
673 radeon_add_atom_encoder(dev,
674 encoder_obj,
675 le16_to_cpu
676 (path->
677 usDeviceTag),
678 caps);
679 }
680 }
681 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
682 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
683 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
684 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
685 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
686 (ctx->bios + data_offset +
687 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
688 ATOM_I2C_RECORD *i2c_record;
689 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
690 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
691 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
692 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
693 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
694 (ctx->bios + data_offset +
695 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
696 u8 *num_dst_objs = (u8 *)
697 ((u8 *)router_src_dst_table + 1 +
698 (router_src_dst_table->ucNumberOfSrc * 2));
699 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
700 int enum_id;
701
702 router.router_id = router_obj_id;
703 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
704 if (le16_to_cpu(path->usConnObjectId) ==
705 le16_to_cpu(dst_objs[enum_id]))
706 break;
707 }
708
709 while (record->ucRecordSize > 0 &&
710 record->ucRecordType > 0 &&
711 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
712 switch (record->ucRecordType) {
713 case ATOM_I2C_RECORD_TYPE:
714 i2c_record =
715 (ATOM_I2C_RECORD *)
716 record;
717 i2c_config =
718 (ATOM_I2C_ID_CONFIG_ACCESS *)
719 &i2c_record->sucI2cId;
720 router.i2c_info =
721 radeon_lookup_i2c_gpio(rdev,
722 i2c_config->
723 ucAccess);
724 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
725 break;
726 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
727 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
728 record;
729 router.ddc_valid = true;
730 router.ddc_mux_type = ddc_path->ucMuxType;
731 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
732 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
733 break;
734 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
735 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
736 record;
737 router.cd_valid = true;
738 router.cd_mux_type = cd_path->ucMuxType;
739 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
740 router.cd_mux_state = cd_path->ucMuxState[enum_id];
741 break;
742 }
743 record = (ATOM_COMMON_RECORD_HEADER *)
744 ((char *)record + record->ucRecordSize);
745 }
746 }
747 }
748 }
749 }
750
751 /* look up gpio for ddc, hpd */
752 ddc_bus.valid = false;
753 hpd.hpd = RADEON_HPD_NONE;
754 if ((le16_to_cpu(path->usDeviceTag) &
755 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
756 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
757 if (le16_to_cpu(path->usConnObjectId) ==
758 le16_to_cpu(con_obj->asObjects[j].
759 usObjectID)) {
760 ATOM_COMMON_RECORD_HEADER
761 *record =
762 (ATOM_COMMON_RECORD_HEADER
763 *)
764 (ctx->bios + data_offset +
765 le16_to_cpu(con_obj->
766 asObjects[j].
767 usRecordOffset));
768 ATOM_I2C_RECORD *i2c_record;
769 ATOM_HPD_INT_RECORD *hpd_record;
770 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
771
772 while (record->ucRecordSize > 0 &&
773 record->ucRecordType > 0 &&
774 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
775 switch (record->ucRecordType) {
776 case ATOM_I2C_RECORD_TYPE:
777 i2c_record =
778 (ATOM_I2C_RECORD *)
779 record;
780 i2c_config =
781 (ATOM_I2C_ID_CONFIG_ACCESS *)
782 &i2c_record->sucI2cId;
783 ddc_bus = radeon_lookup_i2c_gpio(rdev,
784 i2c_config->
785 ucAccess);
786 break;
787 case ATOM_HPD_INT_RECORD_TYPE:
788 hpd_record =
789 (ATOM_HPD_INT_RECORD *)
790 record;
791 gpio = radeon_atombios_lookup_gpio(rdev,
792 hpd_record->ucHPDIntGPIOID);
793 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
794 hpd.plugged_state = hpd_record->ucPlugged_PinState;
795 break;
796 }
797 record =
798 (ATOM_COMMON_RECORD_HEADER
799 *) ((char *)record
800 +
801 record->
802 ucRecordSize);
803 }
804 break;
805 }
806 }
807 }
808
809 /* needed for aux chan transactions */
810 ddc_bus.hpd = hpd.hpd;
811
812 conn_id = le16_to_cpu(path->usConnObjectId);
813
814 if (!radeon_atom_apply_quirks
815 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
816 &ddc_bus, &conn_id, &hpd))
817 continue;
818
819 radeon_add_atom_connector(dev,
820 conn_id,
821 le16_to_cpu(path->
822 usDeviceTag),
823 connector_type, &ddc_bus,
824 igp_lane_info,
825 connector_object_id,
826 &hpd,
827 &router);
828
829 }
830 }
831
832 radeon_link_encoder_connector(dev);
833 return true;
834 }
835
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)836 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
837 int connector_type,
838 uint16_t devices)
839 {
840 struct radeon_device *rdev = dev->dev_private;
841
842 if (rdev->flags & RADEON_IS_IGP) {
843 return supported_devices_connector_object_id_convert
844 [connector_type];
845 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
846 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
847 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
848 struct radeon_mode_info *mode_info = &rdev->mode_info;
849 struct atom_context *ctx = mode_info->atom_context;
850 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
851 uint16_t size, data_offset;
852 uint8_t frev, crev;
853 ATOM_XTMDS_INFO *xtmds;
854
855 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
856 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
857
858 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
859 if (connector_type == DRM_MODE_CONNECTOR_DVII)
860 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
861 else
862 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
863 } else {
864 if (connector_type == DRM_MODE_CONNECTOR_DVII)
865 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
866 else
867 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
868 }
869 } else
870 return supported_devices_connector_object_id_convert
871 [connector_type];
872 } else {
873 return supported_devices_connector_object_id_convert
874 [connector_type];
875 }
876 }
877
878 struct bios_connector {
879 bool valid;
880 uint16_t line_mux;
881 uint16_t devices;
882 int connector_type;
883 struct radeon_i2c_bus_rec ddc_bus;
884 struct radeon_hpd hpd;
885 };
886
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)887 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
888 drm_device
889 *dev)
890 {
891 struct radeon_device *rdev = dev->dev_private;
892 struct radeon_mode_info *mode_info = &rdev->mode_info;
893 struct atom_context *ctx = mode_info->atom_context;
894 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
895 uint16_t size, data_offset;
896 uint8_t frev, crev;
897 uint16_t device_support;
898 uint8_t dac;
899 union atom_supported_devices *supported_devices;
900 int i, j, max_device;
901 struct bios_connector *bios_connectors;
902 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
903 struct radeon_router router;
904
905 router.ddc_valid = false;
906 router.cd_valid = false;
907
908 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
909 if (!bios_connectors)
910 return false;
911
912 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
913 &data_offset)) {
914 kfree(bios_connectors);
915 return false;
916 }
917
918 supported_devices =
919 (union atom_supported_devices *)(ctx->bios + data_offset);
920
921 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
922
923 if (frev > 1)
924 max_device = ATOM_MAX_SUPPORTED_DEVICE;
925 else
926 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
927
928 for (i = 0; i < max_device; i++) {
929 ATOM_CONNECTOR_INFO_I2C ci;
930
931 if (frev > 1)
932 ci = supported_devices->info_2d1.asConnInfo[i];
933 else
934 ci = supported_devices->info.asConnInfo[i];
935
936 bios_connectors[i].valid = false;
937
938 if (!(device_support & (1 << i))) {
939 continue;
940 }
941
942 if (i == ATOM_DEVICE_CV_INDEX) {
943 DRM_DEBUG_KMS("Skipping Component Video\n");
944 continue;
945 }
946
947 bios_connectors[i].connector_type =
948 supported_devices_connector_convert[ci.sucConnectorInfo.
949 sbfAccess.
950 bfConnectorType];
951
952 if (bios_connectors[i].connector_type ==
953 DRM_MODE_CONNECTOR_Unknown)
954 continue;
955
956 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
957
958 bios_connectors[i].line_mux =
959 ci.sucI2cId.ucAccess;
960
961 /* give tv unique connector ids */
962 if (i == ATOM_DEVICE_TV1_INDEX) {
963 bios_connectors[i].ddc_bus.valid = false;
964 bios_connectors[i].line_mux = 50;
965 } else if (i == ATOM_DEVICE_TV2_INDEX) {
966 bios_connectors[i].ddc_bus.valid = false;
967 bios_connectors[i].line_mux = 51;
968 } else if (i == ATOM_DEVICE_CV_INDEX) {
969 bios_connectors[i].ddc_bus.valid = false;
970 bios_connectors[i].line_mux = 52;
971 } else
972 bios_connectors[i].ddc_bus =
973 radeon_lookup_i2c_gpio(rdev,
974 bios_connectors[i].line_mux);
975
976 if ((crev > 1) && (frev > 1)) {
977 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
978 switch (isb) {
979 case 0x4:
980 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
981 break;
982 case 0xa:
983 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
984 break;
985 default:
986 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
987 break;
988 }
989 } else {
990 if (i == ATOM_DEVICE_DFP1_INDEX)
991 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
992 else if (i == ATOM_DEVICE_DFP2_INDEX)
993 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
994 else
995 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
996 }
997
998 /* Always set the connector type to VGA for CRT1/CRT2. if they are
999 * shared with a DVI port, we'll pick up the DVI connector when we
1000 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1001 */
1002 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1003 bios_connectors[i].connector_type =
1004 DRM_MODE_CONNECTOR_VGA;
1005
1006 if (!radeon_atom_apply_quirks
1007 (dev, (1 << i), &bios_connectors[i].connector_type,
1008 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1009 &bios_connectors[i].hpd))
1010 continue;
1011
1012 bios_connectors[i].valid = true;
1013 bios_connectors[i].devices = (1 << i);
1014
1015 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1016 radeon_add_atom_encoder(dev,
1017 radeon_get_encoder_enum(dev,
1018 (1 << i),
1019 dac),
1020 (1 << i),
1021 0);
1022 else
1023 radeon_add_legacy_encoder(dev,
1024 radeon_get_encoder_enum(dev,
1025 (1 << i),
1026 dac),
1027 (1 << i));
1028 }
1029
1030 /* combine shared connectors */
1031 for (i = 0; i < max_device; i++) {
1032 if (bios_connectors[i].valid) {
1033 for (j = 0; j < max_device; j++) {
1034 if (bios_connectors[j].valid && (i != j)) {
1035 if (bios_connectors[i].line_mux ==
1036 bios_connectors[j].line_mux) {
1037 /* make sure not to combine LVDS */
1038 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1039 bios_connectors[i].line_mux = 53;
1040 bios_connectors[i].ddc_bus.valid = false;
1041 continue;
1042 }
1043 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1044 bios_connectors[j].line_mux = 53;
1045 bios_connectors[j].ddc_bus.valid = false;
1046 continue;
1047 }
1048 /* combine analog and digital for DVI-I */
1049 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1050 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1051 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1052 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1053 bios_connectors[i].devices |=
1054 bios_connectors[j].devices;
1055 bios_connectors[i].connector_type =
1056 DRM_MODE_CONNECTOR_DVII;
1057 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1058 bios_connectors[i].hpd =
1059 bios_connectors[j].hpd;
1060 bios_connectors[j].valid = false;
1061 }
1062 }
1063 }
1064 }
1065 }
1066 }
1067
1068 /* add the connectors */
1069 for (i = 0; i < max_device; i++) {
1070 if (bios_connectors[i].valid) {
1071 uint16_t connector_object_id =
1072 atombios_get_connector_object_id(dev,
1073 bios_connectors[i].connector_type,
1074 bios_connectors[i].devices);
1075 radeon_add_atom_connector(dev,
1076 bios_connectors[i].line_mux,
1077 bios_connectors[i].devices,
1078 bios_connectors[i].
1079 connector_type,
1080 &bios_connectors[i].ddc_bus,
1081 0,
1082 connector_object_id,
1083 &bios_connectors[i].hpd,
1084 &router);
1085 }
1086 }
1087
1088 radeon_link_encoder_connector(dev);
1089
1090 kfree(bios_connectors);
1091 return true;
1092 }
1093
1094 union firmware_info {
1095 ATOM_FIRMWARE_INFO info;
1096 ATOM_FIRMWARE_INFO_V1_2 info_12;
1097 ATOM_FIRMWARE_INFO_V1_3 info_13;
1098 ATOM_FIRMWARE_INFO_V1_4 info_14;
1099 ATOM_FIRMWARE_INFO_V2_1 info_21;
1100 ATOM_FIRMWARE_INFO_V2_2 info_22;
1101 };
1102
1103 union igp_info {
1104 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1106 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1107 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1108 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1109 };
1110
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1111 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1112 {
1113 struct radeon_mode_info *mode_info = &rdev->mode_info;
1114 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1115 union igp_info *igp_info;
1116 u8 frev, crev;
1117 u16 data_offset;
1118
1119 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1120 &frev, &crev, &data_offset)) {
1121 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1122 data_offset);
1123 rdev->clock.vco_freq =
1124 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1125 }
1126 }
1127
radeon_atom_get_clock_info(struct drm_device * dev)1128 bool radeon_atom_get_clock_info(struct drm_device *dev)
1129 {
1130 struct radeon_device *rdev = dev->dev_private;
1131 struct radeon_mode_info *mode_info = &rdev->mode_info;
1132 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1133 union firmware_info *firmware_info;
1134 uint8_t frev, crev;
1135 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1136 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1137 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1138 struct radeon_pll *spll = &rdev->clock.spll;
1139 struct radeon_pll *mpll = &rdev->clock.mpll;
1140 uint16_t data_offset;
1141
1142 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1143 &frev, &crev, &data_offset)) {
1144 firmware_info =
1145 (union firmware_info *)(mode_info->atom_context->bios +
1146 data_offset);
1147 /* pixel clocks */
1148 p1pll->reference_freq =
1149 le16_to_cpu(firmware_info->info.usReferenceClock);
1150 p1pll->reference_div = 0;
1151
1152 if ((frev < 2) && (crev < 2))
1153 p1pll->pll_out_min =
1154 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1155 else
1156 p1pll->pll_out_min =
1157 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1158 p1pll->pll_out_max =
1159 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1160
1161 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1162 p1pll->lcd_pll_out_min =
1163 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1164 if (p1pll->lcd_pll_out_min == 0)
1165 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1166 p1pll->lcd_pll_out_max =
1167 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1168 if (p1pll->lcd_pll_out_max == 0)
1169 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1170 } else {
1171 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1172 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1173 }
1174
1175 if (p1pll->pll_out_min == 0) {
1176 if (ASIC_IS_AVIVO(rdev))
1177 p1pll->pll_out_min = 64800;
1178 else
1179 p1pll->pll_out_min = 20000;
1180 }
1181
1182 p1pll->pll_in_min =
1183 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1184 p1pll->pll_in_max =
1185 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1186
1187 *p2pll = *p1pll;
1188
1189 /* system clock */
1190 if (ASIC_IS_DCE4(rdev))
1191 spll->reference_freq =
1192 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1193 else
1194 spll->reference_freq =
1195 le16_to_cpu(firmware_info->info.usReferenceClock);
1196 spll->reference_div = 0;
1197
1198 spll->pll_out_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1200 spll->pll_out_max =
1201 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1202
1203 /* ??? */
1204 if (spll->pll_out_min == 0) {
1205 if (ASIC_IS_AVIVO(rdev))
1206 spll->pll_out_min = 64800;
1207 else
1208 spll->pll_out_min = 20000;
1209 }
1210
1211 spll->pll_in_min =
1212 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1213 spll->pll_in_max =
1214 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1215
1216 /* memory clock */
1217 if (ASIC_IS_DCE4(rdev))
1218 mpll->reference_freq =
1219 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1220 else
1221 mpll->reference_freq =
1222 le16_to_cpu(firmware_info->info.usReferenceClock);
1223 mpll->reference_div = 0;
1224
1225 mpll->pll_out_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1227 mpll->pll_out_max =
1228 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1229
1230 /* ??? */
1231 if (mpll->pll_out_min == 0) {
1232 if (ASIC_IS_AVIVO(rdev))
1233 mpll->pll_out_min = 64800;
1234 else
1235 mpll->pll_out_min = 20000;
1236 }
1237
1238 mpll->pll_in_min =
1239 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1240 mpll->pll_in_max =
1241 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1242
1243 rdev->clock.default_sclk =
1244 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1245 rdev->clock.default_mclk =
1246 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1247
1248 if (ASIC_IS_DCE4(rdev)) {
1249 rdev->clock.default_dispclk =
1250 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1251 if (rdev->clock.default_dispclk == 0) {
1252 if (ASIC_IS_DCE6(rdev))
1253 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1254 else if (ASIC_IS_DCE5(rdev))
1255 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1256 else
1257 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1258 }
1259 /* set a reasonable default for DP */
1260 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1261 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1262 rdev->clock.default_dispclk / 100);
1263 rdev->clock.default_dispclk = 60000;
1264 }
1265 rdev->clock.dp_extclk =
1266 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1267 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1268 }
1269 *dcpll = *p1pll;
1270
1271 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1272 if (rdev->clock.max_pixel_clock == 0)
1273 rdev->clock.max_pixel_clock = 40000;
1274
1275 /* not technically a clock, but... */
1276 rdev->mode_info.firmware_flags =
1277 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1278
1279 if (ASIC_IS_DCE8(rdev))
1280 rdev->clock.vco_freq =
1281 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1282 else if (ASIC_IS_DCE5(rdev))
1283 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1284 else if (ASIC_IS_DCE41(rdev))
1285 radeon_atombios_get_dentist_vco_freq(rdev);
1286 else
1287 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1288
1289 if (rdev->clock.vco_freq == 0)
1290 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1291
1292 return true;
1293 }
1294
1295 return false;
1296 }
1297
radeon_atombios_sideport_present(struct radeon_device * rdev)1298 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1299 {
1300 struct radeon_mode_info *mode_info = &rdev->mode_info;
1301 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1302 union igp_info *igp_info;
1303 u8 frev, crev;
1304 u16 data_offset;
1305
1306 /* sideport is AMD only */
1307 if (rdev->family == CHIP_RS600)
1308 return false;
1309
1310 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1311 &frev, &crev, &data_offset)) {
1312 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1313 data_offset);
1314 switch (crev) {
1315 case 1:
1316 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1317 return true;
1318 break;
1319 case 2:
1320 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1321 return true;
1322 break;
1323 default:
1324 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1325 break;
1326 }
1327 }
1328 return false;
1329 }
1330
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1331 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1332 struct radeon_encoder_int_tmds *tmds)
1333 {
1334 struct drm_device *dev = encoder->base.dev;
1335 struct radeon_device *rdev = dev->dev_private;
1336 struct radeon_mode_info *mode_info = &rdev->mode_info;
1337 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1338 uint16_t data_offset;
1339 struct _ATOM_TMDS_INFO *tmds_info;
1340 uint8_t frev, crev;
1341 uint16_t maxfreq;
1342 int i;
1343
1344 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1345 &frev, &crev, &data_offset)) {
1346 tmds_info =
1347 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1348 data_offset);
1349
1350 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1351 for (i = 0; i < 4; i++) {
1352 tmds->tmds_pll[i].freq =
1353 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1354 tmds->tmds_pll[i].value =
1355 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1356 tmds->tmds_pll[i].value |=
1357 (tmds_info->asMiscInfo[i].
1358 ucPLL_VCO_Gain & 0x3f) << 6;
1359 tmds->tmds_pll[i].value |=
1360 (tmds_info->asMiscInfo[i].
1361 ucPLL_DutyCycle & 0xf) << 12;
1362 tmds->tmds_pll[i].value |=
1363 (tmds_info->asMiscInfo[i].
1364 ucPLL_VoltageSwing & 0xf) << 16;
1365
1366 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1367 tmds->tmds_pll[i].freq,
1368 tmds->tmds_pll[i].value);
1369
1370 if (maxfreq == tmds->tmds_pll[i].freq) {
1371 tmds->tmds_pll[i].freq = 0xffffffff;
1372 break;
1373 }
1374 }
1375 return true;
1376 }
1377 return false;
1378 }
1379
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1380 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1381 struct radeon_atom_ss *ss,
1382 int id)
1383 {
1384 struct radeon_mode_info *mode_info = &rdev->mode_info;
1385 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1386 uint16_t data_offset, size;
1387 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1388 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1389 uint8_t frev, crev;
1390 int i, num_indices;
1391
1392 memset(ss, 0, sizeof(struct radeon_atom_ss));
1393 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1394 &frev, &crev, &data_offset)) {
1395 ss_info =
1396 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1397
1398 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1399 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1400 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1401 ((u8 *)&ss_info->asSS_Info[0]);
1402 for (i = 0; i < num_indices; i++) {
1403 if (ss_assign->ucSS_Id == id) {
1404 ss->percentage =
1405 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1406 ss->type = ss_assign->ucSpreadSpectrumType;
1407 ss->step = ss_assign->ucSS_Step;
1408 ss->delay = ss_assign->ucSS_Delay;
1409 ss->range = ss_assign->ucSS_Range;
1410 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1411 return true;
1412 }
1413 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1414 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1415 }
1416 }
1417 return false;
1418 }
1419
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1420 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1421 struct radeon_atom_ss *ss,
1422 int id)
1423 {
1424 struct radeon_mode_info *mode_info = &rdev->mode_info;
1425 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1426 u16 data_offset, size;
1427 union igp_info *igp_info;
1428 u8 frev, crev;
1429 u16 percentage = 0, rate = 0;
1430
1431 /* get any igp specific overrides */
1432 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1433 &frev, &crev, &data_offset)) {
1434 igp_info = (union igp_info *)
1435 (mode_info->atom_context->bios + data_offset);
1436 switch (crev) {
1437 case 6:
1438 switch (id) {
1439 case ASIC_INTERNAL_SS_ON_TMDS:
1440 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1441 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1442 break;
1443 case ASIC_INTERNAL_SS_ON_HDMI:
1444 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1445 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1446 break;
1447 case ASIC_INTERNAL_SS_ON_LVDS:
1448 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1449 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1450 break;
1451 }
1452 break;
1453 case 7:
1454 switch (id) {
1455 case ASIC_INTERNAL_SS_ON_TMDS:
1456 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1457 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1458 break;
1459 case ASIC_INTERNAL_SS_ON_HDMI:
1460 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1461 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1462 break;
1463 case ASIC_INTERNAL_SS_ON_LVDS:
1464 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1465 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1466 break;
1467 }
1468 break;
1469 case 8:
1470 switch (id) {
1471 case ASIC_INTERNAL_SS_ON_TMDS:
1472 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1473 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1474 break;
1475 case ASIC_INTERNAL_SS_ON_HDMI:
1476 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1477 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1478 break;
1479 case ASIC_INTERNAL_SS_ON_LVDS:
1480 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1481 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1482 break;
1483 }
1484 break;
1485 default:
1486 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1487 break;
1488 }
1489 if (percentage)
1490 ss->percentage = percentage;
1491 if (rate)
1492 ss->rate = rate;
1493 }
1494 }
1495
1496 union asic_ss_info {
1497 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1498 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1499 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1500 };
1501
1502 union asic_ss_assignment {
1503 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1504 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1505 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1506 };
1507
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1508 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1509 struct radeon_atom_ss *ss,
1510 int id, u32 clock)
1511 {
1512 struct radeon_mode_info *mode_info = &rdev->mode_info;
1513 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1514 uint16_t data_offset, size;
1515 union asic_ss_info *ss_info;
1516 union asic_ss_assignment *ss_assign;
1517 uint8_t frev, crev;
1518 int i, num_indices;
1519
1520 if (id == ASIC_INTERNAL_MEMORY_SS) {
1521 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1522 return false;
1523 }
1524 if (id == ASIC_INTERNAL_ENGINE_SS) {
1525 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1526 return false;
1527 }
1528
1529 memset(ss, 0, sizeof(struct radeon_atom_ss));
1530 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1531 &frev, &crev, &data_offset)) {
1532
1533 ss_info =
1534 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1535
1536 switch (frev) {
1537 case 1:
1538 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1539 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1540
1541 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1542 for (i = 0; i < num_indices; i++) {
1543 if ((ss_assign->v1.ucClockIndication == id) &&
1544 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1545 ss->percentage =
1546 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1547 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1548 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1549 ss->percentage_divider = 100;
1550 return true;
1551 }
1552 ss_assign = (union asic_ss_assignment *)
1553 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1554 }
1555 break;
1556 case 2:
1557 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1558 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1559 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1560 for (i = 0; i < num_indices; i++) {
1561 if ((ss_assign->v2.ucClockIndication == id) &&
1562 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1563 ss->percentage =
1564 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1565 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1566 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1567 ss->percentage_divider = 100;
1568 if ((crev == 2) &&
1569 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1570 (id == ASIC_INTERNAL_MEMORY_SS)))
1571 ss->rate /= 100;
1572 return true;
1573 }
1574 ss_assign = (union asic_ss_assignment *)
1575 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1576 }
1577 break;
1578 case 3:
1579 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1580 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1581 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1582 for (i = 0; i < num_indices; i++) {
1583 if ((ss_assign->v3.ucClockIndication == id) &&
1584 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1585 ss->percentage =
1586 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1587 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1588 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1589 if (ss_assign->v3.ucSpreadSpectrumMode &
1590 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1591 ss->percentage_divider = 1000;
1592 else
1593 ss->percentage_divider = 100;
1594 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1595 (id == ASIC_INTERNAL_MEMORY_SS))
1596 ss->rate /= 100;
1597 if (rdev->flags & RADEON_IS_IGP)
1598 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1599 return true;
1600 }
1601 ss_assign = (union asic_ss_assignment *)
1602 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1603 }
1604 break;
1605 default:
1606 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1607 break;
1608 }
1609
1610 }
1611 return false;
1612 }
1613
1614 union lvds_info {
1615 struct _ATOM_LVDS_INFO info;
1616 struct _ATOM_LVDS_INFO_V12 info_12;
1617 };
1618
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1619 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1620 radeon_encoder
1621 *encoder)
1622 {
1623 struct drm_device *dev = encoder->base.dev;
1624 struct radeon_device *rdev = dev->dev_private;
1625 struct radeon_mode_info *mode_info = &rdev->mode_info;
1626 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1627 uint16_t data_offset, misc;
1628 union lvds_info *lvds_info;
1629 uint8_t frev, crev;
1630 struct radeon_encoder_atom_dig *lvds = NULL;
1631 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1632
1633 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1634 &frev, &crev, &data_offset)) {
1635 lvds_info =
1636 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1637 lvds =
1638 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1639
1640 if (!lvds)
1641 return NULL;
1642
1643 lvds->native_mode.clock =
1644 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1645 lvds->native_mode.hdisplay =
1646 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1647 lvds->native_mode.vdisplay =
1648 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1649 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1650 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1651 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1652 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1653 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1654 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1655 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1656 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1657 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1658 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1659 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1660 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1661 lvds->panel_pwr_delay =
1662 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1663 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1664
1665 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1666 if (misc & ATOM_VSYNC_POLARITY)
1667 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1668 if (misc & ATOM_HSYNC_POLARITY)
1669 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1670 if (misc & ATOM_COMPOSITESYNC)
1671 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1672 if (misc & ATOM_INTERLACE)
1673 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1674 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1675 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1676
1677 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1678 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1679
1680 /* set crtc values */
1681 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1682
1683 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1684
1685 encoder->native_mode = lvds->native_mode;
1686
1687 if (encoder_enum == 2)
1688 lvds->linkb = true;
1689 else
1690 lvds->linkb = false;
1691
1692 /* parse the lcd record table */
1693 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1694 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1695 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1696 bool bad_record = false;
1697 u8 *record;
1698
1699 if ((frev == 1) && (crev < 2))
1700 /* absolute */
1701 record = (u8 *)(mode_info->atom_context->bios +
1702 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1703 else
1704 /* relative */
1705 record = (u8 *)(mode_info->atom_context->bios +
1706 data_offset +
1707 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1708 while (*record != ATOM_RECORD_END_TYPE) {
1709 switch (*record) {
1710 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1711 record += sizeof(ATOM_PATCH_RECORD_MODE);
1712 break;
1713 case LCD_RTS_RECORD_TYPE:
1714 record += sizeof(ATOM_LCD_RTS_RECORD);
1715 break;
1716 case LCD_CAP_RECORD_TYPE:
1717 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1718 break;
1719 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1720 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1721 if (fake_edid_record->ucFakeEDIDLength) {
1722 struct edid *edid;
1723 int edid_size;
1724
1725 if (fake_edid_record->ucFakeEDIDLength == 128)
1726 edid_size = fake_edid_record->ucFakeEDIDLength;
1727 else
1728 edid_size = fake_edid_record->ucFakeEDIDLength * 128;
1729 edid = kmemdup(&fake_edid_record->ucFakeEDIDString[0],
1730 edid_size, GFP_KERNEL);
1731 if (edid) {
1732 if (drm_edid_is_valid(edid)) {
1733 rdev->mode_info.bios_hardcoded_edid = edid;
1734 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1735 } else {
1736 kfree(edid);
1737 }
1738 }
1739 record += struct_size(fake_edid_record,
1740 ucFakeEDIDString,
1741 edid_size);
1742 } else {
1743 /* empty fake edid record must be 3 bytes long */
1744 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1745 }
1746 break;
1747 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1748 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1749 lvds->native_mode.width_mm = panel_res_record->usHSize;
1750 lvds->native_mode.height_mm = panel_res_record->usVSize;
1751 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1752 break;
1753 default:
1754 DRM_ERROR("Bad LCD record %d\n", *record);
1755 bad_record = true;
1756 break;
1757 }
1758 if (bad_record)
1759 break;
1760 }
1761 }
1762 }
1763 return lvds;
1764 }
1765
1766 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1767 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1768 {
1769 struct drm_device *dev = encoder->base.dev;
1770 struct radeon_device *rdev = dev->dev_private;
1771 struct radeon_mode_info *mode_info = &rdev->mode_info;
1772 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1773 uint16_t data_offset;
1774 struct _COMPASSIONATE_DATA *dac_info;
1775 uint8_t frev, crev;
1776 uint8_t bg, dac;
1777 struct radeon_encoder_primary_dac *p_dac = NULL;
1778
1779 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1780 &frev, &crev, &data_offset)) {
1781 dac_info = (struct _COMPASSIONATE_DATA *)
1782 (mode_info->atom_context->bios + data_offset);
1783
1784 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1785
1786 if (!p_dac)
1787 return NULL;
1788
1789 bg = dac_info->ucDAC1_BG_Adjustment;
1790 dac = dac_info->ucDAC1_DAC_Adjustment;
1791 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1792
1793 }
1794 return p_dac;
1795 }
1796
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1797 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1798 struct drm_display_mode *mode)
1799 {
1800 struct radeon_mode_info *mode_info = &rdev->mode_info;
1801 ATOM_ANALOG_TV_INFO *tv_info;
1802 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1803 ATOM_DTD_FORMAT *dtd_timings;
1804 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1805 u8 frev, crev;
1806 u16 data_offset, misc;
1807
1808 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1809 &frev, &crev, &data_offset))
1810 return false;
1811
1812 switch (crev) {
1813 case 1:
1814 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1815 if (index >= MAX_SUPPORTED_TV_TIMING)
1816 return false;
1817
1818 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1819 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1820 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1821 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1822 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1823
1824 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1825 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1826 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1827 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1828 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1829
1830 mode->flags = 0;
1831 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1832 if (misc & ATOM_VSYNC_POLARITY)
1833 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1834 if (misc & ATOM_HSYNC_POLARITY)
1835 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1836 if (misc & ATOM_COMPOSITESYNC)
1837 mode->flags |= DRM_MODE_FLAG_CSYNC;
1838 if (misc & ATOM_INTERLACE)
1839 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1840 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1841 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1842
1843 mode->crtc_clock = mode->clock =
1844 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1845
1846 if (index == 1) {
1847 /* PAL timings appear to have wrong values for totals */
1848 mode->crtc_htotal -= 1;
1849 mode->crtc_vtotal -= 1;
1850 }
1851 break;
1852 case 2:
1853 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1854 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1855 return false;
1856
1857 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1858 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1859 le16_to_cpu(dtd_timings->usHBlanking_Time);
1860 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1861 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1862 le16_to_cpu(dtd_timings->usHSyncOffset);
1863 mode->crtc_hsync_end = mode->crtc_hsync_start +
1864 le16_to_cpu(dtd_timings->usHSyncWidth);
1865
1866 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1867 le16_to_cpu(dtd_timings->usVBlanking_Time);
1868 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1869 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1870 le16_to_cpu(dtd_timings->usVSyncOffset);
1871 mode->crtc_vsync_end = mode->crtc_vsync_start +
1872 le16_to_cpu(dtd_timings->usVSyncWidth);
1873
1874 mode->flags = 0;
1875 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1876 if (misc & ATOM_VSYNC_POLARITY)
1877 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1878 if (misc & ATOM_HSYNC_POLARITY)
1879 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1880 if (misc & ATOM_COMPOSITESYNC)
1881 mode->flags |= DRM_MODE_FLAG_CSYNC;
1882 if (misc & ATOM_INTERLACE)
1883 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1884 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1885 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1886
1887 mode->crtc_clock = mode->clock =
1888 le16_to_cpu(dtd_timings->usPixClk) * 10;
1889 break;
1890 }
1891 return true;
1892 }
1893
1894 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1895 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1896 {
1897 struct radeon_mode_info *mode_info = &rdev->mode_info;
1898 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1899 uint16_t data_offset;
1900 uint8_t frev, crev;
1901 struct _ATOM_ANALOG_TV_INFO *tv_info;
1902 enum radeon_tv_std tv_std = TV_STD_NTSC;
1903
1904 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1905 &frev, &crev, &data_offset)) {
1906
1907 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1908 (mode_info->atom_context->bios + data_offset);
1909
1910 switch (tv_info->ucTV_BootUpDefaultStandard) {
1911 case ATOM_TV_NTSC:
1912 tv_std = TV_STD_NTSC;
1913 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1914 break;
1915 case ATOM_TV_NTSCJ:
1916 tv_std = TV_STD_NTSC_J;
1917 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1918 break;
1919 case ATOM_TV_PAL:
1920 tv_std = TV_STD_PAL;
1921 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1922 break;
1923 case ATOM_TV_PALM:
1924 tv_std = TV_STD_PAL_M;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1926 break;
1927 case ATOM_TV_PALN:
1928 tv_std = TV_STD_PAL_N;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1930 break;
1931 case ATOM_TV_PALCN:
1932 tv_std = TV_STD_PAL_CN;
1933 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1934 break;
1935 case ATOM_TV_PAL60:
1936 tv_std = TV_STD_PAL_60;
1937 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1938 break;
1939 case ATOM_TV_SECAM:
1940 tv_std = TV_STD_SECAM;
1941 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1942 break;
1943 default:
1944 tv_std = TV_STD_NTSC;
1945 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1946 break;
1947 }
1948 }
1949 return tv_std;
1950 }
1951
1952 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1953 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1954 {
1955 struct drm_device *dev = encoder->base.dev;
1956 struct radeon_device *rdev = dev->dev_private;
1957 struct radeon_mode_info *mode_info = &rdev->mode_info;
1958 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1959 uint16_t data_offset;
1960 struct _COMPASSIONATE_DATA *dac_info;
1961 uint8_t frev, crev;
1962 uint8_t bg, dac;
1963 struct radeon_encoder_tv_dac *tv_dac = NULL;
1964
1965 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1966 &frev, &crev, &data_offset)) {
1967
1968 dac_info = (struct _COMPASSIONATE_DATA *)
1969 (mode_info->atom_context->bios + data_offset);
1970
1971 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1972
1973 if (!tv_dac)
1974 return NULL;
1975
1976 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1977 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1978 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1981 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1982 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1983
1984 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1985 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1986 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1987
1988 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1989 }
1990 return tv_dac;
1991 }
1992
1993 static const char *thermal_controller_names[] = {
1994 "NONE",
1995 "lm63",
1996 "adm1032",
1997 "adm1030",
1998 "max6649",
1999 "lm63", /* lm64 */
2000 "f75375",
2001 "asc7xxx",
2002 };
2003
2004 static const char *pp_lib_thermal_controller_names[] = {
2005 "NONE",
2006 "lm63",
2007 "adm1032",
2008 "adm1030",
2009 "max6649",
2010 "lm63", /* lm64 */
2011 "f75375",
2012 "RV6xx",
2013 "RV770",
2014 "adt7473",
2015 "NONE",
2016 "External GPIO",
2017 "Evergreen",
2018 "emc2103",
2019 "Sumo",
2020 "Northern Islands",
2021 "Southern Islands",
2022 "lm96163",
2023 "Sea Islands",
2024 };
2025
2026 union power_info {
2027 struct _ATOM_POWERPLAY_INFO info;
2028 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2029 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2030 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2031 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2032 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2033 };
2034
2035 union pplib_clock_info {
2036 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2037 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2038 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2039 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2040 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2041 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2042 };
2043
2044 union pplib_power_state {
2045 struct _ATOM_PPLIB_STATE v1;
2046 struct _ATOM_PPLIB_STATE_V2 v2;
2047 };
2048
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2049 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2050 int state_index,
2051 u32 misc, u32 misc2)
2052 {
2053 rdev->pm.power_state[state_index].misc = misc;
2054 rdev->pm.power_state[state_index].misc2 = misc2;
2055 /* order matters! */
2056 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2057 rdev->pm.power_state[state_index].type =
2058 POWER_STATE_TYPE_POWERSAVE;
2059 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2060 rdev->pm.power_state[state_index].type =
2061 POWER_STATE_TYPE_BATTERY;
2062 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2063 rdev->pm.power_state[state_index].type =
2064 POWER_STATE_TYPE_BATTERY;
2065 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2066 rdev->pm.power_state[state_index].type =
2067 POWER_STATE_TYPE_BALANCED;
2068 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2069 rdev->pm.power_state[state_index].type =
2070 POWER_STATE_TYPE_PERFORMANCE;
2071 rdev->pm.power_state[state_index].flags &=
2072 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2073 }
2074 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2075 rdev->pm.power_state[state_index].type =
2076 POWER_STATE_TYPE_BALANCED;
2077 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2078 rdev->pm.power_state[state_index].type =
2079 POWER_STATE_TYPE_DEFAULT;
2080 rdev->pm.default_power_state_index = state_index;
2081 rdev->pm.power_state[state_index].default_clock_mode =
2082 &rdev->pm.power_state[state_index].clock_info[0];
2083 } else if (state_index == 0) {
2084 rdev->pm.power_state[state_index].clock_info[0].flags |=
2085 RADEON_PM_MODE_NO_DISPLAY;
2086 }
2087 }
2088
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2089 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2090 {
2091 struct radeon_mode_info *mode_info = &rdev->mode_info;
2092 u32 misc, misc2 = 0;
2093 int num_modes = 0, i;
2094 int state_index = 0;
2095 struct radeon_i2c_bus_rec i2c_bus;
2096 union power_info *power_info;
2097 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2098 u16 data_offset;
2099 u8 frev, crev;
2100
2101 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2102 &frev, &crev, &data_offset))
2103 return state_index;
2104 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2105
2106 /* add the i2c bus for thermal/fan chip */
2107 if ((power_info->info.ucOverdriveThermalController > 0) &&
2108 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2109 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2110 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2111 power_info->info.ucOverdriveControllerAddress >> 1);
2112 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2113 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2114 #ifdef notyet
2115 if (rdev->pm.i2c_bus) {
2116 struct i2c_board_info info = { };
2117 const char *name = thermal_controller_names[power_info->info.
2118 ucOverdriveThermalController];
2119 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2120 strscpy(info.type, name, sizeof(info.type));
2121 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2122 }
2123 #endif
2124 }
2125 num_modes = power_info->info.ucNumOfPowerModeEntries;
2126 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2127 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2128 if (num_modes == 0)
2129 return state_index;
2130 rdev->pm.power_state = kcalloc(num_modes,
2131 sizeof(struct radeon_power_state),
2132 GFP_KERNEL);
2133 if (!rdev->pm.power_state)
2134 return state_index;
2135 /* last mode is usually default, array is low to high */
2136 for (i = 0; i < num_modes; i++) {
2137 /* avoid memory leaks from invalid modes or unknown frev. */
2138 if (!rdev->pm.power_state[state_index].clock_info) {
2139 rdev->pm.power_state[state_index].clock_info =
2140 kzalloc(sizeof(struct radeon_pm_clock_info),
2141 GFP_KERNEL);
2142 }
2143 if (!rdev->pm.power_state[state_index].clock_info)
2144 goto out;
2145 rdev->pm.power_state[state_index].num_clock_modes = 1;
2146 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2147 switch (frev) {
2148 case 1:
2149 rdev->pm.power_state[state_index].clock_info[0].mclk =
2150 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2151 rdev->pm.power_state[state_index].clock_info[0].sclk =
2152 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2153 /* skip invalid modes */
2154 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2155 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2156 continue;
2157 rdev->pm.power_state[state_index].pcie_lanes =
2158 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2159 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2160 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2161 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2163 VOLTAGE_GPIO;
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2165 radeon_atombios_lookup_gpio(rdev,
2166 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2167 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2169 true;
2170 else
2171 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2172 false;
2173 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2174 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2175 VOLTAGE_VDDC;
2176 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2177 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2178 }
2179 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2180 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2181 state_index++;
2182 break;
2183 case 2:
2184 rdev->pm.power_state[state_index].clock_info[0].mclk =
2185 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2186 rdev->pm.power_state[state_index].clock_info[0].sclk =
2187 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2188 /* skip invalid modes */
2189 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2190 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2191 continue;
2192 rdev->pm.power_state[state_index].pcie_lanes =
2193 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2194 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2195 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2196 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2197 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2198 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2199 VOLTAGE_GPIO;
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2201 radeon_atombios_lookup_gpio(rdev,
2202 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2203 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2205 true;
2206 else
2207 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2208 false;
2209 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2210 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2211 VOLTAGE_VDDC;
2212 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2213 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2214 }
2215 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2216 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2217 state_index++;
2218 break;
2219 case 3:
2220 rdev->pm.power_state[state_index].clock_info[0].mclk =
2221 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2222 rdev->pm.power_state[state_index].clock_info[0].sclk =
2223 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2224 /* skip invalid modes */
2225 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2226 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2227 continue;
2228 rdev->pm.power_state[state_index].pcie_lanes =
2229 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2230 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2231 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2232 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2233 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2234 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2235 VOLTAGE_GPIO;
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2237 radeon_atombios_lookup_gpio(rdev,
2238 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2239 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2241 true;
2242 else
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2244 false;
2245 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2246 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2247 VOLTAGE_VDDC;
2248 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2249 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2250 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2251 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2252 true;
2253 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2254 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2255 }
2256 }
2257 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2258 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2259 state_index++;
2260 break;
2261 }
2262 }
2263 out:
2264 /* free any unused clock_info allocation. */
2265 if (state_index && state_index < num_modes) {
2266 kfree(rdev->pm.power_state[state_index].clock_info);
2267 rdev->pm.power_state[state_index].clock_info = NULL;
2268 }
2269
2270 /* last mode is usually default */
2271 if (state_index && rdev->pm.default_power_state_index == -1) {
2272 rdev->pm.power_state[state_index - 1].type =
2273 POWER_STATE_TYPE_DEFAULT;
2274 rdev->pm.default_power_state_index = state_index - 1;
2275 rdev->pm.power_state[state_index - 1].default_clock_mode =
2276 &rdev->pm.power_state[state_index - 1].clock_info[0];
2277 rdev->pm.power_state[state_index - 1].flags &=
2278 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2279 rdev->pm.power_state[state_index - 1].misc = 0;
2280 rdev->pm.power_state[state_index - 1].misc2 = 0;
2281 }
2282 return state_index;
2283 }
2284
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2285 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2286 ATOM_PPLIB_THERMALCONTROLLER *controller)
2287 {
2288 struct radeon_i2c_bus_rec i2c_bus;
2289
2290 /* add the i2c bus for thermal/fan chip */
2291 if (controller->ucType > 0) {
2292 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2293 rdev->pm.no_fan = true;
2294 rdev->pm.fan_pulses_per_revolution =
2295 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2296 if (rdev->pm.fan_pulses_per_revolution) {
2297 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2298 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2299 }
2300 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2301 DRM_INFO("Internal thermal controller %s fan control\n",
2302 (controller->ucFanParameters &
2303 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2304 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2305 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2306 DRM_INFO("Internal thermal controller %s fan control\n",
2307 (controller->ucFanParameters &
2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2309 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2310 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2311 DRM_INFO("Internal thermal controller %s fan control\n",
2312 (controller->ucFanParameters &
2313 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2314 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2315 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2316 DRM_INFO("Internal thermal controller %s fan control\n",
2317 (controller->ucFanParameters &
2318 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2319 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2320 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2321 DRM_INFO("Internal thermal controller %s fan control\n",
2322 (controller->ucFanParameters &
2323 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2324 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2325 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2326 DRM_INFO("Internal thermal controller %s fan control\n",
2327 (controller->ucFanParameters &
2328 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2329 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2330 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2331 DRM_INFO("Internal thermal controller %s fan control\n",
2332 (controller->ucFanParameters &
2333 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2334 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2335 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2336 DRM_INFO("Internal thermal controller %s fan control\n",
2337 (controller->ucFanParameters &
2338 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2339 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2340 } else if (controller->ucType ==
2341 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2342 DRM_INFO("External GPIO thermal controller %s fan control\n",
2343 (controller->ucFanParameters &
2344 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2345 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2346 } else if (controller->ucType ==
2347 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2348 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2349 (controller->ucFanParameters &
2350 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2351 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2352 } else if (controller->ucType ==
2353 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2354 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2355 (controller->ucFanParameters &
2356 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2357 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2358 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2359 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2360 pp_lib_thermal_controller_names[controller->ucType],
2361 controller->ucI2cAddress >> 1,
2362 (controller->ucFanParameters &
2363 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2364 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2365 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2366 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2367 #ifdef notyet
2368 if (rdev->pm.i2c_bus) {
2369 struct i2c_board_info info = { };
2370 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2371 info.addr = controller->ucI2cAddress >> 1;
2372 strscpy(info.type, name, sizeof(info.type));
2373 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2374 }
2375 #endif
2376 } else {
2377 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2378 controller->ucType,
2379 controller->ucI2cAddress >> 1,
2380 (controller->ucFanParameters &
2381 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2382 }
2383 }
2384 }
2385
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2386 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2387 u16 *vddc, u16 *vddci, u16 *mvdd)
2388 {
2389 struct radeon_mode_info *mode_info = &rdev->mode_info;
2390 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2391 u8 frev, crev;
2392 u16 data_offset;
2393 union firmware_info *firmware_info;
2394
2395 *vddc = 0;
2396 *vddci = 0;
2397 *mvdd = 0;
2398
2399 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2400 &frev, &crev, &data_offset)) {
2401 firmware_info =
2402 (union firmware_info *)(mode_info->atom_context->bios +
2403 data_offset);
2404 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2405 if ((frev == 2) && (crev >= 2)) {
2406 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2407 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2408 }
2409 }
2410 }
2411
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2412 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2413 int state_index, int mode_index,
2414 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2415 {
2416 int j;
2417 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2418 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2419 u16 vddc, vddci, mvdd;
2420
2421 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2422
2423 rdev->pm.power_state[state_index].misc = misc;
2424 rdev->pm.power_state[state_index].misc2 = misc2;
2425 rdev->pm.power_state[state_index].pcie_lanes =
2426 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2427 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2428 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2429 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2430 rdev->pm.power_state[state_index].type =
2431 POWER_STATE_TYPE_BATTERY;
2432 break;
2433 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2434 rdev->pm.power_state[state_index].type =
2435 POWER_STATE_TYPE_BALANCED;
2436 break;
2437 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2438 rdev->pm.power_state[state_index].type =
2439 POWER_STATE_TYPE_PERFORMANCE;
2440 break;
2441 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2442 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2443 rdev->pm.power_state[state_index].type =
2444 POWER_STATE_TYPE_PERFORMANCE;
2445 break;
2446 }
2447 rdev->pm.power_state[state_index].flags = 0;
2448 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2449 rdev->pm.power_state[state_index].flags |=
2450 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2451 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2452 rdev->pm.power_state[state_index].type =
2453 POWER_STATE_TYPE_DEFAULT;
2454 rdev->pm.default_power_state_index = state_index;
2455 rdev->pm.power_state[state_index].default_clock_mode =
2456 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2457 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2458 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2459 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2460 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2461 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2462 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2463 } else {
2464 u16 max_vddci = 0;
2465
2466 if (ASIC_IS_DCE4(rdev))
2467 radeon_atom_get_max_voltage(rdev,
2468 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2469 &max_vddci);
2470 /* patch the table values with the default sclk/mclk from firmware info */
2471 for (j = 0; j < mode_index; j++) {
2472 rdev->pm.power_state[state_index].clock_info[j].mclk =
2473 rdev->clock.default_mclk;
2474 rdev->pm.power_state[state_index].clock_info[j].sclk =
2475 rdev->clock.default_sclk;
2476 if (vddc)
2477 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2478 vddc;
2479 if (max_vddci)
2480 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2481 max_vddci;
2482 }
2483 }
2484 }
2485 }
2486
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2487 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2488 int state_index, int mode_index,
2489 union pplib_clock_info *clock_info)
2490 {
2491 u32 sclk, mclk;
2492 u16 vddc;
2493
2494 if (rdev->flags & RADEON_IS_IGP) {
2495 if (rdev->family >= CHIP_PALM) {
2496 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2497 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2498 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2499 } else {
2500 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2501 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2502 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2503 }
2504 } else if (rdev->family >= CHIP_BONAIRE) {
2505 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2506 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2507 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2508 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2509 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2511 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2512 VOLTAGE_NONE;
2513 } else if (rdev->family >= CHIP_TAHITI) {
2514 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2515 sclk |= clock_info->si.ucEngineClockHigh << 16;
2516 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2517 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2521 VOLTAGE_SW;
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2523 le16_to_cpu(clock_info->si.usVDDC);
2524 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2525 le16_to_cpu(clock_info->si.usVDDCI);
2526 } else if (rdev->family >= CHIP_CEDAR) {
2527 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2528 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2529 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2530 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2533 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2534 VOLTAGE_SW;
2535 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2536 le16_to_cpu(clock_info->evergreen.usVDDC);
2537 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2538 le16_to_cpu(clock_info->evergreen.usVDDCI);
2539 } else {
2540 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2541 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2542 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2543 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2544 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2545 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2546 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2547 VOLTAGE_SW;
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2549 le16_to_cpu(clock_info->r600.usVDDC);
2550 }
2551
2552 /* patch up vddc if necessary */
2553 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2554 case ATOM_VIRTUAL_VOLTAGE_ID0:
2555 case ATOM_VIRTUAL_VOLTAGE_ID1:
2556 case ATOM_VIRTUAL_VOLTAGE_ID2:
2557 case ATOM_VIRTUAL_VOLTAGE_ID3:
2558 case ATOM_VIRTUAL_VOLTAGE_ID4:
2559 case ATOM_VIRTUAL_VOLTAGE_ID5:
2560 case ATOM_VIRTUAL_VOLTAGE_ID6:
2561 case ATOM_VIRTUAL_VOLTAGE_ID7:
2562 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2563 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2564 &vddc) == 0)
2565 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2566 break;
2567 default:
2568 break;
2569 }
2570
2571 if (rdev->flags & RADEON_IS_IGP) {
2572 /* skip invalid modes */
2573 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2574 return false;
2575 } else {
2576 /* skip invalid modes */
2577 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2578 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2579 return false;
2580 }
2581 return true;
2582 }
2583
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2584 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2585 {
2586 struct radeon_mode_info *mode_info = &rdev->mode_info;
2587 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2588 union pplib_power_state *power_state;
2589 int i, j;
2590 int state_index = 0, mode_index = 0;
2591 union pplib_clock_info *clock_info;
2592 bool valid;
2593 union power_info *power_info;
2594 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2595 u16 data_offset;
2596 u8 frev, crev;
2597
2598 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2599 &frev, &crev, &data_offset))
2600 return state_index;
2601 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2602
2603 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2604 if (power_info->pplib.ucNumStates == 0)
2605 return state_index;
2606 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2607 sizeof(struct radeon_power_state),
2608 GFP_KERNEL);
2609 if (!rdev->pm.power_state)
2610 return state_index;
2611 /* first mode is usually default, followed by low to high */
2612 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2613 mode_index = 0;
2614 power_state = (union pplib_power_state *)
2615 (mode_info->atom_context->bios + data_offset +
2616 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2617 i * power_info->pplib.ucStateEntrySize);
2618 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2619 (mode_info->atom_context->bios + data_offset +
2620 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2621 (power_state->v1.ucNonClockStateIndex *
2622 power_info->pplib.ucNonClockSize));
2623 rdev->pm.power_state[i].clock_info =
2624 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2625 (power_info->pplib.ucStateEntrySize - 1) : 1,
2626 sizeof(struct radeon_pm_clock_info),
2627 GFP_KERNEL);
2628 if (!rdev->pm.power_state[i].clock_info)
2629 return state_index;
2630 if (power_info->pplib.ucStateEntrySize - 1) {
2631 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2632 clock_info = (union pplib_clock_info *)
2633 (mode_info->atom_context->bios + data_offset +
2634 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2635 (power_state->v1.ucClockStateIndices[j] *
2636 power_info->pplib.ucClockInfoSize));
2637 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2638 state_index, mode_index,
2639 clock_info);
2640 if (valid)
2641 mode_index++;
2642 }
2643 } else {
2644 rdev->pm.power_state[state_index].clock_info[0].mclk =
2645 rdev->clock.default_mclk;
2646 rdev->pm.power_state[state_index].clock_info[0].sclk =
2647 rdev->clock.default_sclk;
2648 mode_index++;
2649 }
2650 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2651 if (mode_index) {
2652 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2653 non_clock_info);
2654 state_index++;
2655 }
2656 }
2657 /* if multiple clock modes, mark the lowest as no display */
2658 for (i = 0; i < state_index; i++) {
2659 if (rdev->pm.power_state[i].num_clock_modes > 1)
2660 rdev->pm.power_state[i].clock_info[0].flags |=
2661 RADEON_PM_MODE_NO_DISPLAY;
2662 }
2663 /* first mode is usually default */
2664 if (rdev->pm.default_power_state_index == -1) {
2665 rdev->pm.power_state[0].type =
2666 POWER_STATE_TYPE_DEFAULT;
2667 rdev->pm.default_power_state_index = 0;
2668 rdev->pm.power_state[0].default_clock_mode =
2669 &rdev->pm.power_state[0].clock_info[0];
2670 }
2671 return state_index;
2672 }
2673
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2674 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2675 {
2676 struct radeon_mode_info *mode_info = &rdev->mode_info;
2677 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2678 union pplib_power_state *power_state;
2679 int i, j, non_clock_array_index, clock_array_index;
2680 int state_index = 0, mode_index = 0;
2681 union pplib_clock_info *clock_info;
2682 struct _StateArray *state_array;
2683 struct _ClockInfoArray *clock_info_array;
2684 struct _NonClockInfoArray *non_clock_info_array;
2685 bool valid;
2686 union power_info *power_info;
2687 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2688 u16 data_offset;
2689 u8 frev, crev;
2690 u8 *power_state_offset;
2691
2692 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2693 &frev, &crev, &data_offset))
2694 return state_index;
2695 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2696
2697 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2698 state_array = (struct _StateArray *)
2699 (mode_info->atom_context->bios + data_offset +
2700 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2701 clock_info_array = (struct _ClockInfoArray *)
2702 (mode_info->atom_context->bios + data_offset +
2703 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2704 non_clock_info_array = (struct _NonClockInfoArray *)
2705 (mode_info->atom_context->bios + data_offset +
2706 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2707 if (state_array->ucNumEntries == 0)
2708 return state_index;
2709 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2710 sizeof(struct radeon_power_state),
2711 GFP_KERNEL);
2712 if (!rdev->pm.power_state)
2713 return state_index;
2714 power_state_offset = (u8 *)state_array->states;
2715 for (i = 0; i < state_array->ucNumEntries; i++) {
2716 mode_index = 0;
2717 power_state = (union pplib_power_state *)power_state_offset;
2718 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2719 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2720 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2721 rdev->pm.power_state[i].clock_info =
2722 kcalloc(power_state->v2.ucNumDPMLevels ?
2723 power_state->v2.ucNumDPMLevels : 1,
2724 sizeof(struct radeon_pm_clock_info),
2725 GFP_KERNEL);
2726 if (!rdev->pm.power_state[i].clock_info)
2727 return state_index;
2728 if (power_state->v2.ucNumDPMLevels) {
2729 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2730 clock_array_index = power_state->v2.clockInfoIndex[j];
2731 clock_info = (union pplib_clock_info *)
2732 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2733 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2734 state_index, mode_index,
2735 clock_info);
2736 if (valid)
2737 mode_index++;
2738 }
2739 } else {
2740 rdev->pm.power_state[state_index].clock_info[0].mclk =
2741 rdev->clock.default_mclk;
2742 rdev->pm.power_state[state_index].clock_info[0].sclk =
2743 rdev->clock.default_sclk;
2744 mode_index++;
2745 }
2746 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2747 if (mode_index) {
2748 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2749 non_clock_info);
2750 state_index++;
2751 }
2752 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2753 }
2754 /* if multiple clock modes, mark the lowest as no display */
2755 for (i = 0; i < state_index; i++) {
2756 if (rdev->pm.power_state[i].num_clock_modes > 1)
2757 rdev->pm.power_state[i].clock_info[0].flags |=
2758 RADEON_PM_MODE_NO_DISPLAY;
2759 }
2760 /* first mode is usually default */
2761 if (rdev->pm.default_power_state_index == -1) {
2762 rdev->pm.power_state[0].type =
2763 POWER_STATE_TYPE_DEFAULT;
2764 rdev->pm.default_power_state_index = 0;
2765 rdev->pm.power_state[0].default_clock_mode =
2766 &rdev->pm.power_state[0].clock_info[0];
2767 }
2768 return state_index;
2769 }
2770
radeon_atombios_get_power_modes(struct radeon_device * rdev)2771 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2772 {
2773 struct radeon_mode_info *mode_info = &rdev->mode_info;
2774 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2775 u16 data_offset;
2776 u8 frev, crev;
2777 int state_index = 0;
2778
2779 rdev->pm.default_power_state_index = -1;
2780
2781 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2782 &frev, &crev, &data_offset)) {
2783 switch (frev) {
2784 case 1:
2785 case 2:
2786 case 3:
2787 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2788 break;
2789 case 4:
2790 case 5:
2791 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2792 break;
2793 case 6:
2794 state_index = radeon_atombios_parse_power_table_6(rdev);
2795 break;
2796 default:
2797 break;
2798 }
2799 }
2800
2801 if (state_index == 0) {
2802 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2803 if (rdev->pm.power_state) {
2804 rdev->pm.power_state[0].clock_info =
2805 kcalloc(1,
2806 sizeof(struct radeon_pm_clock_info),
2807 GFP_KERNEL);
2808 if (rdev->pm.power_state[0].clock_info) {
2809 /* add the default mode */
2810 rdev->pm.power_state[state_index].type =
2811 POWER_STATE_TYPE_DEFAULT;
2812 rdev->pm.power_state[state_index].num_clock_modes = 1;
2813 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2814 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2815 rdev->pm.power_state[state_index].default_clock_mode =
2816 &rdev->pm.power_state[state_index].clock_info[0];
2817 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2818 rdev->pm.power_state[state_index].pcie_lanes = 16;
2819 rdev->pm.default_power_state_index = state_index;
2820 rdev->pm.power_state[state_index].flags = 0;
2821 state_index++;
2822 }
2823 }
2824 }
2825
2826 rdev->pm.num_power_states = state_index;
2827
2828 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2829 rdev->pm.current_clock_mode_index = 0;
2830 if (rdev->pm.default_power_state_index >= 0)
2831 rdev->pm.current_vddc =
2832 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2833 else
2834 rdev->pm.current_vddc = 0;
2835 }
2836
2837 union get_clock_dividers {
2838 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2839 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2840 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2841 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2842 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2843 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2844 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2845 };
2846
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2847 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2848 u8 clock_type,
2849 u32 clock,
2850 bool strobe_mode,
2851 struct atom_clock_dividers *dividers)
2852 {
2853 union get_clock_dividers args;
2854 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2855 u8 frev, crev;
2856
2857 memset(&args, 0, sizeof(args));
2858 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2859
2860 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2861 return -EINVAL;
2862
2863 switch (crev) {
2864 case 1:
2865 /* r4xx, r5xx */
2866 args.v1.ucAction = clock_type;
2867 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2868
2869 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2870
2871 dividers->post_div = args.v1.ucPostDiv;
2872 dividers->fb_div = args.v1.ucFbDiv;
2873 dividers->enable_post_div = true;
2874 break;
2875 case 2:
2876 case 3:
2877 case 5:
2878 /* r6xx, r7xx, evergreen, ni, si */
2879 if (rdev->family <= CHIP_RV770) {
2880 args.v2.ucAction = clock_type;
2881 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2882
2883 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2884
2885 dividers->post_div = args.v2.ucPostDiv;
2886 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2887 dividers->ref_div = args.v2.ucAction;
2888 if (rdev->family == CHIP_RV770) {
2889 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2890 true : false;
2891 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2892 } else
2893 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2894 } else {
2895 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2896 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2897
2898 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2899
2900 dividers->post_div = args.v3.ucPostDiv;
2901 dividers->enable_post_div = (args.v3.ucCntlFlag &
2902 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2903 dividers->enable_dithen = (args.v3.ucCntlFlag &
2904 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2905 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2906 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2907 dividers->ref_div = args.v3.ucRefDiv;
2908 dividers->vco_mode = (args.v3.ucCntlFlag &
2909 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2910 } else {
2911 /* for SI we use ComputeMemoryClockParam for memory plls */
2912 if (rdev->family >= CHIP_TAHITI)
2913 return -EINVAL;
2914 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2915 if (strobe_mode)
2916 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2917
2918 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2919
2920 dividers->post_div = args.v5.ucPostDiv;
2921 dividers->enable_post_div = (args.v5.ucCntlFlag &
2922 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2923 dividers->enable_dithen = (args.v5.ucCntlFlag &
2924 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2925 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2926 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2927 dividers->ref_div = args.v5.ucRefDiv;
2928 dividers->vco_mode = (args.v5.ucCntlFlag &
2929 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2930 }
2931 }
2932 break;
2933 case 4:
2934 /* fusion */
2935 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2936
2937 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2938
2939 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2940 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2941 break;
2942 case 6:
2943 /* CI */
2944 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2945 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2946 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2947
2948 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2949
2950 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2951 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2952 dividers->ref_div = args.v6_out.ucPllRefDiv;
2953 dividers->post_div = args.v6_out.ucPllPostDiv;
2954 dividers->flags = args.v6_out.ucPllCntlFlag;
2955 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2956 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2957 break;
2958 default:
2959 return -EINVAL;
2960 }
2961 return 0;
2962 }
2963
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2964 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2965 u32 clock,
2966 bool strobe_mode,
2967 struct atom_mpll_param *mpll_param)
2968 {
2969 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2970 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2971 u8 frev, crev;
2972
2973 memset(&args, 0, sizeof(args));
2974 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2975
2976 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2977 return -EINVAL;
2978
2979 switch (frev) {
2980 case 2:
2981 switch (crev) {
2982 case 1:
2983 /* SI */
2984 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2985 args.ucInputFlag = 0;
2986 if (strobe_mode)
2987 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2988
2989 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2990
2991 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2992 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2993 mpll_param->post_div = args.ucPostDiv;
2994 mpll_param->dll_speed = args.ucDllSpeed;
2995 mpll_param->bwcntl = args.ucBWCntl;
2996 mpll_param->vco_mode =
2997 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2998 mpll_param->yclk_sel =
2999 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
3000 mpll_param->qdr =
3001 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
3002 mpll_param->half_rate =
3003 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
3004 break;
3005 default:
3006 return -EINVAL;
3007 }
3008 break;
3009 default:
3010 return -EINVAL;
3011 }
3012 return 0;
3013 }
3014
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)3015 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3016 {
3017 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3018 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3019
3020 args.ucEnable = enable;
3021
3022 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3023 }
3024
radeon_atom_get_engine_clock(struct radeon_device * rdev)3025 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3026 {
3027 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3028 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3029
3030 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3031 return le32_to_cpu(args.ulReturnEngineClock);
3032 }
3033
radeon_atom_get_memory_clock(struct radeon_device * rdev)3034 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3035 {
3036 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3037 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3038
3039 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3040 return le32_to_cpu(args.ulReturnMemoryClock);
3041 }
3042
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3043 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3044 uint32_t eng_clock)
3045 {
3046 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3047 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3048
3049 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3050
3051 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3052 }
3053
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3054 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3055 uint32_t mem_clock)
3056 {
3057 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3058 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3059
3060 if (rdev->flags & RADEON_IS_IGP)
3061 return;
3062
3063 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3064
3065 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3066 }
3067
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3068 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3069 u32 eng_clock, u32 mem_clock)
3070 {
3071 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3072 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3073 u32 tmp;
3074
3075 memset(&args, 0, sizeof(args));
3076
3077 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3078 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3079
3080 args.ulTargetEngineClock = cpu_to_le32(tmp);
3081 if (mem_clock)
3082 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3083
3084 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3085 }
3086
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3087 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3088 u32 mem_clock)
3089 {
3090 u32 args;
3091 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3092
3093 args = cpu_to_le32(mem_clock); /* 10 khz */
3094
3095 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3096 }
3097
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3098 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3099 u32 mem_clock)
3100 {
3101 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3102 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3103 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3104
3105 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3106
3107 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3108 }
3109
3110 union set_voltage {
3111 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3112 struct _SET_VOLTAGE_PARAMETERS v1;
3113 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3114 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3115 };
3116
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3117 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3118 {
3119 union set_voltage args;
3120 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3121 u8 frev, crev, volt_index = voltage_level;
3122
3123 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3124 return;
3125
3126 /* 0xff01 is a flag rather then an actual voltage */
3127 if (voltage_level == 0xff01)
3128 return;
3129
3130 switch (crev) {
3131 case 1:
3132 args.v1.ucVoltageType = voltage_type;
3133 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3134 args.v1.ucVoltageIndex = volt_index;
3135 break;
3136 case 2:
3137 args.v2.ucVoltageType = voltage_type;
3138 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3139 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3140 break;
3141 case 3:
3142 args.v3.ucVoltageType = voltage_type;
3143 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3144 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3145 break;
3146 default:
3147 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3148 return;
3149 }
3150
3151 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3152 }
3153
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3154 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3155 u16 voltage_id, u16 *voltage)
3156 {
3157 union set_voltage args;
3158 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3159 u8 frev, crev;
3160
3161 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3162 return -EINVAL;
3163
3164 switch (crev) {
3165 case 1:
3166 return -EINVAL;
3167 case 2:
3168 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3169 args.v2.ucVoltageMode = 0;
3170 args.v2.usVoltageLevel = 0;
3171
3172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3173
3174 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3175 break;
3176 case 3:
3177 args.v3.ucVoltageType = voltage_type;
3178 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3179 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3180
3181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3182
3183 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3184 break;
3185 default:
3186 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3187 return -EINVAL;
3188 }
3189
3190 return 0;
3191 }
3192
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3193 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3194 u16 *voltage,
3195 u16 leakage_idx)
3196 {
3197 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3198 }
3199
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3200 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3201 u16 *leakage_id)
3202 {
3203 union set_voltage args;
3204 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3205 u8 frev, crev;
3206
3207 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3208 return -EINVAL;
3209
3210 switch (crev) {
3211 case 3:
3212 case 4:
3213 args.v3.ucVoltageType = 0;
3214 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3215 args.v3.usVoltageLevel = 0;
3216
3217 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3218
3219 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3220 break;
3221 default:
3222 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3223 return -EINVAL;
3224 }
3225
3226 return 0;
3227 }
3228
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3229 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3230 u16 *vddc, u16 *vddci,
3231 u16 virtual_voltage_id,
3232 u16 vbios_voltage_id)
3233 {
3234 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3235 u8 frev, crev;
3236 u16 data_offset, size;
3237 int i, j;
3238 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3239 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3240
3241 *vddc = 0;
3242 *vddci = 0;
3243
3244 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3245 &frev, &crev, &data_offset))
3246 return -EINVAL;
3247
3248 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3249 (rdev->mode_info.atom_context->bios + data_offset);
3250
3251 switch (frev) {
3252 case 1:
3253 return -EINVAL;
3254 case 2:
3255 switch (crev) {
3256 case 1:
3257 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3258 return -EINVAL;
3259 leakage_bin = (u16 *)
3260 (rdev->mode_info.atom_context->bios + data_offset +
3261 le16_to_cpu(profile->usLeakageBinArrayOffset));
3262 vddc_id_buf = (u16 *)
3263 (rdev->mode_info.atom_context->bios + data_offset +
3264 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3265 vddc_buf = (u16 *)
3266 (rdev->mode_info.atom_context->bios + data_offset +
3267 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3268 vddci_id_buf = (u16 *)
3269 (rdev->mode_info.atom_context->bios + data_offset +
3270 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3271 vddci_buf = (u16 *)
3272 (rdev->mode_info.atom_context->bios + data_offset +
3273 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3274
3275 if (profile->ucElbVDDC_Num > 0) {
3276 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3277 if (vddc_id_buf[i] == virtual_voltage_id) {
3278 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3279 if (vbios_voltage_id <= leakage_bin[j]) {
3280 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3281 break;
3282 }
3283 }
3284 break;
3285 }
3286 }
3287 }
3288 if (profile->ucElbVDDCI_Num > 0) {
3289 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3290 if (vddci_id_buf[i] == virtual_voltage_id) {
3291 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3292 if (vbios_voltage_id <= leakage_bin[j]) {
3293 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3294 break;
3295 }
3296 }
3297 break;
3298 }
3299 }
3300 }
3301 break;
3302 default:
3303 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3304 return -EINVAL;
3305 }
3306 break;
3307 default:
3308 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3309 return -EINVAL;
3310 }
3311
3312 return 0;
3313 }
3314
3315 union get_voltage_info {
3316 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3317 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3318 };
3319
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3320 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3321 u16 virtual_voltage_id,
3322 u16 *voltage)
3323 {
3324 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3325 u32 entry_id;
3326 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3327 union get_voltage_info args;
3328
3329 for (entry_id = 0; entry_id < count; entry_id++) {
3330 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3331 virtual_voltage_id)
3332 break;
3333 }
3334
3335 if (entry_id >= count)
3336 return -EINVAL;
3337
3338 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3339 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3340 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3341 args.in.ulSCLKFreq =
3342 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3343
3344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3345
3346 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3347
3348 return 0;
3349 }
3350
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3351 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3352 u16 voltage_level, u8 voltage_type,
3353 u32 *gpio_value, u32 *gpio_mask)
3354 {
3355 union set_voltage args;
3356 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3357 u8 frev, crev;
3358
3359 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3360 return -EINVAL;
3361
3362 switch (crev) {
3363 case 1:
3364 return -EINVAL;
3365 case 2:
3366 args.v2.ucVoltageType = voltage_type;
3367 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3368 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3369
3370 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3371
3372 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3373
3374 args.v2.ucVoltageType = voltage_type;
3375 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3376 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3377
3378 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3379
3380 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3381 break;
3382 default:
3383 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3384 return -EINVAL;
3385 }
3386
3387 return 0;
3388 }
3389
3390 union voltage_object_info {
3391 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3392 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3393 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3394 };
3395
3396 union voltage_object {
3397 struct _ATOM_VOLTAGE_OBJECT v1;
3398 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3399 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3400 };
3401
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3402 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3403 u8 voltage_type)
3404 {
3405 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3406 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3407 u8 *start = (u8 *)v1;
3408
3409 while (offset < size) {
3410 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3411 if (vo->ucVoltageType == voltage_type)
3412 return vo;
3413 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3414 vo->asFormula.ucNumOfVoltageEntries;
3415 }
3416 return NULL;
3417 }
3418
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3419 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3420 u8 voltage_type)
3421 {
3422 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3423 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3424 u8 *start = (u8 *)v2;
3425
3426 while (offset < size) {
3427 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3428 if (vo->ucVoltageType == voltage_type)
3429 return vo;
3430 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3431 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3432 }
3433 return NULL;
3434 }
3435
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3436 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3437 u8 voltage_type, u8 voltage_mode)
3438 {
3439 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3440 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3441 u8 *start = (u8 *)v3;
3442
3443 while (offset < size) {
3444 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3445 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3446 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3447 return vo;
3448 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3449 }
3450 return NULL;
3451 }
3452
3453 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3454 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3455 u8 voltage_type, u8 voltage_mode)
3456 {
3457 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3458 u8 frev, crev;
3459 u16 data_offset, size;
3460 union voltage_object_info *voltage_info;
3461 union voltage_object *voltage_object = NULL;
3462
3463 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3464 &frev, &crev, &data_offset)) {
3465 voltage_info = (union voltage_object_info *)
3466 (rdev->mode_info.atom_context->bios + data_offset);
3467
3468 switch (frev) {
3469 case 1:
3470 case 2:
3471 switch (crev) {
3472 case 1:
3473 voltage_object = (union voltage_object *)
3474 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3475 if (voltage_object &&
3476 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3477 return true;
3478 break;
3479 case 2:
3480 voltage_object = (union voltage_object *)
3481 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3482 if (voltage_object &&
3483 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3484 return true;
3485 break;
3486 default:
3487 DRM_ERROR("unknown voltage object table\n");
3488 return false;
3489 }
3490 break;
3491 case 3:
3492 switch (crev) {
3493 case 1:
3494 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3495 voltage_type, voltage_mode))
3496 return true;
3497 break;
3498 default:
3499 DRM_ERROR("unknown voltage object table\n");
3500 return false;
3501 }
3502 break;
3503 default:
3504 DRM_ERROR("unknown voltage object table\n");
3505 return false;
3506 }
3507
3508 }
3509 return false;
3510 }
3511
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3512 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3513 u8 voltage_type,
3514 u8 *svd_gpio_id, u8 *svc_gpio_id)
3515 {
3516 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3517 u8 frev, crev;
3518 u16 data_offset, size;
3519 union voltage_object_info *voltage_info;
3520 union voltage_object *voltage_object = NULL;
3521
3522 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3523 &frev, &crev, &data_offset)) {
3524 voltage_info = (union voltage_object_info *)
3525 (rdev->mode_info.atom_context->bios + data_offset);
3526
3527 switch (frev) {
3528 case 3:
3529 switch (crev) {
3530 case 1:
3531 voltage_object = (union voltage_object *)
3532 atom_lookup_voltage_object_v3(&voltage_info->v3,
3533 voltage_type,
3534 VOLTAGE_OBJ_SVID2);
3535 if (voltage_object) {
3536 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3537 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3538 } else {
3539 return -EINVAL;
3540 }
3541 break;
3542 default:
3543 DRM_ERROR("unknown voltage object table\n");
3544 return -EINVAL;
3545 }
3546 break;
3547 default:
3548 DRM_ERROR("unknown voltage object table\n");
3549 return -EINVAL;
3550 }
3551
3552 }
3553 return 0;
3554 }
3555
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3556 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3557 u8 voltage_type, u16 *max_voltage)
3558 {
3559 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3560 u8 frev, crev;
3561 u16 data_offset, size;
3562 union voltage_object_info *voltage_info;
3563 union voltage_object *voltage_object = NULL;
3564
3565 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3566 &frev, &crev, &data_offset)) {
3567 voltage_info = (union voltage_object_info *)
3568 (rdev->mode_info.atom_context->bios + data_offset);
3569
3570 switch (crev) {
3571 case 1:
3572 voltage_object = (union voltage_object *)
3573 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3574 if (voltage_object) {
3575 ATOM_VOLTAGE_FORMULA *formula =
3576 &voltage_object->v1.asFormula;
3577 if (formula->ucFlag & 1)
3578 *max_voltage =
3579 le16_to_cpu(formula->usVoltageBaseLevel) +
3580 formula->ucNumOfVoltageEntries / 2 *
3581 le16_to_cpu(formula->usVoltageStep);
3582 else
3583 *max_voltage =
3584 le16_to_cpu(formula->usVoltageBaseLevel) +
3585 (formula->ucNumOfVoltageEntries - 1) *
3586 le16_to_cpu(formula->usVoltageStep);
3587 return 0;
3588 }
3589 break;
3590 case 2:
3591 voltage_object = (union voltage_object *)
3592 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3593 if (voltage_object) {
3594 ATOM_VOLTAGE_FORMULA_V2 *formula =
3595 &voltage_object->v2.asFormula;
3596 if (formula->ucNumOfVoltageEntries) {
3597 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3598 ((u8 *)&formula->asVIDAdjustEntries[0] +
3599 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3600 *max_voltage =
3601 le16_to_cpu(lut->usVoltageValue);
3602 return 0;
3603 }
3604 }
3605 break;
3606 default:
3607 DRM_ERROR("unknown voltage object table\n");
3608 return -EINVAL;
3609 }
3610
3611 }
3612 return -EINVAL;
3613 }
3614
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3615 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3616 u8 voltage_type, u16 *min_voltage)
3617 {
3618 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3619 u8 frev, crev;
3620 u16 data_offset, size;
3621 union voltage_object_info *voltage_info;
3622 union voltage_object *voltage_object = NULL;
3623
3624 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3625 &frev, &crev, &data_offset)) {
3626 voltage_info = (union voltage_object_info *)
3627 (rdev->mode_info.atom_context->bios + data_offset);
3628
3629 switch (crev) {
3630 case 1:
3631 voltage_object = (union voltage_object *)
3632 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3633 if (voltage_object) {
3634 ATOM_VOLTAGE_FORMULA *formula =
3635 &voltage_object->v1.asFormula;
3636 *min_voltage =
3637 le16_to_cpu(formula->usVoltageBaseLevel);
3638 return 0;
3639 }
3640 break;
3641 case 2:
3642 voltage_object = (union voltage_object *)
3643 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3644 if (voltage_object) {
3645 ATOM_VOLTAGE_FORMULA_V2 *formula =
3646 &voltage_object->v2.asFormula;
3647 if (formula->ucNumOfVoltageEntries) {
3648 *min_voltage =
3649 le16_to_cpu(formula->asVIDAdjustEntries[
3650 0
3651 ].usVoltageValue);
3652 return 0;
3653 }
3654 }
3655 break;
3656 default:
3657 DRM_ERROR("unknown voltage object table\n");
3658 return -EINVAL;
3659 }
3660
3661 }
3662 return -EINVAL;
3663 }
3664
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3665 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3666 u8 voltage_type, u16 *voltage_step)
3667 {
3668 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3669 u8 frev, crev;
3670 u16 data_offset, size;
3671 union voltage_object_info *voltage_info;
3672 union voltage_object *voltage_object = NULL;
3673
3674 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3675 &frev, &crev, &data_offset)) {
3676 voltage_info = (union voltage_object_info *)
3677 (rdev->mode_info.atom_context->bios + data_offset);
3678
3679 switch (crev) {
3680 case 1:
3681 voltage_object = (union voltage_object *)
3682 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3683 if (voltage_object) {
3684 ATOM_VOLTAGE_FORMULA *formula =
3685 &voltage_object->v1.asFormula;
3686 if (formula->ucFlag & 1)
3687 *voltage_step =
3688 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3689 else
3690 *voltage_step =
3691 le16_to_cpu(formula->usVoltageStep);
3692 return 0;
3693 }
3694 break;
3695 case 2:
3696 return -EINVAL;
3697 default:
3698 DRM_ERROR("unknown voltage object table\n");
3699 return -EINVAL;
3700 }
3701
3702 }
3703 return -EINVAL;
3704 }
3705
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3706 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3707 u8 voltage_type,
3708 u16 nominal_voltage,
3709 u16 *true_voltage)
3710 {
3711 u16 min_voltage, max_voltage, voltage_step;
3712
3713 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3714 return -EINVAL;
3715 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3716 return -EINVAL;
3717 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3718 return -EINVAL;
3719
3720 if (nominal_voltage <= min_voltage)
3721 *true_voltage = min_voltage;
3722 else if (nominal_voltage >= max_voltage)
3723 *true_voltage = max_voltage;
3724 else
3725 *true_voltage = min_voltage +
3726 ((nominal_voltage - min_voltage) / voltage_step) *
3727 voltage_step;
3728
3729 return 0;
3730 }
3731
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3732 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3733 u8 voltage_type, u8 voltage_mode,
3734 struct atom_voltage_table *voltage_table)
3735 {
3736 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3737 u8 frev, crev;
3738 u16 data_offset, size;
3739 int i, ret;
3740 union voltage_object_info *voltage_info;
3741 union voltage_object *voltage_object = NULL;
3742
3743 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3744 &frev, &crev, &data_offset)) {
3745 voltage_info = (union voltage_object_info *)
3746 (rdev->mode_info.atom_context->bios + data_offset);
3747
3748 switch (frev) {
3749 case 1:
3750 case 2:
3751 switch (crev) {
3752 case 1:
3753 DRM_ERROR("old table version %d, %d\n", frev, crev);
3754 return -EINVAL;
3755 case 2:
3756 voltage_object = (union voltage_object *)
3757 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3758 if (voltage_object) {
3759 ATOM_VOLTAGE_FORMULA_V2 *formula =
3760 &voltage_object->v2.asFormula;
3761 VOLTAGE_LUT_ENTRY *lut;
3762 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3763 return -EINVAL;
3764 lut = &formula->asVIDAdjustEntries[0];
3765 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3766 voltage_table->entries[i].value =
3767 le16_to_cpu(lut->usVoltageValue);
3768 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3769 voltage_table->entries[i].value,
3770 voltage_type,
3771 &voltage_table->entries[i].smio_low,
3772 &voltage_table->mask_low);
3773 if (ret)
3774 return ret;
3775 lut = (VOLTAGE_LUT_ENTRY *)
3776 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3777 }
3778 voltage_table->count = formula->ucNumOfVoltageEntries;
3779 return 0;
3780 }
3781 break;
3782 default:
3783 DRM_ERROR("unknown voltage object table\n");
3784 return -EINVAL;
3785 }
3786 break;
3787 case 3:
3788 switch (crev) {
3789 case 1:
3790 voltage_object = (union voltage_object *)
3791 atom_lookup_voltage_object_v3(&voltage_info->v3,
3792 voltage_type, voltage_mode);
3793 if (voltage_object) {
3794 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3795 &voltage_object->v3.asGpioVoltageObj;
3796 VOLTAGE_LUT_ENTRY_V2 *lut;
3797 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3798 return -EINVAL;
3799 lut = &gpio->asVolGpioLut[0];
3800 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3801 voltage_table->entries[i].value =
3802 le16_to_cpu(lut->usVoltageValue);
3803 voltage_table->entries[i].smio_low =
3804 le32_to_cpu(lut->ulVoltageId);
3805 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3806 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3807 }
3808 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3809 voltage_table->count = gpio->ucGpioEntryNum;
3810 voltage_table->phase_delay = gpio->ucPhaseDelay;
3811 return 0;
3812 }
3813 break;
3814 default:
3815 DRM_ERROR("unknown voltage object table\n");
3816 return -EINVAL;
3817 }
3818 break;
3819 default:
3820 DRM_ERROR("unknown voltage object table\n");
3821 return -EINVAL;
3822 }
3823 }
3824 return -EINVAL;
3825 }
3826
3827 union vram_info {
3828 struct _ATOM_VRAM_INFO_V3 v1_3;
3829 struct _ATOM_VRAM_INFO_V4 v1_4;
3830 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3831 };
3832
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3833 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3834 u8 module_index, struct atom_memory_info *mem_info)
3835 {
3836 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3837 u8 frev, crev, i;
3838 u16 data_offset, size;
3839 union vram_info *vram_info;
3840
3841 memset(mem_info, 0, sizeof(struct atom_memory_info));
3842
3843 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3844 &frev, &crev, &data_offset)) {
3845 vram_info = (union vram_info *)
3846 (rdev->mode_info.atom_context->bios + data_offset);
3847 switch (frev) {
3848 case 1:
3849 switch (crev) {
3850 case 3:
3851 /* r6xx */
3852 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3853 ATOM_VRAM_MODULE_V3 *vram_module =
3854 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3855
3856 for (i = 0; i < module_index; i++) {
3857 if (le16_to_cpu(vram_module->usSize) == 0)
3858 return -EINVAL;
3859 vram_module = (ATOM_VRAM_MODULE_V3 *)
3860 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3861 }
3862 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3863 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3864 } else
3865 return -EINVAL;
3866 break;
3867 case 4:
3868 /* r7xx, evergreen */
3869 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3870 ATOM_VRAM_MODULE_V4 *vram_module =
3871 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3872
3873 for (i = 0; i < module_index; i++) {
3874 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3875 return -EINVAL;
3876 vram_module = (ATOM_VRAM_MODULE_V4 *)
3877 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3878 }
3879 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3880 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3881 } else
3882 return -EINVAL;
3883 break;
3884 default:
3885 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3886 return -EINVAL;
3887 }
3888 break;
3889 case 2:
3890 switch (crev) {
3891 case 1:
3892 /* ni */
3893 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3894 ATOM_VRAM_MODULE_V7 *vram_module =
3895 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3896
3897 for (i = 0; i < module_index; i++) {
3898 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3899 return -EINVAL;
3900 vram_module = (ATOM_VRAM_MODULE_V7 *)
3901 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3902 }
3903 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3904 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3905 } else
3906 return -EINVAL;
3907 break;
3908 default:
3909 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3910 return -EINVAL;
3911 }
3912 break;
3913 default:
3914 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3915 return -EINVAL;
3916 }
3917 return 0;
3918 }
3919 return -EINVAL;
3920 }
3921
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3922 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3923 bool gddr5, u8 module_index,
3924 struct atom_memory_clock_range_table *mclk_range_table)
3925 {
3926 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3927 u8 frev, crev, i;
3928 u16 data_offset, size;
3929 union vram_info *vram_info;
3930 u32 mem_timing_size = gddr5 ?
3931 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3932
3933 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3934
3935 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3936 &frev, &crev, &data_offset)) {
3937 vram_info = (union vram_info *)
3938 (rdev->mode_info.atom_context->bios + data_offset);
3939 switch (frev) {
3940 case 1:
3941 switch (crev) {
3942 case 3:
3943 DRM_ERROR("old table version %d, %d\n", frev, crev);
3944 return -EINVAL;
3945 case 4:
3946 /* r7xx, evergreen */
3947 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3948 ATOM_VRAM_MODULE_V4 *vram_module =
3949 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3950 ATOM_MEMORY_TIMING_FORMAT *format;
3951
3952 for (i = 0; i < module_index; i++) {
3953 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3954 return -EINVAL;
3955 vram_module = (ATOM_VRAM_MODULE_V4 *)
3956 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3957 }
3958 mclk_range_table->num_entries = (u8)
3959 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3960 mem_timing_size);
3961 format = &vram_module->asMemTiming[0];
3962 for (i = 0; i < mclk_range_table->num_entries; i++) {
3963 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3964 format = (ATOM_MEMORY_TIMING_FORMAT *)
3965 ((u8 *)format + mem_timing_size);
3966 }
3967 } else
3968 return -EINVAL;
3969 break;
3970 default:
3971 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3972 return -EINVAL;
3973 }
3974 break;
3975 case 2:
3976 DRM_ERROR("new table version %d, %d\n", frev, crev);
3977 return -EINVAL;
3978 default:
3979 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3980 return -EINVAL;
3981 }
3982 return 0;
3983 }
3984 return -EINVAL;
3985 }
3986
3987 #define MEM_ID_MASK 0xff000000
3988 #define MEM_ID_SHIFT 24
3989 #define CLOCK_RANGE_MASK 0x00ffffff
3990 #define CLOCK_RANGE_SHIFT 0
3991 #define LOW_NIBBLE_MASK 0xf
3992 #define DATA_EQU_PREV 0
3993 #define DATA_FROM_TABLE 4
3994
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3995 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3996 u8 module_index,
3997 struct atom_mc_reg_table *reg_table)
3998 {
3999 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
4000 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
4001 u32 i = 0, j;
4002 u16 data_offset, size;
4003 union vram_info *vram_info;
4004
4005 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
4006
4007 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
4008 &frev, &crev, &data_offset)) {
4009 vram_info = (union vram_info *)
4010 (rdev->mode_info.atom_context->bios + data_offset);
4011 switch (frev) {
4012 case 1:
4013 DRM_ERROR("old table version %d, %d\n", frev, crev);
4014 return -EINVAL;
4015 case 2:
4016 switch (crev) {
4017 case 1:
4018 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4019 ATOM_INIT_REG_BLOCK *reg_block =
4020 (ATOM_INIT_REG_BLOCK *)
4021 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4022 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4023 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4024 ((u8 *)reg_block + (2 * sizeof(u16)) +
4025 le16_to_cpu(reg_block->usRegIndexTblSize));
4026 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4027 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4028 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4029 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4030 return -EINVAL;
4031 while (i < num_entries) {
4032 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4033 break;
4034 reg_table->mc_reg_address[i].s1 =
4035 (u16)(le16_to_cpu(format->usRegIndex));
4036 reg_table->mc_reg_address[i].pre_reg_data =
4037 (u8)(format->ucPreRegDataLength);
4038 i++;
4039 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4040 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4041 }
4042 reg_table->last = i;
4043 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4044 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4045 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4046 >> MEM_ID_SHIFT);
4047 if (module_index == t_mem_id) {
4048 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4049 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4050 >> CLOCK_RANGE_SHIFT);
4051 for (i = 0, j = 1; i < reg_table->last; i++) {
4052 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4053 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4054 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4055 j++;
4056 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4057 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4058 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4059 }
4060 }
4061 num_ranges++;
4062 }
4063 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4064 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4065 }
4066 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4067 return -EINVAL;
4068 reg_table->num_entries = num_ranges;
4069 } else
4070 return -EINVAL;
4071 break;
4072 default:
4073 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4074 return -EINVAL;
4075 }
4076 break;
4077 default:
4078 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4079 return -EINVAL;
4080 }
4081 return 0;
4082 }
4083 return -EINVAL;
4084 }
4085
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4086 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4087 {
4088 struct radeon_device *rdev = dev->dev_private;
4089 uint32_t bios_2_scratch, bios_6_scratch;
4090
4091 if (rdev->family >= CHIP_R600) {
4092 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4093 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4094 } else {
4095 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4096 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4097 }
4098
4099 /* let the bios control the backlight */
4100 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4101
4102 /* tell the bios not to handle mode switching */
4103 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4104
4105 /* clear the vbios dpms state */
4106 if (ASIC_IS_DCE4(rdev))
4107 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4108
4109 if (rdev->family >= CHIP_R600) {
4110 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4111 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4112 } else {
4113 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4114 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4115 }
4116
4117 }
4118
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4119 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4120 {
4121 uint32_t scratch_reg;
4122 int i;
4123
4124 if (rdev->family >= CHIP_R600)
4125 scratch_reg = R600_BIOS_0_SCRATCH;
4126 else
4127 scratch_reg = RADEON_BIOS_0_SCRATCH;
4128
4129 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4130 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4131 }
4132
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4133 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4134 {
4135 uint32_t scratch_reg;
4136 int i;
4137
4138 if (rdev->family >= CHIP_R600)
4139 scratch_reg = R600_BIOS_0_SCRATCH;
4140 else
4141 scratch_reg = RADEON_BIOS_0_SCRATCH;
4142
4143 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4144 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4145 }
4146
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4147 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4148 {
4149 struct drm_device *dev = encoder->dev;
4150 struct radeon_device *rdev = dev->dev_private;
4151 uint32_t bios_6_scratch;
4152
4153 if (rdev->family >= CHIP_R600)
4154 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4155 else
4156 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4157
4158 if (lock) {
4159 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4160 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4161 } else {
4162 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4163 bios_6_scratch |= ATOM_S6_ACC_MODE;
4164 }
4165
4166 if (rdev->family >= CHIP_R600)
4167 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4168 else
4169 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4170 }
4171
4172 /* at some point we may want to break this out into individual functions */
4173 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4174 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4175 struct drm_encoder *encoder,
4176 bool connected)
4177 {
4178 struct drm_device *dev = connector->dev;
4179 struct radeon_device *rdev = dev->dev_private;
4180 struct radeon_connector *radeon_connector =
4181 to_radeon_connector(connector);
4182 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4183 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4184
4185 if (rdev->family >= CHIP_R600) {
4186 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4187 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4188 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4189 } else {
4190 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4191 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4192 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4193 }
4194
4195 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4196 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4197 if (connected) {
4198 DRM_DEBUG_KMS("TV1 connected\n");
4199 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4200 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4201 } else {
4202 DRM_DEBUG_KMS("TV1 disconnected\n");
4203 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4204 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4205 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4206 }
4207 }
4208 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4209 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4210 if (connected) {
4211 DRM_DEBUG_KMS("CV connected\n");
4212 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4213 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4214 } else {
4215 DRM_DEBUG_KMS("CV disconnected\n");
4216 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4217 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4218 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4219 }
4220 }
4221 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4222 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4223 if (connected) {
4224 DRM_DEBUG_KMS("LCD1 connected\n");
4225 bios_0_scratch |= ATOM_S0_LCD1;
4226 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4227 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4228 } else {
4229 DRM_DEBUG_KMS("LCD1 disconnected\n");
4230 bios_0_scratch &= ~ATOM_S0_LCD1;
4231 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4232 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4233 }
4234 }
4235 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4236 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4237 if (connected) {
4238 DRM_DEBUG_KMS("CRT1 connected\n");
4239 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4240 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4241 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4242 } else {
4243 DRM_DEBUG_KMS("CRT1 disconnected\n");
4244 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4245 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4246 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4247 }
4248 }
4249 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4250 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4251 if (connected) {
4252 DRM_DEBUG_KMS("CRT2 connected\n");
4253 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4254 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4255 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4256 } else {
4257 DRM_DEBUG_KMS("CRT2 disconnected\n");
4258 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4259 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4260 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4261 }
4262 }
4263 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4264 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4265 if (connected) {
4266 DRM_DEBUG_KMS("DFP1 connected\n");
4267 bios_0_scratch |= ATOM_S0_DFP1;
4268 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4269 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4270 } else {
4271 DRM_DEBUG_KMS("DFP1 disconnected\n");
4272 bios_0_scratch &= ~ATOM_S0_DFP1;
4273 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4274 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4275 }
4276 }
4277 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4278 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4279 if (connected) {
4280 DRM_DEBUG_KMS("DFP2 connected\n");
4281 bios_0_scratch |= ATOM_S0_DFP2;
4282 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4283 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4284 } else {
4285 DRM_DEBUG_KMS("DFP2 disconnected\n");
4286 bios_0_scratch &= ~ATOM_S0_DFP2;
4287 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4288 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4289 }
4290 }
4291 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4292 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4293 if (connected) {
4294 DRM_DEBUG_KMS("DFP3 connected\n");
4295 bios_0_scratch |= ATOM_S0_DFP3;
4296 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4297 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4298 } else {
4299 DRM_DEBUG_KMS("DFP3 disconnected\n");
4300 bios_0_scratch &= ~ATOM_S0_DFP3;
4301 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4302 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4303 }
4304 }
4305 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4306 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4307 if (connected) {
4308 DRM_DEBUG_KMS("DFP4 connected\n");
4309 bios_0_scratch |= ATOM_S0_DFP4;
4310 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4311 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4312 } else {
4313 DRM_DEBUG_KMS("DFP4 disconnected\n");
4314 bios_0_scratch &= ~ATOM_S0_DFP4;
4315 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4316 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4317 }
4318 }
4319 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4320 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4321 if (connected) {
4322 DRM_DEBUG_KMS("DFP5 connected\n");
4323 bios_0_scratch |= ATOM_S0_DFP5;
4324 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4325 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4326 } else {
4327 DRM_DEBUG_KMS("DFP5 disconnected\n");
4328 bios_0_scratch &= ~ATOM_S0_DFP5;
4329 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4330 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4331 }
4332 }
4333 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4334 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4335 if (connected) {
4336 DRM_DEBUG_KMS("DFP6 connected\n");
4337 bios_0_scratch |= ATOM_S0_DFP6;
4338 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4339 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4340 } else {
4341 DRM_DEBUG_KMS("DFP6 disconnected\n");
4342 bios_0_scratch &= ~ATOM_S0_DFP6;
4343 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4344 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4345 }
4346 }
4347
4348 if (rdev->family >= CHIP_R600) {
4349 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4350 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4351 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4352 } else {
4353 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4354 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4355 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4356 }
4357 }
4358
4359 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4360 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4361 {
4362 struct drm_device *dev = encoder->dev;
4363 struct radeon_device *rdev = dev->dev_private;
4364 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4365 uint32_t bios_3_scratch;
4366
4367 if (ASIC_IS_DCE4(rdev))
4368 return;
4369
4370 if (rdev->family >= CHIP_R600)
4371 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4372 else
4373 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4374
4375 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4376 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4377 bios_3_scratch |= (crtc << 18);
4378 }
4379 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4380 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4381 bios_3_scratch |= (crtc << 24);
4382 }
4383 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4384 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4385 bios_3_scratch |= (crtc << 16);
4386 }
4387 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4388 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4389 bios_3_scratch |= (crtc << 20);
4390 }
4391 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4392 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4393 bios_3_scratch |= (crtc << 17);
4394 }
4395 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4396 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4397 bios_3_scratch |= (crtc << 19);
4398 }
4399 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4400 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4401 bios_3_scratch |= (crtc << 23);
4402 }
4403 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4404 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4405 bios_3_scratch |= (crtc << 25);
4406 }
4407
4408 if (rdev->family >= CHIP_R600)
4409 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4410 else
4411 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4412 }
4413
4414 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4415 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4416 {
4417 struct drm_device *dev = encoder->dev;
4418 struct radeon_device *rdev = dev->dev_private;
4419 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4420 uint32_t bios_2_scratch;
4421
4422 if (ASIC_IS_DCE4(rdev))
4423 return;
4424
4425 if (rdev->family >= CHIP_R600)
4426 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4427 else
4428 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4429
4430 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4431 if (on)
4432 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4433 else
4434 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4435 }
4436 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4437 if (on)
4438 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4439 else
4440 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4441 }
4442 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4443 if (on)
4444 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4445 else
4446 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4447 }
4448 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4449 if (on)
4450 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4451 else
4452 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4453 }
4454 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4455 if (on)
4456 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4457 else
4458 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4459 }
4460 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4461 if (on)
4462 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4463 else
4464 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4465 }
4466 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4467 if (on)
4468 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4469 else
4470 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4471 }
4472 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4473 if (on)
4474 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4475 else
4476 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4477 }
4478 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4479 if (on)
4480 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4481 else
4482 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4483 }
4484 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4485 if (on)
4486 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4487 else
4488 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4489 }
4490
4491 if (rdev->family >= CHIP_R600)
4492 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4493 else
4494 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4495 }
4496