1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/pci.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include <drm/drm_file.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/radeon_drm.h>
38
39 #include "radeon.h"
40 #include "radeon_asic.h"
41 #include "radeon_drv.h"
42 #include "radeon_kms.h"
43
44 #if defined(CONFIG_VGA_SWITCHEROO)
45 bool radeon_has_atpx(void);
46 #else
radeon_has_atpx(void)47 static inline bool radeon_has_atpx(void) { return false; }
48 #endif
49
50 /**
51 * radeon_driver_unload_kms - Main unload function for KMS.
52 *
53 * @dev: drm dev pointer
54 *
55 * This is the main unload function for KMS (all asics).
56 * It calls radeon_modeset_fini() to tear down the
57 * displays, and radeon_device_fini() to tear down
58 * the rest of the device (CP, writeback, etc.).
59 * Returns 0 on success.
60 */
61 #ifdef __linux__
radeon_driver_unload_kms(struct drm_device * dev)62 void radeon_driver_unload_kms(struct drm_device *dev)
63 {
64 struct radeon_device *rdev = dev->dev_private;
65
66 if (rdev == NULL)
67 return;
68
69 if (rdev->rmmio == NULL)
70 goto done_free;
71
72 if (radeon_is_px(dev)) {
73 pm_runtime_get_sync(dev->dev);
74 pm_runtime_forbid(dev->dev);
75 }
76
77 radeon_acpi_fini(rdev);
78
79 radeon_modeset_fini(rdev);
80 radeon_device_fini(rdev);
81
82 if (rdev->agp)
83 arch_phys_wc_del(rdev->agp->agp_mtrr);
84 kfree(rdev->agp);
85 rdev->agp = NULL;
86
87 done_free:
88 kfree(rdev);
89 dev->dev_private = NULL;
90 }
91
92 /**
93 * radeon_driver_load_kms - Main load function for KMS.
94 *
95 * @dev: drm dev pointer
96 * @flags: device flags
97 *
98 * This is the main load function for KMS (all asics).
99 * It calls radeon_device_init() to set up the non-display
100 * parts of the chip (asic init, CP, writeback, etc.), and
101 * radeon_modeset_init() to set up the display parts
102 * (crtcs, encoders, hotplug detect, etc.).
103 * Returns 0 on success, error on failure.
104 */
radeon_driver_load_kms(struct drm_device * dev,unsigned long flags)105 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
106 {
107 struct pci_dev *pdev = to_pci_dev(dev->dev);
108 struct radeon_device *rdev;
109 int r, acpi_status;
110
111 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
112 if (rdev == NULL) {
113 return -ENOMEM;
114 }
115 dev->dev_private = (void *)rdev;
116
117 #ifdef __alpha__
118 rdev->hose = pdev->sysdata;
119 #endif
120
121 if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
122 rdev->agp = radeon_agp_head_init(dev);
123 if (rdev->agp) {
124 rdev->agp->agp_mtrr = arch_phys_wc_add(
125 rdev->agp->agp_info.aper_base,
126 rdev->agp->agp_info.aper_size *
127 1024 * 1024);
128 }
129
130 /* update BUS flag */
131 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
132 flags |= RADEON_IS_AGP;
133 } else if (pci_is_pcie(pdev)) {
134 flags |= RADEON_IS_PCIE;
135 } else {
136 flags |= RADEON_IS_PCI;
137 }
138
139 if ((radeon_runtime_pm != 0) &&
140 radeon_has_atpx() &&
141 ((flags & RADEON_IS_IGP) == 0) &&
142 !pci_is_thunderbolt_attached(pdev))
143 flags |= RADEON_IS_PX;
144
145 /* radeon_device_init should report only fatal error
146 * like memory allocation failure or iomapping failure,
147 * or memory manager initialization failure, it must
148 * properly initialize the GPU MC controller and permit
149 * VRAM allocation
150 */
151 r = radeon_device_init(rdev, dev, pdev, flags);
152 if (r) {
153 dev_err(dev->dev, "Fatal error during GPU init\n");
154 goto out;
155 }
156
157 /* Again modeset_init should fail only on fatal error
158 * otherwise it should provide enough functionalities
159 * for shadowfb to run
160 */
161 r = radeon_modeset_init(rdev);
162 if (r)
163 dev_err(dev->dev, "Fatal error during modeset init\n");
164
165 /* Call ACPI methods: require modeset init
166 * but failure is not fatal
167 */
168 if (!r) {
169 acpi_status = radeon_acpi_init(rdev);
170 if (acpi_status)
171 dev_dbg(dev->dev, "Error during ACPI methods call\n");
172 }
173
174 if (radeon_is_px(dev)) {
175 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
176 pm_runtime_use_autosuspend(dev->dev);
177 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
178 pm_runtime_set_active(dev->dev);
179 pm_runtime_allow(dev->dev);
180 pm_runtime_mark_last_busy(dev->dev);
181 pm_runtime_put_autosuspend(dev->dev);
182 }
183
184 out:
185 if (r)
186 radeon_driver_unload_kms(dev);
187
188
189 return r;
190 }
191 #endif
192
193 /**
194 * radeon_set_filp_rights - Set filp right.
195 *
196 * @dev: drm dev pointer
197 * @owner: drm file
198 * @applier: drm file
199 * @value: value
200 *
201 * Sets the filp rights for the device (all asics).
202 */
radeon_set_filp_rights(struct drm_device * dev,struct drm_file ** owner,struct drm_file * applier,uint32_t * value)203 static void radeon_set_filp_rights(struct drm_device *dev,
204 struct drm_file **owner,
205 struct drm_file *applier,
206 uint32_t *value)
207 {
208 struct radeon_device *rdev = dev->dev_private;
209
210 mutex_lock(&rdev->gem.mutex);
211 if (*value == 1) {
212 /* wants rights */
213 if (!*owner)
214 *owner = applier;
215 } else if (*value == 0) {
216 /* revokes rights */
217 if (*owner == applier)
218 *owner = NULL;
219 }
220 *value = *owner == applier ? 1 : 0;
221 mutex_unlock(&rdev->gem.mutex);
222 }
223
224 /*
225 * Userspace get information ioctl
226 */
227 /**
228 * radeon_info_ioctl - answer a device specific request.
229 *
230 * @dev: drm device pointer
231 * @data: request object
232 * @filp: drm filp
233 *
234 * This function is used to pass device specific parameters to the userspace
235 * drivers. Examples include: pci device id, pipeline parms, tiling params,
236 * etc. (all asics).
237 * Returns 0 on success, -EINVAL on failure.
238 */
radeon_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)239 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
240 {
241 struct radeon_device *rdev = dev->dev_private;
242 struct drm_radeon_info *info = data;
243 struct radeon_mode_info *minfo = &rdev->mode_info;
244 uint32_t *value, value_tmp, *value_ptr, value_size;
245 struct ttm_resource_manager *man;
246 uint64_t value64;
247 struct drm_crtc *crtc;
248 int i, found;
249
250 value_ptr = (uint32_t *)((unsigned long)info->value);
251 value = &value_tmp;
252 value_size = sizeof(uint32_t);
253
254 switch (info->request) {
255 case RADEON_INFO_DEVICE_ID:
256 #ifdef __linux__
257 *value = to_pci_dev(dev->dev)->device;
258 #else
259 *value = dev->pdev->device;
260 #endif
261 break;
262 case RADEON_INFO_NUM_GB_PIPES:
263 *value = rdev->num_gb_pipes;
264 break;
265 case RADEON_INFO_NUM_Z_PIPES:
266 *value = rdev->num_z_pipes;
267 break;
268 case RADEON_INFO_ACCEL_WORKING:
269 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
270 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
271 *value = false;
272 else
273 *value = rdev->accel_working;
274 break;
275 case RADEON_INFO_CRTC_FROM_ID:
276 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
277 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
278 return -EFAULT;
279 }
280 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
281 crtc = (struct drm_crtc *)minfo->crtcs[i];
282 if (crtc && crtc->base.id == *value) {
283 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
284 *value = radeon_crtc->crtc_id;
285 found = 1;
286 break;
287 }
288 }
289 if (!found) {
290 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
291 return -EINVAL;
292 }
293 break;
294 case RADEON_INFO_ACCEL_WORKING2:
295 if (rdev->family == CHIP_HAWAII) {
296 if (rdev->accel_working) {
297 if (rdev->new_fw)
298 *value = 3;
299 else
300 *value = 2;
301 } else {
302 *value = 0;
303 }
304 } else {
305 *value = rdev->accel_working;
306 }
307 break;
308 case RADEON_INFO_TILING_CONFIG:
309 if (rdev->family >= CHIP_BONAIRE)
310 *value = rdev->config.cik.tile_config;
311 else if (rdev->family >= CHIP_TAHITI)
312 *value = rdev->config.si.tile_config;
313 else if (rdev->family >= CHIP_CAYMAN)
314 *value = rdev->config.cayman.tile_config;
315 else if (rdev->family >= CHIP_CEDAR)
316 *value = rdev->config.evergreen.tile_config;
317 else if (rdev->family >= CHIP_RV770)
318 *value = rdev->config.rv770.tile_config;
319 else if (rdev->family >= CHIP_R600)
320 *value = rdev->config.r600.tile_config;
321 else {
322 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
323 return -EINVAL;
324 }
325 break;
326 case RADEON_INFO_WANT_HYPERZ:
327 /* The "value" here is both an input and output parameter.
328 * If the input value is 1, filp requests hyper-z access.
329 * If the input value is 0, filp revokes its hyper-z access.
330 *
331 * When returning, the value is 1 if filp owns hyper-z access,
332 * 0 otherwise. */
333 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
334 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
335 return -EFAULT;
336 }
337 if (*value >= 2) {
338 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
339 return -EINVAL;
340 }
341 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
342 break;
343 case RADEON_INFO_WANT_CMASK:
344 /* The same logic as Hyper-Z. */
345 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
346 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
347 return -EFAULT;
348 }
349 if (*value >= 2) {
350 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
351 return -EINVAL;
352 }
353 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
354 break;
355 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
356 /* return clock value in KHz */
357 if (rdev->asic->get_xclk)
358 *value = radeon_get_xclk(rdev) * 10;
359 else
360 *value = rdev->clock.spll.reference_freq * 10;
361 break;
362 case RADEON_INFO_NUM_BACKENDS:
363 if (rdev->family >= CHIP_BONAIRE)
364 *value = rdev->config.cik.max_backends_per_se *
365 rdev->config.cik.max_shader_engines;
366 else if (rdev->family >= CHIP_TAHITI)
367 *value = rdev->config.si.max_backends_per_se *
368 rdev->config.si.max_shader_engines;
369 else if (rdev->family >= CHIP_CAYMAN)
370 *value = rdev->config.cayman.max_backends_per_se *
371 rdev->config.cayman.max_shader_engines;
372 else if (rdev->family >= CHIP_CEDAR)
373 *value = rdev->config.evergreen.max_backends;
374 else if (rdev->family >= CHIP_RV770)
375 *value = rdev->config.rv770.max_backends;
376 else if (rdev->family >= CHIP_R600)
377 *value = rdev->config.r600.max_backends;
378 else {
379 return -EINVAL;
380 }
381 break;
382 case RADEON_INFO_NUM_TILE_PIPES:
383 if (rdev->family >= CHIP_BONAIRE)
384 *value = rdev->config.cik.max_tile_pipes;
385 else if (rdev->family >= CHIP_TAHITI)
386 *value = rdev->config.si.max_tile_pipes;
387 else if (rdev->family >= CHIP_CAYMAN)
388 *value = rdev->config.cayman.max_tile_pipes;
389 else if (rdev->family >= CHIP_CEDAR)
390 *value = rdev->config.evergreen.max_tile_pipes;
391 else if (rdev->family >= CHIP_RV770)
392 *value = rdev->config.rv770.max_tile_pipes;
393 else if (rdev->family >= CHIP_R600)
394 *value = rdev->config.r600.max_tile_pipes;
395 else {
396 return -EINVAL;
397 }
398 break;
399 case RADEON_INFO_FUSION_GART_WORKING:
400 *value = 1;
401 break;
402 case RADEON_INFO_BACKEND_MAP:
403 if (rdev->family >= CHIP_BONAIRE)
404 *value = rdev->config.cik.backend_map;
405 else if (rdev->family >= CHIP_TAHITI)
406 *value = rdev->config.si.backend_map;
407 else if (rdev->family >= CHIP_CAYMAN)
408 *value = rdev->config.cayman.backend_map;
409 else if (rdev->family >= CHIP_CEDAR)
410 *value = rdev->config.evergreen.backend_map;
411 else if (rdev->family >= CHIP_RV770)
412 *value = rdev->config.rv770.backend_map;
413 else if (rdev->family >= CHIP_R600)
414 *value = rdev->config.r600.backend_map;
415 else {
416 return -EINVAL;
417 }
418 break;
419 case RADEON_INFO_VA_START:
420 /* this is where we report if vm is supported or not */
421 if (rdev->family < CHIP_CAYMAN)
422 return -EINVAL;
423 *value = RADEON_VA_RESERVED_SIZE;
424 break;
425 case RADEON_INFO_IB_VM_MAX_SIZE:
426 /* this is where we report if vm is supported or not */
427 if (rdev->family < CHIP_CAYMAN)
428 return -EINVAL;
429 *value = RADEON_IB_VM_MAX_SIZE;
430 break;
431 case RADEON_INFO_MAX_PIPES:
432 if (rdev->family >= CHIP_BONAIRE)
433 *value = rdev->config.cik.max_cu_per_sh;
434 else if (rdev->family >= CHIP_TAHITI)
435 *value = rdev->config.si.max_cu_per_sh;
436 else if (rdev->family >= CHIP_CAYMAN)
437 *value = rdev->config.cayman.max_pipes_per_simd;
438 else if (rdev->family >= CHIP_CEDAR)
439 *value = rdev->config.evergreen.max_pipes;
440 else if (rdev->family >= CHIP_RV770)
441 *value = rdev->config.rv770.max_pipes;
442 else if (rdev->family >= CHIP_R600)
443 *value = rdev->config.r600.max_pipes;
444 else {
445 return -EINVAL;
446 }
447 break;
448 case RADEON_INFO_TIMESTAMP:
449 if (rdev->family < CHIP_R600) {
450 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
451 return -EINVAL;
452 }
453 value = (uint32_t *)&value64;
454 value_size = sizeof(uint64_t);
455 value64 = radeon_get_gpu_clock_counter(rdev);
456 break;
457 case RADEON_INFO_MAX_SE:
458 if (rdev->family >= CHIP_BONAIRE)
459 *value = rdev->config.cik.max_shader_engines;
460 else if (rdev->family >= CHIP_TAHITI)
461 *value = rdev->config.si.max_shader_engines;
462 else if (rdev->family >= CHIP_CAYMAN)
463 *value = rdev->config.cayman.max_shader_engines;
464 else if (rdev->family >= CHIP_CEDAR)
465 *value = rdev->config.evergreen.num_ses;
466 else
467 *value = 1;
468 break;
469 case RADEON_INFO_MAX_SH_PER_SE:
470 if (rdev->family >= CHIP_BONAIRE)
471 *value = rdev->config.cik.max_sh_per_se;
472 else if (rdev->family >= CHIP_TAHITI)
473 *value = rdev->config.si.max_sh_per_se;
474 else
475 return -EINVAL;
476 break;
477 case RADEON_INFO_FASTFB_WORKING:
478 *value = rdev->fastfb_working;
479 break;
480 case RADEON_INFO_RING_WORKING:
481 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
482 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
483 return -EFAULT;
484 }
485 switch (*value) {
486 case RADEON_CS_RING_GFX:
487 case RADEON_CS_RING_COMPUTE:
488 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
489 break;
490 case RADEON_CS_RING_DMA:
491 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
492 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
493 break;
494 case RADEON_CS_RING_UVD:
495 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
496 break;
497 case RADEON_CS_RING_VCE:
498 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
499 break;
500 default:
501 return -EINVAL;
502 }
503 break;
504 case RADEON_INFO_SI_TILE_MODE_ARRAY:
505 if (rdev->family >= CHIP_BONAIRE) {
506 value = rdev->config.cik.tile_mode_array;
507 value_size = sizeof(uint32_t)*32;
508 } else if (rdev->family >= CHIP_TAHITI) {
509 value = rdev->config.si.tile_mode_array;
510 value_size = sizeof(uint32_t)*32;
511 } else {
512 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
513 return -EINVAL;
514 }
515 break;
516 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
517 if (rdev->family >= CHIP_BONAIRE) {
518 value = rdev->config.cik.macrotile_mode_array;
519 value_size = sizeof(uint32_t)*16;
520 } else {
521 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
522 return -EINVAL;
523 }
524 break;
525 case RADEON_INFO_SI_CP_DMA_COMPUTE:
526 *value = 1;
527 break;
528 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
529 if (rdev->family >= CHIP_BONAIRE) {
530 *value = rdev->config.cik.backend_enable_mask;
531 } else if (rdev->family >= CHIP_TAHITI) {
532 *value = rdev->config.si.backend_enable_mask;
533 } else {
534 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
535 return -EINVAL;
536 }
537 break;
538 case RADEON_INFO_MAX_SCLK:
539 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
540 rdev->pm.dpm_enabled)
541 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
542 else
543 *value = rdev->pm.default_sclk * 10;
544 break;
545 case RADEON_INFO_VCE_FW_VERSION:
546 *value = rdev->vce.fw_version;
547 break;
548 case RADEON_INFO_VCE_FB_VERSION:
549 *value = rdev->vce.fb_version;
550 break;
551 case RADEON_INFO_NUM_BYTES_MOVED:
552 value = (uint32_t *)&value64;
553 value_size = sizeof(uint64_t);
554 value64 = atomic64_read(&rdev->num_bytes_moved);
555 break;
556 case RADEON_INFO_VRAM_USAGE:
557 value = (uint32_t *)&value64;
558 value_size = sizeof(uint64_t);
559 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
560 value64 = ttm_resource_manager_usage(man);
561 break;
562 case RADEON_INFO_GTT_USAGE:
563 value = (uint32_t *)&value64;
564 value_size = sizeof(uint64_t);
565 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT);
566 value64 = ttm_resource_manager_usage(man);
567 break;
568 case RADEON_INFO_ACTIVE_CU_COUNT:
569 if (rdev->family >= CHIP_BONAIRE)
570 *value = rdev->config.cik.active_cus;
571 else if (rdev->family >= CHIP_TAHITI)
572 *value = rdev->config.si.active_cus;
573 else if (rdev->family >= CHIP_CAYMAN)
574 *value = rdev->config.cayman.active_simds;
575 else if (rdev->family >= CHIP_CEDAR)
576 *value = rdev->config.evergreen.active_simds;
577 else if (rdev->family >= CHIP_RV770)
578 *value = rdev->config.rv770.active_simds;
579 else if (rdev->family >= CHIP_R600)
580 *value = rdev->config.r600.active_simds;
581 else
582 *value = 1;
583 break;
584 case RADEON_INFO_CURRENT_GPU_TEMP:
585 /* get temperature in millidegrees C */
586 if (rdev->asic->pm.get_temperature)
587 *value = radeon_get_temperature(rdev);
588 else
589 *value = 0;
590 break;
591 case RADEON_INFO_CURRENT_GPU_SCLK:
592 /* get sclk in Mhz */
593 if (rdev->pm.dpm_enabled)
594 *value = radeon_dpm_get_current_sclk(rdev) / 100;
595 else
596 *value = rdev->pm.current_sclk / 100;
597 break;
598 case RADEON_INFO_CURRENT_GPU_MCLK:
599 /* get mclk in Mhz */
600 if (rdev->pm.dpm_enabled)
601 *value = radeon_dpm_get_current_mclk(rdev) / 100;
602 else
603 *value = rdev->pm.current_mclk / 100;
604 break;
605 case RADEON_INFO_READ_REG:
606 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
607 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
608 return -EFAULT;
609 }
610 if (radeon_get_allowed_info_register(rdev, *value, value))
611 return -EINVAL;
612 break;
613 case RADEON_INFO_VA_UNMAP_WORKING:
614 *value = true;
615 break;
616 case RADEON_INFO_GPU_RESET_COUNTER:
617 *value = atomic_read(&rdev->gpu_reset_counter);
618 break;
619 default:
620 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
621 return -EINVAL;
622 }
623 if (copy_to_user(value_ptr, (char *)value, value_size)) {
624 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
625 return -EFAULT;
626 }
627 return 0;
628 }
629
630 /**
631 * radeon_driver_open_kms - drm callback for open
632 *
633 * @dev: drm dev pointer
634 * @file_priv: drm file
635 *
636 * On device open, init vm on cayman+ (all asics).
637 * Returns 0 on success, error on failure.
638 */
radeon_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)639 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
640 {
641 struct radeon_device *rdev = dev->dev_private;
642 struct radeon_fpriv *fpriv;
643 struct radeon_vm *vm;
644 int r;
645
646 file_priv->driver_priv = NULL;
647
648 r = pm_runtime_get_sync(dev->dev);
649 if (r < 0) {
650 pm_runtime_put_autosuspend(dev->dev);
651 return r;
652 }
653
654 /* new gpu have virtual address space support */
655 if (rdev->family >= CHIP_CAYMAN) {
656
657 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
658 if (unlikely(!fpriv)) {
659 r = -ENOMEM;
660 goto err_suspend;
661 }
662
663 if (rdev->accel_working) {
664 vm = &fpriv->vm;
665 r = radeon_vm_init(rdev, vm);
666 if (r)
667 goto err_fpriv;
668
669 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
670 if (r)
671 goto err_vm_fini;
672
673 /* map the ib pool buffer read only into
674 * virtual address space */
675 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
676 rdev->ring_tmp_bo.bo);
677 if (!vm->ib_bo_va) {
678 r = -ENOMEM;
679 goto err_vm_fini;
680 }
681
682 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
683 RADEON_VA_IB_OFFSET,
684 RADEON_VM_PAGE_READABLE |
685 RADEON_VM_PAGE_SNOOPED);
686 if (r)
687 goto err_vm_fini;
688 }
689 file_priv->driver_priv = fpriv;
690 }
691
692 pm_runtime_mark_last_busy(dev->dev);
693 pm_runtime_put_autosuspend(dev->dev);
694 return 0;
695
696 err_vm_fini:
697 radeon_vm_fini(rdev, vm);
698 err_fpriv:
699 kfree(fpriv);
700
701 err_suspend:
702 pm_runtime_mark_last_busy(dev->dev);
703 pm_runtime_put_autosuspend(dev->dev);
704 return r;
705 }
706
707 /**
708 * radeon_driver_postclose_kms - drm callback for post close
709 *
710 * @dev: drm dev pointer
711 * @file_priv: drm file
712 *
713 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
714 * (all asics). And tear down vm on cayman+ (all asics).
715 */
radeon_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)716 void radeon_driver_postclose_kms(struct drm_device *dev,
717 struct drm_file *file_priv)
718 {
719 struct radeon_device *rdev = dev->dev_private;
720
721 pm_runtime_get_sync(dev->dev);
722
723 mutex_lock(&rdev->gem.mutex);
724 if (rdev->hyperz_filp == file_priv)
725 rdev->hyperz_filp = NULL;
726 if (rdev->cmask_filp == file_priv)
727 rdev->cmask_filp = NULL;
728 mutex_unlock(&rdev->gem.mutex);
729
730 radeon_uvd_free_handles(rdev, file_priv);
731 radeon_vce_free_handles(rdev, file_priv);
732
733 /* new gpu have virtual address space support */
734 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
735 struct radeon_fpriv *fpriv = file_priv->driver_priv;
736 struct radeon_vm *vm = &fpriv->vm;
737 int r;
738
739 if (rdev->accel_working) {
740 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
741 if (!r) {
742 if (vm->ib_bo_va)
743 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
744 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
745 }
746 radeon_vm_fini(rdev, vm);
747 }
748
749 kfree(fpriv);
750 file_priv->driver_priv = NULL;
751 }
752 pm_runtime_mark_last_busy(dev->dev);
753 pm_runtime_put_autosuspend(dev->dev);
754 }
755
756 /*
757 * VBlank related functions.
758 */
759 /**
760 * radeon_get_vblank_counter_kms - get frame count
761 *
762 * @crtc: crtc to get the frame count from
763 *
764 * Gets the frame count on the requested crtc (all asics).
765 * Returns frame count on success, -EINVAL on failure.
766 */
radeon_get_vblank_counter_kms(struct drm_crtc * crtc)767 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
768 {
769 struct drm_device *dev = crtc->dev;
770 unsigned int pipe = crtc->index;
771 int vpos, hpos, stat;
772 u32 count;
773 struct radeon_device *rdev = dev->dev_private;
774
775 if (pipe >= rdev->num_crtc) {
776 DRM_ERROR("Invalid crtc %u\n", pipe);
777 return -EINVAL;
778 }
779
780 /* The hw increments its frame counter at start of vsync, not at start
781 * of vblank, as is required by DRM core vblank counter handling.
782 * Cook the hw count here to make it appear to the caller as if it
783 * incremented at start of vblank. We measure distance to start of
784 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
785 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
786 * result by 1 to give the proper appearance to caller.
787 */
788 if (rdev->mode_info.crtcs[pipe]) {
789 /* Repeat readout if needed to provide stable result if
790 * we cross start of vsync during the queries.
791 */
792 do {
793 count = radeon_get_vblank_counter(rdev, pipe);
794 /* Ask radeon_get_crtc_scanoutpos to return vpos as
795 * distance to start of vblank, instead of regular
796 * vertical scanout pos.
797 */
798 stat = radeon_get_crtc_scanoutpos(
799 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
800 &vpos, &hpos, NULL, NULL,
801 &rdev->mode_info.crtcs[pipe]->base.hwmode);
802 } while (count != radeon_get_vblank_counter(rdev, pipe));
803
804 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
805 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
806 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
807 }
808 else {
809 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
810 pipe, vpos);
811
812 /* Bump counter if we are at >= leading edge of vblank,
813 * but before vsync where vpos would turn negative and
814 * the hw counter really increments.
815 */
816 if (vpos >= 0)
817 count++;
818 }
819 }
820 else {
821 /* Fallback to use value as is. */
822 count = radeon_get_vblank_counter(rdev, pipe);
823 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
824 }
825
826 return count;
827 }
828
829 /**
830 * radeon_enable_vblank_kms - enable vblank interrupt
831 *
832 * @crtc: crtc to enable vblank interrupt for
833 *
834 * Enable the interrupt on the requested crtc (all asics).
835 * Returns 0 on success, -EINVAL on failure.
836 */
radeon_enable_vblank_kms(struct drm_crtc * crtc)837 int radeon_enable_vblank_kms(struct drm_crtc *crtc)
838 {
839 struct drm_device *dev = crtc->dev;
840 unsigned int pipe = crtc->index;
841 struct radeon_device *rdev = dev->dev_private;
842 unsigned long irqflags;
843 int r;
844
845 if (pipe >= rdev->num_crtc) {
846 DRM_ERROR("Invalid crtc %d\n", pipe);
847 return -EINVAL;
848 }
849
850 spin_lock_irqsave(&rdev->irq.lock, irqflags);
851 rdev->irq.crtc_vblank_int[pipe] = true;
852 r = radeon_irq_set(rdev);
853 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
854 return r;
855 }
856
857 /**
858 * radeon_disable_vblank_kms - disable vblank interrupt
859 *
860 * @crtc: crtc to disable vblank interrupt for
861 *
862 * Disable the interrupt on the requested crtc (all asics).
863 */
radeon_disable_vblank_kms(struct drm_crtc * crtc)864 void radeon_disable_vblank_kms(struct drm_crtc *crtc)
865 {
866 struct drm_device *dev = crtc->dev;
867 unsigned int pipe = crtc->index;
868 struct radeon_device *rdev = dev->dev_private;
869 unsigned long irqflags;
870
871 if (pipe >= rdev->num_crtc) {
872 DRM_ERROR("Invalid crtc %d\n", pipe);
873 return;
874 }
875
876 spin_lock_irqsave(&rdev->irq.lock, irqflags);
877 rdev->irq.crtc_vblank_int[pipe] = false;
878 radeon_irq_set(rdev);
879 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
880 }
881