1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23
24 #include <linux/hwmon-sysfs.h>
25 #include <linux/hwmon.h>
26 #include <linux/pci.h>
27 #include <linux/power_supply.h>
28
29 #include <drm/drm_vblank.h>
30
31 #include "atom.h"
32 #include "avivod.h"
33 #include "r600_dpm.h"
34 #include "radeon.h"
35 #include "radeon_pm.h"
36
37 #define RADEON_IDLE_LOOP_MS 100
38 #define RADEON_RECLOCK_DELAY_MS 200
39 #define RADEON_WAIT_VBLANK_TIMEOUT 200
40
41 static const char *radeon_pm_state_type_name[5] = {
42 "",
43 "Powersave",
44 "Battery",
45 "Balanced",
46 "Performance",
47 };
48
49 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
50 static void radeon_debugfs_pm_init(struct radeon_device *rdev);
51 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
52 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
53 static void radeon_pm_update_profile(struct radeon_device *rdev);
54 static void radeon_pm_set_clocks(struct radeon_device *rdev);
55
radeon_pm_get_type_index(struct radeon_device * rdev,enum radeon_pm_state_type ps_type,int instance)56 int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
58 int instance)
59 {
60 int i;
61 int found_instance = -1;
62
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
65 found_instance++;
66 if (found_instance == instance)
67 return i;
68 }
69 }
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
72 }
73
radeon_pm_acpi_event_handler(struct radeon_device * rdev)74 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
75 {
76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
77 mutex_lock(&rdev->pm.mutex);
78 if (power_supply_is_system_supplied() > 0)
79 rdev->pm.dpm.ac_power = true;
80 else
81 rdev->pm.dpm.ac_power = false;
82 if (rdev->family == CHIP_ARUBA) {
83 if (rdev->asic->dpm.enable_bapm)
84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
85 }
86 mutex_unlock(&rdev->pm.mutex);
87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
88 if (rdev->pm.profile == PM_PROFILE_AUTO) {
89 mutex_lock(&rdev->pm.mutex);
90 radeon_pm_update_profile(rdev);
91 radeon_pm_set_clocks(rdev);
92 mutex_unlock(&rdev->pm.mutex);
93 }
94 }
95 }
96
radeon_pm_update_profile(struct radeon_device * rdev)97 static void radeon_pm_update_profile(struct radeon_device *rdev)
98 {
99 switch (rdev->pm.profile) {
100 case PM_PROFILE_DEFAULT:
101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
102 break;
103 case PM_PROFILE_AUTO:
104 if (power_supply_is_system_supplied() > 0) {
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
107 else
108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
109 } else {
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
112 else
113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
114 }
115 break;
116 case PM_PROFILE_LOW:
117 if (rdev->pm.active_crtc_count > 1)
118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
119 else
120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
121 break;
122 case PM_PROFILE_MID:
123 if (rdev->pm.active_crtc_count > 1)
124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
125 else
126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
127 break;
128 case PM_PROFILE_HIGH:
129 if (rdev->pm.active_crtc_count > 1)
130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
131 else
132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
133 break;
134 }
135
136 if (rdev->pm.active_crtc_count == 0) {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
141 } else {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
146 }
147 }
148
radeon_unmap_vram_bos(struct radeon_device * rdev)149 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
150 {
151 struct radeon_bo *bo, *n;
152
153 if (list_empty(&rdev->gem.objects))
154 return;
155
156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
157 if (bo->tbo.resource->mem_type == TTM_PL_VRAM)
158 ttm_bo_unmap_virtual(&bo->tbo);
159 }
160 }
161
radeon_sync_with_vblank(struct radeon_device * rdev)162 static void radeon_sync_with_vblank(struct radeon_device *rdev)
163 {
164 if (rdev->pm.active_crtcs) {
165 rdev->pm.vblank_sync = false;
166 wait_event_timeout(
167 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
168 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
169 }
170 }
171
radeon_set_power_state(struct radeon_device * rdev)172 static void radeon_set_power_state(struct radeon_device *rdev)
173 {
174 u32 sclk, mclk;
175 bool misc_after = false;
176
177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
179 return;
180
181 if (radeon_gui_idle(rdev)) {
182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].sclk;
184 if (sclk > rdev->pm.default_sclk)
185 sclk = rdev->pm.default_sclk;
186
187 /* starting with BTC, there is one state that is used for both
188 * MH and SH. Difference is that we always use the high clock index for
189 * mclk and vddci.
190 */
191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
192 (rdev->family >= CHIP_BARTS) &&
193 rdev->pm.active_crtc_count &&
194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
198 else
199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 clock_info[rdev->pm.requested_clock_mode_index].mclk;
201
202 if (mclk > rdev->pm.default_mclk)
203 mclk = rdev->pm.default_mclk;
204
205 /* upvolt before raising clocks, downvolt after lowering clocks */
206 if (sclk < rdev->pm.current_sclk)
207 misc_after = true;
208
209 radeon_sync_with_vblank(rdev);
210
211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
212 if (!radeon_pm_in_vbl(rdev))
213 return;
214 }
215
216 radeon_pm_prepare(rdev);
217
218 if (!misc_after)
219 /* voltage, pcie lanes, etc.*/
220 radeon_pm_misc(rdev);
221
222 /* set engine clock */
223 if (sclk != rdev->pm.current_sclk) {
224 radeon_pm_debug_check_in_vbl(rdev, false);
225 radeon_set_engine_clock(rdev, sclk);
226 radeon_pm_debug_check_in_vbl(rdev, true);
227 rdev->pm.current_sclk = sclk;
228 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
229 }
230
231 /* set memory clock */
232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
233 radeon_pm_debug_check_in_vbl(rdev, false);
234 radeon_set_memory_clock(rdev, mclk);
235 radeon_pm_debug_check_in_vbl(rdev, true);
236 rdev->pm.current_mclk = mclk;
237 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
238 }
239
240 if (misc_after)
241 /* voltage, pcie lanes, etc.*/
242 radeon_pm_misc(rdev);
243
244 radeon_pm_finish(rdev);
245
246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
248 } else
249 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
250 }
251
radeon_pm_set_clocks(struct radeon_device * rdev)252 static void radeon_pm_set_clocks(struct radeon_device *rdev)
253 {
254 struct drm_crtc *crtc;
255 int i, r;
256
257 /* no need to take locks, etc. if nothing's going to change */
258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
260 return;
261
262 down_write(&rdev->pm.mclk_lock);
263 mutex_lock(&rdev->ring_lock);
264
265 /* wait for the rings to drain */
266 for (i = 0; i < RADEON_NUM_RINGS; i++) {
267 struct radeon_ring *ring = &rdev->ring[i];
268 if (!ring->ready) {
269 continue;
270 }
271 r = radeon_fence_wait_empty(rdev, i);
272 if (r) {
273 /* needs a GPU reset dont reset here */
274 mutex_unlock(&rdev->ring_lock);
275 up_write(&rdev->pm.mclk_lock);
276 return;
277 }
278 }
279
280 radeon_unmap_vram_bos(rdev);
281
282 if (rdev->irq.installed) {
283 i = 0;
284 drm_for_each_crtc(crtc, rdev_to_drm(rdev)) {
285 if (rdev->pm.active_crtcs & (1 << i)) {
286 /* This can fail if a modeset is in progress */
287 if (drm_crtc_vblank_get(crtc) == 0)
288 rdev->pm.req_vblank |= (1 << i);
289 else
290 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
291 i);
292 }
293 i++;
294 }
295 }
296
297 radeon_set_power_state(rdev);
298
299 if (rdev->irq.installed) {
300 i = 0;
301 drm_for_each_crtc(crtc, rdev_to_drm(rdev)) {
302 if (rdev->pm.req_vblank & (1 << i)) {
303 rdev->pm.req_vblank &= ~(1 << i);
304 drm_crtc_vblank_put(crtc);
305 }
306 i++;
307 }
308 }
309
310 /* update display watermarks based on new power state */
311 radeon_update_bandwidth_info(rdev);
312 if (rdev->pm.active_crtc_count)
313 radeon_bandwidth_update(rdev);
314
315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
316
317 mutex_unlock(&rdev->ring_lock);
318 up_write(&rdev->pm.mclk_lock);
319 }
320
radeon_pm_print_states(struct radeon_device * rdev)321 static void radeon_pm_print_states(struct radeon_device *rdev)
322 {
323 int i, j;
324 struct radeon_power_state *power_state;
325 struct radeon_pm_clock_info *clock_info;
326
327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
328 for (i = 0; i < rdev->pm.num_power_states; i++) {
329 power_state = &rdev->pm.power_state[i];
330 DRM_DEBUG_DRIVER("State %d: %s\n", i,
331 radeon_pm_state_type_name[power_state->type]);
332 if (i == rdev->pm.default_power_state_index)
333 DRM_DEBUG_DRIVER("\tDefault");
334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
335 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
336 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
337 DRM_DEBUG_DRIVER("\tSingle display only\n");
338 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
339 for (j = 0; j < power_state->num_clock_modes; j++) {
340 clock_info = &(power_state->clock_info[j]);
341 if (rdev->flags & RADEON_IS_IGP)
342 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
343 j,
344 clock_info->sclk * 10);
345 else
346 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
347 j,
348 clock_info->sclk * 10,
349 clock_info->mclk * 10,
350 clock_info->voltage.voltage);
351 }
352 }
353 }
354
355 #ifdef notyet
radeon_get_pm_profile(struct device * dev,struct device_attribute * attr,char * buf)356 static ssize_t radeon_get_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 char *buf)
359 {
360 struct drm_device *ddev = dev_get_drvdata(dev);
361 struct radeon_device *rdev = ddev->dev_private;
362 int cp = rdev->pm.profile;
363
364 return sysfs_emit(buf, "%s\n", (cp == PM_PROFILE_AUTO) ? "auto" :
365 (cp == PM_PROFILE_LOW) ? "low" :
366 (cp == PM_PROFILE_MID) ? "mid" :
367 (cp == PM_PROFILE_HIGH) ? "high" : "default");
368 }
369
radeon_set_pm_profile(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)370 static ssize_t radeon_set_pm_profile(struct device *dev,
371 struct device_attribute *attr,
372 const char *buf,
373 size_t count)
374 {
375 struct drm_device *ddev = dev_get_drvdata(dev);
376 struct radeon_device *rdev = ddev->dev_private;
377
378 /* Can't set profile when the card is off */
379 #ifdef notyet
380 if ((rdev->flags & RADEON_IS_PX) &&
381 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
382 return -EINVAL;
383 #endif
384
385 mutex_lock(&rdev->pm.mutex);
386 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
387 if (strncmp("default", buf, strlen("default")) == 0)
388 rdev->pm.profile = PM_PROFILE_DEFAULT;
389 else if (strncmp("auto", buf, strlen("auto")) == 0)
390 rdev->pm.profile = PM_PROFILE_AUTO;
391 else if (strncmp("low", buf, strlen("low")) == 0)
392 rdev->pm.profile = PM_PROFILE_LOW;
393 else if (strncmp("mid", buf, strlen("mid")) == 0)
394 rdev->pm.profile = PM_PROFILE_MID;
395 else if (strncmp("high", buf, strlen("high")) == 0)
396 rdev->pm.profile = PM_PROFILE_HIGH;
397 else {
398 count = -EINVAL;
399 goto fail;
400 }
401 radeon_pm_update_profile(rdev);
402 radeon_pm_set_clocks(rdev);
403 } else
404 count = -EINVAL;
405
406 fail:
407 mutex_unlock(&rdev->pm.mutex);
408
409 return count;
410 }
411
radeon_get_pm_method(struct device * dev,struct device_attribute * attr,char * buf)412 static ssize_t radeon_get_pm_method(struct device *dev,
413 struct device_attribute *attr,
414 char *buf)
415 {
416 struct drm_device *ddev = dev_get_drvdata(dev);
417 struct radeon_device *rdev = ddev->dev_private;
418 int pm = rdev->pm.pm_method;
419
420 return sysfs_emit(buf, "%s\n", (pm == PM_METHOD_DYNPM) ? "dynpm" :
421 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
422 }
423
radeon_set_pm_method(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)424 static ssize_t radeon_set_pm_method(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf,
427 size_t count)
428 {
429 struct drm_device *ddev = dev_get_drvdata(dev);
430 struct radeon_device *rdev = ddev->dev_private;
431
432 #ifdef notyet
433 /* Can't set method when the card is off */
434 if ((rdev->flags & RADEON_IS_PX) &&
435 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
436 count = -EINVAL;
437 goto fail;
438 }
439 #endif
440
441 /* we don't support the legacy modes with dpm */
442 if (rdev->pm.pm_method == PM_METHOD_DPM) {
443 count = -EINVAL;
444 goto fail;
445 }
446
447 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
448 mutex_lock(&rdev->pm.mutex);
449 rdev->pm.pm_method = PM_METHOD_DYNPM;
450 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
451 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
452 mutex_unlock(&rdev->pm.mutex);
453 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
454 mutex_lock(&rdev->pm.mutex);
455 /* disable dynpm */
456 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
457 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
458 rdev->pm.pm_method = PM_METHOD_PROFILE;
459 mutex_unlock(&rdev->pm.mutex);
460 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
461 } else {
462 count = -EINVAL;
463 goto fail;
464 }
465 radeon_pm_compute_clocks(rdev);
466 fail:
467 return count;
468 }
469
radeon_get_dpm_state(struct device * dev,struct device_attribute * attr,char * buf)470 static ssize_t radeon_get_dpm_state(struct device *dev,
471 struct device_attribute *attr,
472 char *buf)
473 {
474 struct drm_device *ddev = dev_get_drvdata(dev);
475 struct radeon_device *rdev = ddev->dev_private;
476 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
477
478 return sysfs_emit(buf, "%s\n",
479 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
480 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
481 }
482
radeon_set_dpm_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)483 static ssize_t radeon_set_dpm_state(struct device *dev,
484 struct device_attribute *attr,
485 const char *buf,
486 size_t count)
487 {
488 struct drm_device *ddev = dev_get_drvdata(dev);
489 struct radeon_device *rdev = ddev->dev_private;
490
491 mutex_lock(&rdev->pm.mutex);
492 if (strncmp("battery", buf, strlen("battery")) == 0)
493 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
494 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
495 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
496 else if (strncmp("performance", buf, strlen("performance")) == 0)
497 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
498 else {
499 mutex_unlock(&rdev->pm.mutex);
500 count = -EINVAL;
501 goto fail;
502 }
503 mutex_unlock(&rdev->pm.mutex);
504
505 /* Can't set dpm state when the card is off */
506 #ifdef notyet
507 if (!(rdev->flags & RADEON_IS_PX) ||
508 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
509 #endif
510 radeon_pm_compute_clocks(rdev);
511
512 fail:
513 return count;
514 }
515
radeon_get_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,char * buf)516 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
517 struct device_attribute *attr,
518 char *buf)
519 {
520 struct drm_device *ddev = dev_get_drvdata(dev);
521 struct radeon_device *rdev = ddev->dev_private;
522 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
523
524 #ifdef notyet
525 if ((rdev->flags & RADEON_IS_PX) &&
526 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
527 return sysfs_emit(buf, "off\n");
528 #endif
529
530 return sysfs_emit(buf, "%s\n",
531 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
532 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
533 }
534
radeon_set_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)535 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
536 struct device_attribute *attr,
537 const char *buf,
538 size_t count)
539 {
540 struct drm_device *ddev = dev_get_drvdata(dev);
541 struct radeon_device *rdev = ddev->dev_private;
542 enum radeon_dpm_forced_level level;
543 int ret = 0;
544
545 /* Can't force performance level when the card is off */
546 #ifdef notyet
547 if ((rdev->flags & RADEON_IS_PX) &&
548 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
549 return -EINVAL;
550 #endif
551
552 mutex_lock(&rdev->pm.mutex);
553 if (strncmp("low", buf, strlen("low")) == 0) {
554 level = RADEON_DPM_FORCED_LEVEL_LOW;
555 } else if (strncmp("high", buf, strlen("high")) == 0) {
556 level = RADEON_DPM_FORCED_LEVEL_HIGH;
557 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
558 level = RADEON_DPM_FORCED_LEVEL_AUTO;
559 } else {
560 count = -EINVAL;
561 goto fail;
562 }
563 if (rdev->asic->dpm.force_performance_level) {
564 if (rdev->pm.dpm.thermal_active) {
565 count = -EINVAL;
566 goto fail;
567 }
568 ret = radeon_dpm_force_performance_level(rdev, level);
569 if (ret)
570 count = -EINVAL;
571 }
572 fail:
573 mutex_unlock(&rdev->pm.mutex);
574
575 return count;
576 }
577 #endif
578
579 #ifdef notyet
radeon_hwmon_get_pwm1_enable(struct device * dev,struct device_attribute * attr,char * buf)580 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
581 struct device_attribute *attr,
582 char *buf)
583 {
584 struct radeon_device *rdev = dev_get_drvdata(dev);
585 u32 pwm_mode = 0;
586
587 if (rdev->asic->dpm.fan_ctrl_get_mode)
588 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
589
590 /* never 0 (full-speed), fuse or smc-controlled always */
591 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
592 }
593
radeon_hwmon_set_pwm1_enable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)594 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
595 struct device_attribute *attr,
596 const char *buf,
597 size_t count)
598 {
599 struct radeon_device *rdev = dev_get_drvdata(dev);
600 int err;
601 int value;
602
603 if(!rdev->asic->dpm.fan_ctrl_set_mode)
604 return -EINVAL;
605
606 err = kstrtoint(buf, 10, &value);
607 if (err)
608 return err;
609
610 switch (value) {
611 case 1: /* manual, percent-based */
612 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
613 break;
614 default: /* disable */
615 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
616 break;
617 }
618
619 return count;
620 }
621
radeon_hwmon_get_pwm1_min(struct device * dev,struct device_attribute * attr,char * buf)622 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
623 struct device_attribute *attr,
624 char *buf)
625 {
626 return sprintf(buf, "%i\n", 0);
627 }
628
radeon_hwmon_get_pwm1_max(struct device * dev,struct device_attribute * attr,char * buf)629 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
630 struct device_attribute *attr,
631 char *buf)
632 {
633 return sprintf(buf, "%i\n", 255);
634 }
635
radeon_hwmon_set_pwm1(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)636 static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
637 struct device_attribute *attr,
638 const char *buf, size_t count)
639 {
640 struct radeon_device *rdev = dev_get_drvdata(dev);
641 int err;
642 u32 value;
643
644 err = kstrtou32(buf, 10, &value);
645 if (err)
646 return err;
647
648 value = (value * 100) / 255;
649
650 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
651 if (err)
652 return err;
653
654 return count;
655 }
656
radeon_hwmon_get_pwm1(struct device * dev,struct device_attribute * attr,char * buf)657 static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
658 struct device_attribute *attr,
659 char *buf)
660 {
661 struct radeon_device *rdev = dev_get_drvdata(dev);
662 int err;
663 u32 speed;
664
665 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
666 if (err)
667 return err;
668
669 speed = (speed * 255) / 100;
670
671 return sprintf(buf, "%i\n", speed);
672 }
673
674 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
675 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
676 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
677 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
678 radeon_get_dpm_forced_performance_level,
679 radeon_set_dpm_forced_performance_level);
680
radeon_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)681 static ssize_t radeon_hwmon_show_temp(struct device *dev,
682 struct device_attribute *attr,
683 char *buf)
684 {
685 struct radeon_device *rdev = dev_get_drvdata(dev);
686 struct drm_device *ddev = rdev_to_drm(rdev);
687 int temp;
688
689 /* Can't get temperature when the card is off */
690 if ((rdev->flags & RADEON_IS_PX) &&
691 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
692 return -EINVAL;
693
694 if (rdev->asic->pm.get_temperature)
695 temp = radeon_get_temperature(rdev);
696 else
697 temp = 0;
698
699 return sysfs_emit(buf, "%d\n", temp);
700 }
701
radeon_hwmon_show_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)702 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
703 struct device_attribute *attr,
704 char *buf)
705 {
706 struct radeon_device *rdev = dev_get_drvdata(dev);
707 int hyst = to_sensor_dev_attr(attr)->index;
708 int temp;
709
710 if (hyst)
711 temp = rdev->pm.dpm.thermal.min_temp;
712 else
713 temp = rdev->pm.dpm.thermal.max_temp;
714
715 return sysfs_emit(buf, "%d\n", temp);
716 }
717
718 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
719 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
720 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
721 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
722 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
723 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
724 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
725
radeon_hwmon_show_sclk(struct device * dev,struct device_attribute * attr,char * buf)726 static ssize_t radeon_hwmon_show_sclk(struct device *dev,
727 struct device_attribute *attr, char *buf)
728 {
729 struct radeon_device *rdev = dev_get_drvdata(dev);
730 struct drm_device *ddev = rdev_to_drm(rdev);
731 u32 sclk = 0;
732
733 /* Can't get clock frequency when the card is off */
734 if ((rdev->flags & RADEON_IS_PX) &&
735 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
736 return -EINVAL;
737
738 if (rdev->asic->dpm.get_current_sclk)
739 sclk = radeon_dpm_get_current_sclk(rdev);
740
741 /* Value returned by dpm is in 10 KHz units, need to convert it into Hz
742 for hwmon */
743 sclk *= 10000;
744
745 return sysfs_emit(buf, "%u\n", sclk);
746 }
747
748 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL,
749 0);
750
radeon_hwmon_show_vddc(struct device * dev,struct device_attribute * attr,char * buf)751 static ssize_t radeon_hwmon_show_vddc(struct device *dev,
752 struct device_attribute *attr, char *buf)
753 {
754 struct radeon_device *rdev = dev_get_drvdata(dev);
755 struct drm_device *ddev = rdev_to_drm(rdev);
756 u16 vddc = 0;
757
758 /* Can't get vddc when the card is off */
759 if ((rdev->flags & RADEON_IS_PX) &&
760 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
761 return -EINVAL;
762
763 if (rdev->asic->dpm.get_current_vddc)
764 vddc = rdev->asic->dpm.get_current_vddc(rdev);
765
766 return sysfs_emit(buf, "%u\n", vddc);
767 }
768
769 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL,
770 0);
771
772 static struct attribute *hwmon_attributes[] = {
773 &sensor_dev_attr_temp1_input.dev_attr.attr,
774 &sensor_dev_attr_temp1_crit.dev_attr.attr,
775 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
776 &sensor_dev_attr_pwm1.dev_attr.attr,
777 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
778 &sensor_dev_attr_pwm1_min.dev_attr.attr,
779 &sensor_dev_attr_pwm1_max.dev_attr.attr,
780 &sensor_dev_attr_freq1_input.dev_attr.attr,
781 &sensor_dev_attr_in0_input.dev_attr.attr,
782 NULL
783 };
784
hwmon_attributes_visible(struct kobject * kobj,struct attribute * attr,int index)785 static umode_t hwmon_attributes_visible(struct kobject *kobj,
786 struct attribute *attr, int index)
787 {
788 struct device *dev = kobj_to_dev(kobj);
789 struct radeon_device *rdev = dev_get_drvdata(dev);
790 umode_t effective_mode = attr->mode;
791
792 /* Skip attributes if DPM is not enabled */
793 if (rdev->pm.pm_method != PM_METHOD_DPM &&
794 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
795 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
796 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
797 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
798 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
799 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
800 attr == &sensor_dev_attr_freq1_input.dev_attr.attr ||
801 attr == &sensor_dev_attr_in0_input.dev_attr.attr))
802 return 0;
803
804 /* Skip vddc attribute if get_current_vddc is not implemented */
805 if(attr == &sensor_dev_attr_in0_input.dev_attr.attr &&
806 !rdev->asic->dpm.get_current_vddc)
807 return 0;
808
809 /* Skip fan attributes if fan is not present */
810 if (rdev->pm.no_fan &&
811 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
812 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
813 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
814 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
815 return 0;
816
817 /* mask fan attributes if we have no bindings for this asic to expose */
818 if ((!rdev->asic->dpm.get_fan_speed_percent &&
819 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
820 (!rdev->asic->dpm.fan_ctrl_get_mode &&
821 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
822 effective_mode &= ~S_IRUGO;
823
824 if ((!rdev->asic->dpm.set_fan_speed_percent &&
825 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
826 (!rdev->asic->dpm.fan_ctrl_set_mode &&
827 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
828 effective_mode &= ~S_IWUSR;
829
830 /* hide max/min values if we can't both query and manage the fan */
831 if ((!rdev->asic->dpm.set_fan_speed_percent &&
832 !rdev->asic->dpm.get_fan_speed_percent) &&
833 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
834 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
835 return 0;
836
837 return effective_mode;
838 }
839
840 static const struct attribute_group hwmon_attrgroup = {
841 .attrs = hwmon_attributes,
842 .is_visible = hwmon_attributes_visible,
843 };
844
845 static const struct attribute_group *hwmon_groups[] = {
846 &hwmon_attrgroup,
847 NULL
848 };
849 #endif
850
radeon_hwmon_init(struct radeon_device * rdev)851 static int radeon_hwmon_init(struct radeon_device *rdev)
852 {
853 int err = 0;
854
855 switch (rdev->pm.int_thermal_type) {
856 case THERMAL_TYPE_RV6XX:
857 case THERMAL_TYPE_RV770:
858 case THERMAL_TYPE_EVERGREEN:
859 case THERMAL_TYPE_NI:
860 case THERMAL_TYPE_SUMO:
861 case THERMAL_TYPE_SI:
862 case THERMAL_TYPE_CI:
863 case THERMAL_TYPE_KV:
864 if (rdev->asic->pm.get_temperature == NULL)
865 return err;
866 #ifdef notyet
867 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
868 "radeon", rdev,
869 hwmon_groups);
870 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
871 err = PTR_ERR(rdev->pm.int_hwmon_dev);
872 dev_err(rdev->dev,
873 "Unable to register hwmon device: %d\n", err);
874 }
875 #endif
876 break;
877 default:
878 break;
879 }
880
881 return err;
882 }
883
radeon_hwmon_fini(struct radeon_device * rdev)884 static void radeon_hwmon_fini(struct radeon_device *rdev)
885 {
886 #ifdef notyet
887 if (rdev->pm.int_hwmon_dev)
888 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
889 #endif
890 }
891
radeon_dpm_thermal_work_handler(struct work_struct * work)892 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
893 {
894 struct radeon_device *rdev =
895 container_of(work, struct radeon_device,
896 pm.dpm.thermal.work);
897 /* switch to the thermal state */
898 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
899
900 if (!rdev->pm.dpm_enabled)
901 return;
902
903 if (rdev->asic->pm.get_temperature) {
904 int temp = radeon_get_temperature(rdev);
905
906 if (temp < rdev->pm.dpm.thermal.min_temp)
907 /* switch back the user state */
908 dpm_state = rdev->pm.dpm.user_state;
909 } else {
910 if (rdev->pm.dpm.thermal.high_to_low)
911 /* switch back the user state */
912 dpm_state = rdev->pm.dpm.user_state;
913 }
914 mutex_lock(&rdev->pm.mutex);
915 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
916 rdev->pm.dpm.thermal_active = true;
917 else
918 rdev->pm.dpm.thermal_active = false;
919 rdev->pm.dpm.state = dpm_state;
920 mutex_unlock(&rdev->pm.mutex);
921
922 radeon_pm_compute_clocks(rdev);
923 }
924
radeon_dpm_single_display(struct radeon_device * rdev)925 static bool radeon_dpm_single_display(struct radeon_device *rdev)
926 {
927 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
928 true : false;
929
930 /* check if the vblank period is too short to adjust the mclk */
931 if (single_display && rdev->asic->dpm.vblank_too_short) {
932 if (radeon_dpm_vblank_too_short(rdev))
933 single_display = false;
934 }
935
936 /* 120hz tends to be problematic even if they are under the
937 * vblank limit.
938 */
939 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
940 single_display = false;
941
942 return single_display;
943 }
944
radeon_dpm_pick_power_state(struct radeon_device * rdev,enum radeon_pm_state_type dpm_state)945 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
946 enum radeon_pm_state_type dpm_state)
947 {
948 int i;
949 struct radeon_ps *ps;
950 u32 ui_class;
951 bool single_display = radeon_dpm_single_display(rdev);
952
953 /* certain older asics have a separare 3D performance state,
954 * so try that first if the user selected performance
955 */
956 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
957 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
958 /* balanced states don't exist at the moment */
959 if (dpm_state == POWER_STATE_TYPE_BALANCED)
960 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
961
962 restart_search:
963 /* Pick the best power state based on current conditions */
964 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
965 ps = &rdev->pm.dpm.ps[i];
966 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
967 switch (dpm_state) {
968 /* user states */
969 case POWER_STATE_TYPE_BATTERY:
970 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
971 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
972 if (single_display)
973 return ps;
974 } else
975 return ps;
976 }
977 break;
978 case POWER_STATE_TYPE_BALANCED:
979 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
980 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
981 if (single_display)
982 return ps;
983 } else
984 return ps;
985 }
986 break;
987 case POWER_STATE_TYPE_PERFORMANCE:
988 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
989 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
990 if (single_display)
991 return ps;
992 } else
993 return ps;
994 }
995 break;
996 /* internal states */
997 case POWER_STATE_TYPE_INTERNAL_UVD:
998 if (rdev->pm.dpm.uvd_ps)
999 return rdev->pm.dpm.uvd_ps;
1000 else
1001 break;
1002 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1003 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1004 return ps;
1005 break;
1006 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1007 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1008 return ps;
1009 break;
1010 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1011 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1012 return ps;
1013 break;
1014 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1015 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1016 return ps;
1017 break;
1018 case POWER_STATE_TYPE_INTERNAL_BOOT:
1019 return rdev->pm.dpm.boot_ps;
1020 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1021 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1022 return ps;
1023 break;
1024 case POWER_STATE_TYPE_INTERNAL_ACPI:
1025 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1026 return ps;
1027 break;
1028 case POWER_STATE_TYPE_INTERNAL_ULV:
1029 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1030 return ps;
1031 break;
1032 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1033 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1034 return ps;
1035 break;
1036 default:
1037 break;
1038 }
1039 }
1040 /* use a fallback state if we didn't match */
1041 switch (dpm_state) {
1042 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1043 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1044 goto restart_search;
1045 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1046 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1047 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1048 if (rdev->pm.dpm.uvd_ps) {
1049 return rdev->pm.dpm.uvd_ps;
1050 } else {
1051 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1052 goto restart_search;
1053 }
1054 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1055 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1056 goto restart_search;
1057 case POWER_STATE_TYPE_INTERNAL_ACPI:
1058 dpm_state = POWER_STATE_TYPE_BATTERY;
1059 goto restart_search;
1060 case POWER_STATE_TYPE_BATTERY:
1061 case POWER_STATE_TYPE_BALANCED:
1062 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1063 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1064 goto restart_search;
1065 default:
1066 break;
1067 }
1068
1069 return NULL;
1070 }
1071
radeon_dpm_change_power_state_locked(struct radeon_device * rdev)1072 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
1073 {
1074 int i;
1075 struct radeon_ps *ps;
1076 enum radeon_pm_state_type dpm_state;
1077 int ret;
1078 bool single_display = radeon_dpm_single_display(rdev);
1079
1080 /* if dpm init failed */
1081 if (!rdev->pm.dpm_enabled)
1082 return;
1083
1084 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1085 /* add other state override checks here */
1086 if ((!rdev->pm.dpm.thermal_active) &&
1087 (!rdev->pm.dpm.uvd_active))
1088 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1089 }
1090 dpm_state = rdev->pm.dpm.state;
1091
1092 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1093 if (ps)
1094 rdev->pm.dpm.requested_ps = ps;
1095 else
1096 return;
1097
1098 /* no need to reprogram if nothing changed unless we are on BTC+ */
1099 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1100 /* vce just modifies an existing state so force a change */
1101 if (ps->vce_active != rdev->pm.dpm.vce_active)
1102 goto force;
1103 /* user has made a display change (such as timing) */
1104 if (rdev->pm.dpm.single_display != single_display)
1105 goto force;
1106 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1107 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1108 * all we need to do is update the display configuration.
1109 */
1110 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1111 /* update display watermarks based on new power state */
1112 radeon_bandwidth_update(rdev);
1113 /* update displays */
1114 radeon_dpm_display_configuration_changed(rdev);
1115 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1116 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1117 }
1118 return;
1119 } else {
1120 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1121 * nothing to do, if the num crtcs is > 1 and state is the same,
1122 * update display configuration.
1123 */
1124 if (rdev->pm.dpm.new_active_crtcs ==
1125 rdev->pm.dpm.current_active_crtcs) {
1126 return;
1127 } else {
1128 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1129 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1130 /* update display watermarks based on new power state */
1131 radeon_bandwidth_update(rdev);
1132 /* update displays */
1133 radeon_dpm_display_configuration_changed(rdev);
1134 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1135 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1136 return;
1137 }
1138 }
1139 }
1140 }
1141
1142 force:
1143 if (radeon_dpm == 1) {
1144 printk("switching from power state:\n");
1145 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1146 printk("switching to power state:\n");
1147 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1148 }
1149
1150 down_write(&rdev->pm.mclk_lock);
1151 mutex_lock(&rdev->ring_lock);
1152
1153 /* update whether vce is active */
1154 ps->vce_active = rdev->pm.dpm.vce_active;
1155
1156 ret = radeon_dpm_pre_set_power_state(rdev);
1157 if (ret)
1158 goto done;
1159
1160 /* update display watermarks based on new power state */
1161 radeon_bandwidth_update(rdev);
1162 /* update displays */
1163 radeon_dpm_display_configuration_changed(rdev);
1164
1165 /* wait for the rings to drain */
1166 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1167 struct radeon_ring *ring = &rdev->ring[i];
1168 if (ring->ready)
1169 radeon_fence_wait_empty(rdev, i);
1170 }
1171
1172 /* program the new power state */
1173 radeon_dpm_set_power_state(rdev);
1174
1175 /* update current power state */
1176 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1177
1178 radeon_dpm_post_set_power_state(rdev);
1179
1180 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1181 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1182 rdev->pm.dpm.single_display = single_display;
1183
1184 if (rdev->asic->dpm.force_performance_level) {
1185 if (rdev->pm.dpm.thermal_active) {
1186 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1187 /* force low perf level for thermal */
1188 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1189 /* save the user's level */
1190 rdev->pm.dpm.forced_level = level;
1191 } else {
1192 /* otherwise, user selected level */
1193 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1194 }
1195 }
1196
1197 done:
1198 mutex_unlock(&rdev->ring_lock);
1199 up_write(&rdev->pm.mclk_lock);
1200 }
1201
radeon_dpm_enable_uvd(struct radeon_device * rdev,bool enable)1202 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1203 {
1204 enum radeon_pm_state_type dpm_state;
1205
1206 if (rdev->asic->dpm.powergate_uvd) {
1207 mutex_lock(&rdev->pm.mutex);
1208 /* don't powergate anything if we
1209 have active but pause streams */
1210 enable |= rdev->pm.dpm.sd > 0;
1211 enable |= rdev->pm.dpm.hd > 0;
1212 /* enable/disable UVD */
1213 radeon_dpm_powergate_uvd(rdev, !enable);
1214 mutex_unlock(&rdev->pm.mutex);
1215 } else {
1216 if (enable) {
1217 mutex_lock(&rdev->pm.mutex);
1218 rdev->pm.dpm.uvd_active = true;
1219 /* disable this for now */
1220 #if 0
1221 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1222 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1223 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1224 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1225 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1226 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1227 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1228 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1229 else
1230 #endif
1231 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1232 rdev->pm.dpm.state = dpm_state;
1233 mutex_unlock(&rdev->pm.mutex);
1234 } else {
1235 mutex_lock(&rdev->pm.mutex);
1236 rdev->pm.dpm.uvd_active = false;
1237 mutex_unlock(&rdev->pm.mutex);
1238 }
1239
1240 radeon_pm_compute_clocks(rdev);
1241 }
1242 }
1243
radeon_dpm_enable_vce(struct radeon_device * rdev,bool enable)1244 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1245 {
1246 if (enable) {
1247 mutex_lock(&rdev->pm.mutex);
1248 rdev->pm.dpm.vce_active = true;
1249 /* XXX select vce level based on ring/task */
1250 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1251 mutex_unlock(&rdev->pm.mutex);
1252 } else {
1253 mutex_lock(&rdev->pm.mutex);
1254 rdev->pm.dpm.vce_active = false;
1255 mutex_unlock(&rdev->pm.mutex);
1256 }
1257
1258 radeon_pm_compute_clocks(rdev);
1259 }
1260
radeon_pm_suspend_old(struct radeon_device * rdev)1261 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1262 {
1263 mutex_lock(&rdev->pm.mutex);
1264 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1265 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1266 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1267 }
1268 mutex_unlock(&rdev->pm.mutex);
1269
1270 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1271 }
1272
radeon_pm_suspend_dpm(struct radeon_device * rdev)1273 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1274 {
1275 mutex_lock(&rdev->pm.mutex);
1276 /* disable dpm */
1277 radeon_dpm_disable(rdev);
1278 /* reset the power state */
1279 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1280 rdev->pm.dpm_enabled = false;
1281 mutex_unlock(&rdev->pm.mutex);
1282 }
1283
radeon_pm_suspend(struct radeon_device * rdev)1284 void radeon_pm_suspend(struct radeon_device *rdev)
1285 {
1286 if (rdev->pm.pm_method == PM_METHOD_DPM)
1287 radeon_pm_suspend_dpm(rdev);
1288 else
1289 radeon_pm_suspend_old(rdev);
1290 }
1291
radeon_pm_resume_old(struct radeon_device * rdev)1292 static void radeon_pm_resume_old(struct radeon_device *rdev)
1293 {
1294 /* set up the default clocks if the MC ucode is loaded */
1295 if ((rdev->family >= CHIP_BARTS) &&
1296 (rdev->family <= CHIP_CAYMAN) &&
1297 rdev->mc_fw) {
1298 if (rdev->pm.default_vddc)
1299 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1300 SET_VOLTAGE_TYPE_ASIC_VDDC);
1301 if (rdev->pm.default_vddci)
1302 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1303 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1304 if (rdev->pm.default_sclk)
1305 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1306 if (rdev->pm.default_mclk)
1307 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1308 }
1309 /* asic init will reset the default power state */
1310 mutex_lock(&rdev->pm.mutex);
1311 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1312 rdev->pm.current_clock_mode_index = 0;
1313 rdev->pm.current_sclk = rdev->pm.default_sclk;
1314 rdev->pm.current_mclk = rdev->pm.default_mclk;
1315 if (rdev->pm.power_state) {
1316 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1317 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1318 }
1319 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1320 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1321 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1322 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1323 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1324 }
1325 mutex_unlock(&rdev->pm.mutex);
1326 radeon_pm_compute_clocks(rdev);
1327 }
1328
radeon_pm_resume_dpm(struct radeon_device * rdev)1329 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1330 {
1331 int ret;
1332
1333 /* asic init will reset to the boot state */
1334 mutex_lock(&rdev->pm.mutex);
1335 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1336 radeon_dpm_setup_asic(rdev);
1337 ret = radeon_dpm_enable(rdev);
1338 mutex_unlock(&rdev->pm.mutex);
1339 if (ret)
1340 goto dpm_resume_fail;
1341 rdev->pm.dpm_enabled = true;
1342 return;
1343
1344 dpm_resume_fail:
1345 DRM_ERROR("radeon: dpm resume failed\n");
1346 if ((rdev->family >= CHIP_BARTS) &&
1347 (rdev->family <= CHIP_CAYMAN) &&
1348 rdev->mc_fw) {
1349 if (rdev->pm.default_vddc)
1350 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1351 SET_VOLTAGE_TYPE_ASIC_VDDC);
1352 if (rdev->pm.default_vddci)
1353 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1354 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1355 if (rdev->pm.default_sclk)
1356 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1357 if (rdev->pm.default_mclk)
1358 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1359 }
1360 }
1361
radeon_pm_resume(struct radeon_device * rdev)1362 void radeon_pm_resume(struct radeon_device *rdev)
1363 {
1364 if (rdev->pm.pm_method == PM_METHOD_DPM)
1365 radeon_pm_resume_dpm(rdev);
1366 else
1367 radeon_pm_resume_old(rdev);
1368 }
1369
radeon_pm_init_old(struct radeon_device * rdev)1370 static int radeon_pm_init_old(struct radeon_device *rdev)
1371 {
1372 int ret;
1373
1374 rdev->pm.profile = PM_PROFILE_DEFAULT;
1375 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1376 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1377 rdev->pm.dynpm_can_upclock = true;
1378 rdev->pm.dynpm_can_downclock = true;
1379 rdev->pm.default_sclk = rdev->clock.default_sclk;
1380 rdev->pm.default_mclk = rdev->clock.default_mclk;
1381 rdev->pm.current_sclk = rdev->clock.default_sclk;
1382 rdev->pm.current_mclk = rdev->clock.default_mclk;
1383 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1384
1385 if (rdev->bios) {
1386 if (rdev->is_atom_bios)
1387 radeon_atombios_get_power_modes(rdev);
1388 else
1389 radeon_combios_get_power_modes(rdev);
1390 radeon_pm_print_states(rdev);
1391 radeon_pm_init_profile(rdev);
1392 /* set up the default clocks if the MC ucode is loaded */
1393 if ((rdev->family >= CHIP_BARTS) &&
1394 (rdev->family <= CHIP_CAYMAN) &&
1395 rdev->mc_fw) {
1396 if (rdev->pm.default_vddc)
1397 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1398 SET_VOLTAGE_TYPE_ASIC_VDDC);
1399 if (rdev->pm.default_vddci)
1400 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1401 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1402 if (rdev->pm.default_sclk)
1403 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1404 if (rdev->pm.default_mclk)
1405 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1406 }
1407 }
1408
1409 /* set up the internal thermal sensor if applicable */
1410 ret = radeon_hwmon_init(rdev);
1411 if (ret)
1412 return ret;
1413
1414 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1415
1416 if (rdev->pm.num_power_states > 1) {
1417 radeon_debugfs_pm_init(rdev);
1418 DRM_INFO("radeon: power management initialized\n");
1419 }
1420
1421 return 0;
1422 }
1423
radeon_dpm_print_power_states(struct radeon_device * rdev)1424 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1425 {
1426 int i;
1427
1428 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1429 printk("== power state %d ==\n", i);
1430 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1431 }
1432 }
1433
radeon_pm_init_dpm(struct radeon_device * rdev)1434 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1435 {
1436 int ret;
1437
1438 /* default to balanced state */
1439 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1440 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1441 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1442 rdev->pm.default_sclk = rdev->clock.default_sclk;
1443 rdev->pm.default_mclk = rdev->clock.default_mclk;
1444 rdev->pm.current_sclk = rdev->clock.default_sclk;
1445 rdev->pm.current_mclk = rdev->clock.default_mclk;
1446 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1447
1448 if (rdev->bios && rdev->is_atom_bios)
1449 radeon_atombios_get_power_modes(rdev);
1450 else
1451 return -EINVAL;
1452
1453 /* set up the internal thermal sensor if applicable */
1454 ret = radeon_hwmon_init(rdev);
1455 if (ret)
1456 return ret;
1457
1458 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1459 mutex_lock(&rdev->pm.mutex);
1460 radeon_dpm_init(rdev);
1461 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1462 if (radeon_dpm == 1)
1463 radeon_dpm_print_power_states(rdev);
1464 radeon_dpm_setup_asic(rdev);
1465 ret = radeon_dpm_enable(rdev);
1466 mutex_unlock(&rdev->pm.mutex);
1467 if (ret)
1468 goto dpm_failed;
1469 rdev->pm.dpm_enabled = true;
1470
1471 radeon_debugfs_pm_init(rdev);
1472
1473 DRM_INFO("radeon: dpm initialized\n");
1474
1475 return 0;
1476
1477 dpm_failed:
1478 rdev->pm.dpm_enabled = false;
1479 if ((rdev->family >= CHIP_BARTS) &&
1480 (rdev->family <= CHIP_CAYMAN) &&
1481 rdev->mc_fw) {
1482 if (rdev->pm.default_vddc)
1483 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1484 SET_VOLTAGE_TYPE_ASIC_VDDC);
1485 if (rdev->pm.default_vddci)
1486 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1487 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1488 if (rdev->pm.default_sclk)
1489 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1490 if (rdev->pm.default_mclk)
1491 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1492 }
1493 DRM_ERROR("radeon: dpm initialization failed\n");
1494 return ret;
1495 }
1496
1497 struct radeon_dpm_quirk {
1498 u32 chip_vendor;
1499 u32 chip_device;
1500 u32 subsys_vendor;
1501 u32 subsys_device;
1502 };
1503
1504 /* cards with dpm stability problems */
1505 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1506 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1507 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1508 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1509 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1510 { 0, 0, 0, 0 },
1511 };
1512
radeon_pm_init(struct radeon_device * rdev)1513 int radeon_pm_init(struct radeon_device *rdev)
1514 {
1515 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1516 bool disable_dpm = false;
1517
1518 /* Apply dpm quirks */
1519 while (p && p->chip_device != 0) {
1520 if (rdev->pdev->vendor == p->chip_vendor &&
1521 rdev->pdev->device == p->chip_device &&
1522 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1523 rdev->pdev->subsystem_device == p->subsys_device) {
1524 disable_dpm = true;
1525 break;
1526 }
1527 ++p;
1528 }
1529
1530 /* enable dpm on rv6xx+ */
1531 switch (rdev->family) {
1532 case CHIP_RV610:
1533 case CHIP_RV630:
1534 case CHIP_RV620:
1535 case CHIP_RV635:
1536 case CHIP_RV670:
1537 case CHIP_RS780:
1538 case CHIP_RS880:
1539 case CHIP_RV770:
1540 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1541 if (!rdev->rlc_fw)
1542 rdev->pm.pm_method = PM_METHOD_PROFILE;
1543 else if ((rdev->family >= CHIP_RV770) &&
1544 (!(rdev->flags & RADEON_IS_IGP)) &&
1545 (!rdev->smc_fw))
1546 rdev->pm.pm_method = PM_METHOD_PROFILE;
1547 else if (radeon_dpm == 1)
1548 rdev->pm.pm_method = PM_METHOD_DPM;
1549 else
1550 rdev->pm.pm_method = PM_METHOD_PROFILE;
1551 break;
1552 case CHIP_RV730:
1553 case CHIP_RV710:
1554 case CHIP_RV740:
1555 case CHIP_CEDAR:
1556 case CHIP_REDWOOD:
1557 case CHIP_JUNIPER:
1558 case CHIP_CYPRESS:
1559 case CHIP_HEMLOCK:
1560 case CHIP_PALM:
1561 case CHIP_SUMO:
1562 case CHIP_SUMO2:
1563 case CHIP_BARTS:
1564 case CHIP_TURKS:
1565 case CHIP_CAICOS:
1566 case CHIP_CAYMAN:
1567 case CHIP_ARUBA:
1568 case CHIP_TAHITI:
1569 case CHIP_PITCAIRN:
1570 case CHIP_VERDE:
1571 case CHIP_OLAND:
1572 case CHIP_HAINAN:
1573 case CHIP_BONAIRE:
1574 case CHIP_KABINI:
1575 case CHIP_KAVERI:
1576 case CHIP_HAWAII:
1577 case CHIP_MULLINS:
1578 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1579 if (!rdev->rlc_fw)
1580 rdev->pm.pm_method = PM_METHOD_PROFILE;
1581 else if ((rdev->family >= CHIP_RV770) &&
1582 (!(rdev->flags & RADEON_IS_IGP)) &&
1583 (!rdev->smc_fw))
1584 rdev->pm.pm_method = PM_METHOD_PROFILE;
1585 else if (disable_dpm && (radeon_dpm == -1))
1586 rdev->pm.pm_method = PM_METHOD_PROFILE;
1587 else if (radeon_dpm == 0)
1588 rdev->pm.pm_method = PM_METHOD_PROFILE;
1589 else
1590 rdev->pm.pm_method = PM_METHOD_DPM;
1591 break;
1592 default:
1593 /* default to profile method */
1594 rdev->pm.pm_method = PM_METHOD_PROFILE;
1595 break;
1596 }
1597
1598 if (rdev->pm.pm_method == PM_METHOD_DPM)
1599 return radeon_pm_init_dpm(rdev);
1600 else
1601 return radeon_pm_init_old(rdev);
1602 }
1603
radeon_pm_late_init(struct radeon_device * rdev)1604 int radeon_pm_late_init(struct radeon_device *rdev)
1605 {
1606 int ret = 0;
1607
1608 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1609 if (rdev->pm.dpm_enabled) {
1610 #ifdef __linux__
1611 if (!rdev->pm.sysfs_initialized) {
1612 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1613 if (ret)
1614 DRM_ERROR("failed to create device file for dpm state\n");
1615 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1616 if (ret)
1617 DRM_ERROR("failed to create device file for dpm state\n");
1618 /* XXX: these are noops for dpm but are here for backwards compat */
1619 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1620 if (ret)
1621 DRM_ERROR("failed to create device file for power profile\n");
1622 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1623 if (ret)
1624 DRM_ERROR("failed to create device file for power method\n");
1625 rdev->pm.sysfs_initialized = true;
1626 }
1627 #endif
1628
1629 mutex_lock(&rdev->pm.mutex);
1630 ret = radeon_dpm_late_enable(rdev);
1631 mutex_unlock(&rdev->pm.mutex);
1632 if (ret) {
1633 rdev->pm.dpm_enabled = false;
1634 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1635 } else {
1636 /* set the dpm state for PX since there won't be
1637 * a modeset to call this.
1638 */
1639 radeon_pm_compute_clocks(rdev);
1640 }
1641 }
1642 } else {
1643 #ifdef __linux__
1644 if ((rdev->pm.num_power_states > 1) &&
1645 (!rdev->pm.sysfs_initialized)) {
1646 /* where's the best place to put these? */
1647 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1648 if (ret)
1649 DRM_ERROR("failed to create device file for power profile\n");
1650 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1651 if (ret)
1652 DRM_ERROR("failed to create device file for power method\n");
1653 else
1654 rdev->pm.sysfs_initialized = true;
1655 }
1656 #endif
1657 }
1658 return ret;
1659 }
1660
radeon_pm_fini_old(struct radeon_device * rdev)1661 static void radeon_pm_fini_old(struct radeon_device *rdev)
1662 {
1663 if (rdev->pm.num_power_states > 1) {
1664 mutex_lock(&rdev->pm.mutex);
1665 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1666 rdev->pm.profile = PM_PROFILE_DEFAULT;
1667 radeon_pm_update_profile(rdev);
1668 radeon_pm_set_clocks(rdev);
1669 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1670 /* reset default clocks */
1671 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1672 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1673 radeon_pm_set_clocks(rdev);
1674 }
1675 mutex_unlock(&rdev->pm.mutex);
1676
1677 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1678
1679 device_remove_file(rdev->dev, &dev_attr_power_profile);
1680 device_remove_file(rdev->dev, &dev_attr_power_method);
1681 }
1682
1683 radeon_hwmon_fini(rdev);
1684 kfree(rdev->pm.power_state);
1685 }
1686
radeon_pm_fini_dpm(struct radeon_device * rdev)1687 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1688 {
1689 if (rdev->pm.num_power_states > 1) {
1690 mutex_lock(&rdev->pm.mutex);
1691 radeon_dpm_disable(rdev);
1692 mutex_unlock(&rdev->pm.mutex);
1693
1694 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1695 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1696 /* XXX backwards compat */
1697 device_remove_file(rdev->dev, &dev_attr_power_profile);
1698 device_remove_file(rdev->dev, &dev_attr_power_method);
1699 }
1700 radeon_dpm_fini(rdev);
1701
1702 radeon_hwmon_fini(rdev);
1703 kfree(rdev->pm.power_state);
1704 }
1705
radeon_pm_fini(struct radeon_device * rdev)1706 void radeon_pm_fini(struct radeon_device *rdev)
1707 {
1708 if (rdev->pm.pm_method == PM_METHOD_DPM)
1709 radeon_pm_fini_dpm(rdev);
1710 else
1711 radeon_pm_fini_old(rdev);
1712 }
1713
radeon_pm_compute_clocks_old(struct radeon_device * rdev)1714 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1715 {
1716 struct drm_device *ddev = rdev_to_drm(rdev);
1717 struct drm_crtc *crtc;
1718 struct radeon_crtc *radeon_crtc;
1719
1720 if (rdev->pm.num_power_states < 2)
1721 return;
1722
1723 mutex_lock(&rdev->pm.mutex);
1724
1725 rdev->pm.active_crtcs = 0;
1726 rdev->pm.active_crtc_count = 0;
1727 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1728 list_for_each_entry(crtc,
1729 &ddev->mode_config.crtc_list, head) {
1730 radeon_crtc = to_radeon_crtc(crtc);
1731 if (radeon_crtc->enabled) {
1732 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1733 rdev->pm.active_crtc_count++;
1734 }
1735 }
1736 }
1737
1738 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1739 radeon_pm_update_profile(rdev);
1740 radeon_pm_set_clocks(rdev);
1741 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1742 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1743 if (rdev->pm.active_crtc_count > 1) {
1744 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1745 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1746
1747 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1748 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1749 radeon_pm_get_dynpm_state(rdev);
1750 radeon_pm_set_clocks(rdev);
1751
1752 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1753 }
1754 } else if (rdev->pm.active_crtc_count == 1) {
1755 /* TODO: Increase clocks if needed for current mode */
1756
1757 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1758 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1759 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1760 radeon_pm_get_dynpm_state(rdev);
1761 radeon_pm_set_clocks(rdev);
1762
1763 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1764 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1765 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1766 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1767 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1768 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1769 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1770 }
1771 } else { /* count == 0 */
1772 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1773 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1774
1775 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1776 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1777 radeon_pm_get_dynpm_state(rdev);
1778 radeon_pm_set_clocks(rdev);
1779 }
1780 }
1781 }
1782 }
1783
1784 mutex_unlock(&rdev->pm.mutex);
1785 }
1786
radeon_pm_compute_clocks_dpm(struct radeon_device * rdev)1787 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1788 {
1789 struct drm_device *ddev = rdev_to_drm(rdev);
1790 struct drm_crtc *crtc;
1791 struct radeon_crtc *radeon_crtc;
1792 struct radeon_connector *radeon_connector;
1793
1794 if (!rdev->pm.dpm_enabled)
1795 return;
1796
1797 mutex_lock(&rdev->pm.mutex);
1798
1799 /* update active crtc counts */
1800 rdev->pm.dpm.new_active_crtcs = 0;
1801 rdev->pm.dpm.new_active_crtc_count = 0;
1802 rdev->pm.dpm.high_pixelclock_count = 0;
1803 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1804 list_for_each_entry(crtc,
1805 &ddev->mode_config.crtc_list, head) {
1806 radeon_crtc = to_radeon_crtc(crtc);
1807 if (crtc->enabled) {
1808 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1809 rdev->pm.dpm.new_active_crtc_count++;
1810 if (!radeon_crtc->connector)
1811 continue;
1812
1813 radeon_connector = to_radeon_connector(radeon_crtc->connector);
1814 if (radeon_connector->pixelclock_for_modeset > 297000)
1815 rdev->pm.dpm.high_pixelclock_count++;
1816 }
1817 }
1818 }
1819
1820 /* update battery/ac status */
1821 if (power_supply_is_system_supplied() > 0)
1822 rdev->pm.dpm.ac_power = true;
1823 else
1824 rdev->pm.dpm.ac_power = false;
1825
1826 radeon_dpm_change_power_state_locked(rdev);
1827
1828 mutex_unlock(&rdev->pm.mutex);
1829
1830 }
1831
radeon_pm_compute_clocks(struct radeon_device * rdev)1832 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1833 {
1834 if (rdev->pm.pm_method == PM_METHOD_DPM)
1835 radeon_pm_compute_clocks_dpm(rdev);
1836 else
1837 radeon_pm_compute_clocks_old(rdev);
1838 }
1839
radeon_pm_in_vbl(struct radeon_device * rdev)1840 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1841 {
1842 int crtc, vpos, hpos, vbl_status;
1843 bool in_vbl = true;
1844
1845 /* Iterate over all active crtc's. All crtc's must be in vblank,
1846 * otherwise return in_vbl == false.
1847 */
1848 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1849 if (rdev->pm.active_crtcs & (1 << crtc)) {
1850 vbl_status = radeon_get_crtc_scanoutpos(rdev_to_drm(rdev),
1851 crtc,
1852 USE_REAL_VBLANKSTART,
1853 &vpos, &hpos, NULL, NULL,
1854 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1855 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1856 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1857 in_vbl = false;
1858 }
1859 }
1860
1861 return in_vbl;
1862 }
1863
radeon_pm_debug_check_in_vbl(struct radeon_device * rdev,bool finish)1864 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1865 {
1866 u32 stat_crtc = 0;
1867 bool in_vbl = radeon_pm_in_vbl(rdev);
1868
1869 if (!in_vbl)
1870 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1871 finish ? "exit" : "entry");
1872 return in_vbl;
1873 }
1874
radeon_dynpm_idle_work_handler(struct work_struct * work)1875 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1876 {
1877 struct radeon_device *rdev;
1878
1879 rdev = container_of(work, struct radeon_device,
1880 pm.dynpm_idle_work.work);
1881
1882 mutex_lock(&rdev->pm.mutex);
1883 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1884 int not_processed = 0;
1885 int i;
1886
1887 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1888 struct radeon_ring *ring = &rdev->ring[i];
1889
1890 if (ring->ready) {
1891 not_processed += radeon_fence_count_emitted(rdev, i);
1892 if (not_processed >= 3)
1893 break;
1894 }
1895 }
1896
1897 if (not_processed >= 3) { /* should upclock */
1898 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1899 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1900 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1901 rdev->pm.dynpm_can_upclock) {
1902 rdev->pm.dynpm_planned_action =
1903 DYNPM_ACTION_UPCLOCK;
1904 rdev->pm.dynpm_action_timeout = jiffies +
1905 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1906 }
1907 } else if (not_processed == 0) { /* should downclock */
1908 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1909 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1910 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1911 rdev->pm.dynpm_can_downclock) {
1912 rdev->pm.dynpm_planned_action =
1913 DYNPM_ACTION_DOWNCLOCK;
1914 rdev->pm.dynpm_action_timeout = jiffies +
1915 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1916 }
1917 }
1918
1919 /* Note, radeon_pm_set_clocks is called with static_switch set
1920 * to false since we want to wait for vbl to avoid flicker.
1921 */
1922 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1923 time_after(jiffies, rdev->pm.dynpm_action_timeout)) {
1924 radeon_pm_get_dynpm_state(rdev);
1925 radeon_pm_set_clocks(rdev);
1926 }
1927
1928 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1929 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1930 }
1931 mutex_unlock(&rdev->pm.mutex);
1932 }
1933
1934 /*
1935 * Debugfs info
1936 */
1937 #if defined(CONFIG_DEBUG_FS)
1938
radeon_debugfs_pm_info_show(struct seq_file * m,void * unused)1939 static int radeon_debugfs_pm_info_show(struct seq_file *m, void *unused)
1940 {
1941 struct radeon_device *rdev = m->private;
1942 struct drm_device *ddev = rdev_to_drm(rdev);
1943
1944 if ((rdev->flags & RADEON_IS_PX) &&
1945 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1946 seq_printf(m, "PX asic powered off\n");
1947 } else if (rdev->pm.dpm_enabled) {
1948 mutex_lock(&rdev->pm.mutex);
1949 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1950 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1951 else
1952 seq_printf(m, "Debugfs support not implemented for this asic\n");
1953 mutex_unlock(&rdev->pm.mutex);
1954 } else {
1955 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1956 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1957 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1958 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1959 else
1960 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1961 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1962 if (rdev->asic->pm.get_memory_clock)
1963 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1964 if (rdev->pm.current_vddc)
1965 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1966 if (rdev->asic->pm.get_pcie_lanes)
1967 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1968 }
1969
1970 return 0;
1971 }
1972
1973 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_pm_info);
1974 #endif
1975
radeon_debugfs_pm_init(struct radeon_device * rdev)1976 static void radeon_debugfs_pm_init(struct radeon_device *rdev)
1977 {
1978 #if defined(CONFIG_DEBUG_FS)
1979 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
1980
1981 debugfs_create_file("radeon_pm_info", 0444, root, rdev,
1982 &radeon_debugfs_pm_info_fops);
1983
1984 #endif
1985 }
1986