1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/acpi.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32
33 #include <drm/drm_device.h>
34
35 #include "atom.h"
36 #include "radeon.h"
37 #include "radeon_reg.h"
38
39 #if defined(__amd64__) || defined(__i386__)
40 #include <dev/isa/isareg.h>
41 #include <dev/isa/isavar.h>
42 #endif
43
44 #if defined (__loongson__)
45 #include <machine/autoconf.h>
46 #endif
47
48 /*
49 * BIOS.
50 */
51
52 /* If you boot an IGP board with a discrete card as the primary,
53 * the IGP rom is not accessible via the rom bar as the IGP rom is
54 * part of the system bios. On boot, the system bios puts a
55 * copy of the igp rom at the start of vram if a discrete card is
56 * present.
57 */
58 #ifdef __linux__
igp_read_bios_from_vram(struct radeon_device * rdev)59 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
60 {
61 uint8_t __iomem *bios;
62 resource_size_t vram_base;
63 resource_size_t size = 256 * 1024; /* ??? */
64
65 if (!(rdev->flags & RADEON_IS_IGP))
66 if (!radeon_card_posted(rdev))
67 return false;
68
69 rdev->bios = NULL;
70 vram_base = pci_resource_start(rdev->pdev, 0);
71 bios = ioremap(vram_base, size);
72 if (!bios) {
73 return false;
74 }
75
76 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
77 iounmap(bios);
78 return false;
79 }
80 rdev->bios = kmalloc(size, GFP_KERNEL);
81 if (rdev->bios == NULL) {
82 iounmap(bios);
83 return false;
84 }
85 memcpy_fromio(rdev->bios, bios, size);
86 iounmap(bios);
87 return true;
88 }
89 #else
igp_read_bios_from_vram(struct radeon_device * rdev)90 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
91 {
92 bus_size_t size = 256 * 1024; /* ??? */
93 bus_space_handle_t bsh;
94 bus_space_tag_t bst = rdev->memt;
95
96 if (!(rdev->flags & RADEON_IS_IGP))
97 if (!radeon_card_posted(rdev))
98 return false;
99
100 rdev->bios = NULL;
101
102 if (bus_space_map(bst, rdev->fb_aper_offset, size, 0, &bsh) != 0)
103 return false;
104
105 rdev->bios = kmalloc(size, GFP_KERNEL);
106 bus_space_read_region_1(rdev->memt, bsh, 0, rdev->bios, size);
107 bus_space_unmap(bst, bsh, size);
108
109 if (size == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
110 kfree(rdev->bios);
111 rdev->bios = NULL;
112 return false;
113 }
114
115 return true;
116 }
117 #endif
118
119 #ifdef __linux__
radeon_read_bios(struct radeon_device * rdev)120 static bool radeon_read_bios(struct radeon_device *rdev)
121 {
122 uint8_t __iomem *bios, val1, val2;
123 size_t size;
124
125 rdev->bios = NULL;
126 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
127 bios = pci_map_rom(rdev->pdev, &size);
128 if (!bios) {
129 return false;
130 }
131
132 val1 = readb(&bios[0]);
133 val2 = readb(&bios[1]);
134
135 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
136 pci_unmap_rom(rdev->pdev, bios);
137 return false;
138 }
139 rdev->bios = kzalloc(size, GFP_KERNEL);
140 if (rdev->bios == NULL) {
141 pci_unmap_rom(rdev->pdev, bios);
142 return false;
143 }
144 memcpy_fromio(rdev->bios, bios, size);
145 pci_unmap_rom(rdev->pdev, bios);
146 return true;
147 }
148 #else
radeon_read_bios(struct radeon_device * rdev)149 static bool radeon_read_bios(struct radeon_device *rdev)
150 {
151 bus_size_t size;
152 pcireg_t address, mask;
153 bus_space_handle_t romh;
154 int rc;
155
156 rdev->bios = NULL;
157 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
158
159 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);
160 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
161 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);
162 address |= PCI_ROM_ENABLE;
163 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address);
164
165 size = PCI_ROM_SIZE(mask);
166 if (size == 0)
167 return false;
168 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 0, &romh);
169 if (rc != 0) {
170 printf(": can't map PCI ROM (%d)\n", rc);
171 return false;
172 }
173
174 rdev->bios = kmalloc(size, GFP_KERNEL);
175 bus_space_read_region_1(rdev->memt, romh, 0, rdev->bios, size);
176 bus_space_unmap(rdev->memt, romh, size);
177
178 if (size == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
179 kfree(rdev->bios);
180 rdev->bios = NULL;
181 return false;
182 }
183 return true;
184 }
185
186 #endif
187
188 #ifdef __linux__
radeon_read_platform_bios(struct radeon_device * rdev)189 static bool radeon_read_platform_bios(struct radeon_device *rdev)
190 {
191 phys_addr_t rom = rdev->pdev->rom;
192 size_t romlen = rdev->pdev->romlen;
193 void __iomem *bios;
194
195 rdev->bios = NULL;
196
197 if (!rom || romlen == 0)
198 return false;
199
200 rdev->bios = kzalloc(romlen, GFP_KERNEL);
201 if (!rdev->bios)
202 return false;
203
204 bios = ioremap(rom, romlen);
205 if (!bios)
206 goto free_bios;
207
208 memcpy_fromio(rdev->bios, bios, romlen);
209 iounmap(bios);
210
211 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
212 goto free_bios;
213
214 return true;
215 free_bios:
216 kfree(rdev->bios);
217 return false;
218 }
219 #else
radeon_read_platform_bios(struct radeon_device * rdev)220 static bool radeon_read_platform_bios(struct radeon_device *rdev)
221 {
222 #if defined(__amd64__) || defined(__i386__) || defined(__loongson__)
223 uint8_t __iomem *bios;
224 bus_size_t size = 256 * 1024; /* ??? */
225 uint8_t *found = NULL;
226 int i;
227
228 if (!(rdev->flags & RADEON_IS_IGP))
229 if (!radeon_card_posted(rdev))
230 return false;
231
232 rdev->bios = NULL;
233
234 #if defined(__loongson__)
235 if (loongson_videobios == NULL)
236 return false;
237 bios = loongson_videobios;
238 #else
239 bios = (u8 *)ISA_HOLE_VADDR(0xc0000);
240 #endif
241
242 for (i = 0; i + 2 < size; i++) {
243 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) {
244 found = bios + i;
245 break;
246 }
247
248 }
249 if (found == NULL) {
250 DRM_ERROR("bios size zero or checksum mismatch\n");
251 return false;
252 }
253
254 rdev->bios = kmalloc(size, GFP_KERNEL);
255 if (rdev->bios == NULL)
256 return false;
257
258 memcpy(rdev->bios, found, size);
259
260 return true;
261 #endif
262 return false;
263 }
264 #endif
265
266 #ifdef CONFIG_ACPI
267 /* ATRM is used to get the BIOS on the discrete cards in
268 * dual-gpu systems.
269 */
270 /* retrieve the ROM in 4k blocks */
271 #define ATRM_BIOS_PAGE 4096
272 /**
273 * radeon_atrm_call - fetch a chunk of the vbios
274 *
275 * @atrm_handle: acpi ATRM handle
276 * @bios: vbios image pointer
277 * @offset: offset of vbios image data to fetch
278 * @len: length of vbios image data to fetch
279 *
280 * Executes ATRM to fetch a chunk of the discrete
281 * vbios image on PX systems (all asics).
282 * Returns the length of the buffer fetched.
283 */
radeon_atrm_call(acpi_handle atrm_handle,uint8_t * bios,int offset,int len)284 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
285 int offset, int len)
286 {
287 acpi_status status;
288 union acpi_object atrm_arg_elements[2], *obj;
289 struct acpi_object_list atrm_arg;
290 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
291
292 atrm_arg.count = 2;
293 atrm_arg.pointer = &atrm_arg_elements[0];
294
295 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
296 atrm_arg_elements[0].integer.value = offset;
297
298 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
299 atrm_arg_elements[1].integer.value = len;
300
301 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
302 if (ACPI_FAILURE(status)) {
303 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
304 return -ENODEV;
305 }
306
307 obj = (union acpi_object *)buffer.pointer;
308 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
309 len = obj->buffer.length;
310 kfree(buffer.pointer);
311 return len;
312 }
313
radeon_atrm_get_bios(struct radeon_device * rdev)314 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
315 {
316 int ret;
317 int size = 256 * 1024;
318 int i;
319 struct pci_dev *pdev = NULL;
320 acpi_handle dhandle, atrm_handle;
321 acpi_status status;
322 bool found = false;
323
324 /* ATRM is for the discrete card only */
325 if (rdev->flags & RADEON_IS_IGP)
326 return false;
327
328 #ifdef notyet
329 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
330 dhandle = ACPI_HANDLE(&pdev->dev);
331 if (!dhandle)
332 continue;
333
334 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
335 if (ACPI_SUCCESS(status)) {
336 found = true;
337 break;
338 }
339 }
340
341 if (!found) {
342 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
343 dhandle = ACPI_HANDLE(&pdev->dev);
344 if (!dhandle)
345 continue;
346
347 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
348 if (ACPI_SUCCESS(status)) {
349 found = true;
350 break;
351 }
352 }
353 }
354 #else
355 {
356 pdev = rdev->pdev;
357 dhandle = ACPI_HANDLE(&pdev->dev);
358
359 if (dhandle) {
360 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
361 if (ACPI_SUCCESS(status)) {
362 found = true;
363 }
364 }
365 }
366 #endif
367
368 if (!found)
369 return false;
370 pci_dev_put(pdev);
371
372 rdev->bios = kmalloc(size, GFP_KERNEL);
373 if (!rdev->bios) {
374 DRM_ERROR("Unable to allocate bios\n");
375 return false;
376 }
377
378 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
379 ret = radeon_atrm_call(atrm_handle,
380 rdev->bios,
381 (i * ATRM_BIOS_PAGE),
382 ATRM_BIOS_PAGE);
383 if (ret < ATRM_BIOS_PAGE)
384 break;
385 }
386
387 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
388 kfree(rdev->bios);
389 return false;
390 }
391 return true;
392 }
393 #else
radeon_atrm_get_bios(struct radeon_device * rdev)394 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
395 {
396 return false;
397 }
398 #endif
399
ni_read_disabled_bios(struct radeon_device * rdev)400 static bool ni_read_disabled_bios(struct radeon_device *rdev)
401 {
402 u32 bus_cntl;
403 u32 d1vga_control;
404 u32 d2vga_control;
405 u32 vga_render_control;
406 u32 rom_cntl;
407 bool r;
408
409 bus_cntl = RREG32(R600_BUS_CNTL);
410 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
411 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
412 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
413 rom_cntl = RREG32(R600_ROM_CNTL);
414
415 /* enable the rom */
416 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
417 if (!ASIC_IS_NODCE(rdev)) {
418 /* Disable VGA mode */
419 WREG32(AVIVO_D1VGA_CONTROL,
420 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
421 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
422 WREG32(AVIVO_D2VGA_CONTROL,
423 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
424 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
425 WREG32(AVIVO_VGA_RENDER_CONTROL,
426 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
427 }
428 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
429
430 r = radeon_read_bios(rdev);
431
432 /* restore regs */
433 WREG32(R600_BUS_CNTL, bus_cntl);
434 if (!ASIC_IS_NODCE(rdev)) {
435 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
436 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
437 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
438 }
439 WREG32(R600_ROM_CNTL, rom_cntl);
440 return r;
441 }
442
r700_read_disabled_bios(struct radeon_device * rdev)443 static bool r700_read_disabled_bios(struct radeon_device *rdev)
444 {
445 uint32_t viph_control;
446 uint32_t bus_cntl;
447 uint32_t d1vga_control;
448 uint32_t d2vga_control;
449 uint32_t vga_render_control;
450 uint32_t rom_cntl;
451 uint32_t cg_spll_func_cntl = 0;
452 uint32_t cg_spll_status;
453 bool r;
454
455 viph_control = RREG32(RADEON_VIPH_CONTROL);
456 bus_cntl = RREG32(R600_BUS_CNTL);
457 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
458 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
459 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
460 rom_cntl = RREG32(R600_ROM_CNTL);
461
462 /* disable VIP */
463 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
464 /* enable the rom */
465 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
466 /* Disable VGA mode */
467 WREG32(AVIVO_D1VGA_CONTROL,
468 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
469 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
470 WREG32(AVIVO_D2VGA_CONTROL,
471 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
472 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
473 WREG32(AVIVO_VGA_RENDER_CONTROL,
474 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
475
476 if (rdev->family == CHIP_RV730) {
477 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
478
479 /* enable bypass mode */
480 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
481 R600_SPLL_BYPASS_EN));
482
483 /* wait for SPLL_CHG_STATUS to change to 1 */
484 cg_spll_status = 0;
485 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
486 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
487
488 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
489 } else
490 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
491
492 r = radeon_read_bios(rdev);
493
494 /* restore regs */
495 if (rdev->family == CHIP_RV730) {
496 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
497
498 /* wait for SPLL_CHG_STATUS to change to 1 */
499 cg_spll_status = 0;
500 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
501 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
502 }
503 WREG32(RADEON_VIPH_CONTROL, viph_control);
504 WREG32(R600_BUS_CNTL, bus_cntl);
505 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
506 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
507 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
508 WREG32(R600_ROM_CNTL, rom_cntl);
509 return r;
510 }
511
r600_read_disabled_bios(struct radeon_device * rdev)512 static bool r600_read_disabled_bios(struct radeon_device *rdev)
513 {
514 uint32_t viph_control;
515 uint32_t bus_cntl;
516 uint32_t d1vga_control;
517 uint32_t d2vga_control;
518 uint32_t vga_render_control;
519 uint32_t rom_cntl;
520 uint32_t general_pwrmgt;
521 uint32_t low_vid_lower_gpio_cntl;
522 uint32_t medium_vid_lower_gpio_cntl;
523 uint32_t high_vid_lower_gpio_cntl;
524 uint32_t ctxsw_vid_lower_gpio_cntl;
525 uint32_t lower_gpio_enable;
526 bool r;
527
528 /*
529 * Some machines with RV610 running amd64 pass initial checks but later
530 * fail atombios specific checks. Return early here so the bios will be
531 * read from 0xc0000 in radeon_read_platform_bios() instead.
532 * RV610 0x1002:0x94C3 0x1028:0x0402 0x00
533 * RV610 0x1002:0x94C1 0x1028:0x0D02 0x00
534 */
535 if (rdev->family == CHIP_RV610)
536 return false;
537
538 viph_control = RREG32(RADEON_VIPH_CONTROL);
539 bus_cntl = RREG32(R600_BUS_CNTL);
540 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
541 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
542 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
543 rom_cntl = RREG32(R600_ROM_CNTL);
544 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
545 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
546 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
547 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
548 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
549 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
550
551 /* disable VIP */
552 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
553 /* enable the rom */
554 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
555 /* Disable VGA mode */
556 WREG32(AVIVO_D1VGA_CONTROL,
557 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
558 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
559 WREG32(AVIVO_D2VGA_CONTROL,
560 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
561 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
562 WREG32(AVIVO_VGA_RENDER_CONTROL,
563 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
564
565 WREG32(R600_ROM_CNTL,
566 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
567 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
568 R600_SCK_OVERWRITE));
569
570 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
571 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
572 (low_vid_lower_gpio_cntl & ~0x400));
573 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
574 (medium_vid_lower_gpio_cntl & ~0x400));
575 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
576 (high_vid_lower_gpio_cntl & ~0x400));
577 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
578 (ctxsw_vid_lower_gpio_cntl & ~0x400));
579 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
580
581 r = radeon_read_bios(rdev);
582
583 /* restore regs */
584 WREG32(RADEON_VIPH_CONTROL, viph_control);
585 WREG32(R600_BUS_CNTL, bus_cntl);
586 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
587 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
588 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
589 WREG32(R600_ROM_CNTL, rom_cntl);
590 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
591 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
592 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
593 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
594 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
595 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
596 return r;
597 }
598
avivo_read_disabled_bios(struct radeon_device * rdev)599 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
600 {
601 uint32_t seprom_cntl1;
602 uint32_t viph_control;
603 uint32_t bus_cntl;
604 uint32_t d1vga_control;
605 uint32_t d2vga_control;
606 uint32_t vga_render_control;
607 uint32_t gpiopad_a;
608 uint32_t gpiopad_en;
609 uint32_t gpiopad_mask;
610 bool r;
611
612 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
613 viph_control = RREG32(RADEON_VIPH_CONTROL);
614 bus_cntl = RREG32(RV370_BUS_CNTL);
615 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
616 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
617 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
618 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
619 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
620 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
621
622 WREG32(RADEON_SEPROM_CNTL1,
623 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
624 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
625 WREG32(RADEON_GPIOPAD_A, 0);
626 WREG32(RADEON_GPIOPAD_EN, 0);
627 WREG32(RADEON_GPIOPAD_MASK, 0);
628
629 /* disable VIP */
630 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
631
632 /* enable the rom */
633 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
634
635 /* Disable VGA mode */
636 WREG32(AVIVO_D1VGA_CONTROL,
637 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
638 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
639 WREG32(AVIVO_D2VGA_CONTROL,
640 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
641 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
642 WREG32(AVIVO_VGA_RENDER_CONTROL,
643 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
644
645 r = radeon_read_bios(rdev);
646
647 /* restore regs */
648 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
649 WREG32(RADEON_VIPH_CONTROL, viph_control);
650 WREG32(RV370_BUS_CNTL, bus_cntl);
651 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
652 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
653 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
654 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
655 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
656 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
657 return r;
658 }
659
legacy_read_disabled_bios(struct radeon_device * rdev)660 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
661 {
662 uint32_t seprom_cntl1;
663 uint32_t viph_control;
664 uint32_t bus_cntl;
665 uint32_t crtc_gen_cntl;
666 uint32_t crtc2_gen_cntl;
667 uint32_t crtc_ext_cntl;
668 uint32_t fp2_gen_cntl;
669 bool r;
670
671 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
672 viph_control = RREG32(RADEON_VIPH_CONTROL);
673 if (rdev->flags & RADEON_IS_PCIE)
674 bus_cntl = RREG32(RV370_BUS_CNTL);
675 else
676 bus_cntl = RREG32(RADEON_BUS_CNTL);
677 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
678 crtc2_gen_cntl = 0;
679 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
680 fp2_gen_cntl = 0;
681
682 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
683 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
684 }
685
686 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
687 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
688 }
689
690 WREG32(RADEON_SEPROM_CNTL1,
691 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
692 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
693
694 /* disable VIP */
695 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
696
697 /* enable the rom */
698 if (rdev->flags & RADEON_IS_PCIE)
699 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
700 else
701 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
702
703 /* Turn off mem requests and CRTC for both controllers */
704 WREG32(RADEON_CRTC_GEN_CNTL,
705 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
706 (RADEON_CRTC_DISP_REQ_EN_B |
707 RADEON_CRTC_EXT_DISP_EN)));
708 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
709 WREG32(RADEON_CRTC2_GEN_CNTL,
710 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
711 RADEON_CRTC2_DISP_REQ_EN_B));
712 }
713 /* Turn off CRTC */
714 WREG32(RADEON_CRTC_EXT_CNTL,
715 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
716 (RADEON_CRTC_SYNC_TRISTAT |
717 RADEON_CRTC_DISPLAY_DIS)));
718
719 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
720 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
721 }
722
723 r = radeon_read_bios(rdev);
724
725 /* restore regs */
726 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
727 WREG32(RADEON_VIPH_CONTROL, viph_control);
728 if (rdev->flags & RADEON_IS_PCIE)
729 WREG32(RV370_BUS_CNTL, bus_cntl);
730 else
731 WREG32(RADEON_BUS_CNTL, bus_cntl);
732 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
733 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
734 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
735 }
736 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
737 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
738 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
739 }
740 return r;
741 }
742
radeon_read_disabled_bios(struct radeon_device * rdev)743 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
744 {
745 if (rdev->flags & RADEON_IS_IGP)
746 return igp_read_bios_from_vram(rdev);
747 else if (rdev->family >= CHIP_BARTS)
748 return ni_read_disabled_bios(rdev);
749 else if (rdev->family >= CHIP_RV770)
750 return r700_read_disabled_bios(rdev);
751 else if (rdev->family >= CHIP_R600)
752 return r600_read_disabled_bios(rdev);
753 else if (rdev->family >= CHIP_RS600)
754 return avivo_read_disabled_bios(rdev);
755 else
756 return legacy_read_disabled_bios(rdev);
757 }
758
759 #ifdef CONFIG_ACPI
radeon_acpi_vfct_bios(struct radeon_device * rdev)760 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
761 {
762 struct acpi_table_header *hdr;
763 acpi_size tbl_size;
764 UEFI_ACPI_VFCT *vfct;
765 unsigned offset;
766 bool r = false;
767
768 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
769 return false;
770 tbl_size = hdr->length;
771 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
772 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
773 goto out;
774 }
775
776 vfct = (UEFI_ACPI_VFCT *)hdr;
777 offset = vfct->VBIOSImageOffset;
778
779 while (offset < tbl_size) {
780 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
781 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
782
783 offset += sizeof(VFCT_IMAGE_HEADER);
784 if (offset > tbl_size) {
785 DRM_ERROR("ACPI VFCT image header truncated\n");
786 goto out;
787 }
788
789 offset += vhdr->ImageLength;
790 if (offset > tbl_size) {
791 DRM_ERROR("ACPI VFCT image truncated\n");
792 goto out;
793 }
794
795 if (vhdr->ImageLength &&
796 vhdr->PCIBus == rdev->pdev->bus->number &&
797 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
798 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
799 vhdr->VendorID == rdev->pdev->vendor &&
800 vhdr->DeviceID == rdev->pdev->device) {
801 rdev->bios = kmemdup(&vbios->VbiosContent,
802 vhdr->ImageLength,
803 GFP_KERNEL);
804 if (rdev->bios)
805 r = true;
806
807 goto out;
808 }
809 }
810
811 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
812
813 out:
814 acpi_put_table(hdr);
815 return r;
816 }
817 #else
radeon_acpi_vfct_bios(struct radeon_device * rdev)818 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
819 {
820 return false;
821 }
822 #endif
823
radeon_get_bios(struct radeon_device * rdev)824 bool radeon_get_bios(struct radeon_device *rdev)
825 {
826 bool r;
827 uint16_t tmp;
828
829 r = radeon_atrm_get_bios(rdev);
830 if (!r)
831 r = radeon_acpi_vfct_bios(rdev);
832 if (!r)
833 r = igp_read_bios_from_vram(rdev);
834 if (!r)
835 r = radeon_read_bios(rdev);
836 if (!r)
837 r = radeon_read_disabled_bios(rdev);
838 if (!r)
839 r = radeon_read_platform_bios(rdev);
840 if (!r || rdev->bios == NULL) {
841 DRM_ERROR("Unable to locate a BIOS ROM\n");
842 rdev->bios = NULL;
843 return false;
844 }
845 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
846 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
847 goto free_bios;
848 }
849
850 tmp = RBIOS16(0x18);
851 if (RBIOS8(tmp + 0x14) != 0x0) {
852 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
853 goto free_bios;
854 }
855
856 rdev->bios_header_start = RBIOS16(0x48);
857 if (!rdev->bios_header_start) {
858 goto free_bios;
859 }
860 tmp = rdev->bios_header_start + 4;
861 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
862 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
863 rdev->is_atom_bios = true;
864 } else {
865 rdev->is_atom_bios = false;
866 }
867
868 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
869 return true;
870 free_bios:
871 kfree(rdev->bios);
872 rdev->bios = NULL;
873 return false;
874 }
875