1 /* $NetBSD: radeon_clocks.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: radeon_clocks.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $");
33
34 #include <linux/pci.h>
35
36 #include <drm/drm_device.h>
37 #include <drm/radeon_drm.h>
38
39 #include "atom.h"
40 #include "radeon.h"
41 #include "radeon_asic.h"
42 #include "radeon_reg.h"
43
44 /* 10 khz */
radeon_legacy_get_engine_clock(struct radeon_device * rdev)45 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
46 {
47 struct radeon_pll *spll = &rdev->clock.spll;
48 uint32_t fb_div, ref_div, post_div, sclk;
49
50 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
51 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
52 fb_div <<= 1;
53 fb_div *= spll->reference_freq;
54
55 ref_div =
56 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
57
58 if (ref_div == 0)
59 return 0;
60
61 sclk = fb_div / ref_div;
62
63 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
64 if (post_div == 2)
65 sclk >>= 1;
66 else if (post_div == 3)
67 sclk >>= 2;
68 else if (post_div == 4)
69 sclk >>= 3;
70
71 return sclk;
72 }
73
74 /* 10 khz */
radeon_legacy_get_memory_clock(struct radeon_device * rdev)75 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
76 {
77 struct radeon_pll *mpll = &rdev->clock.mpll;
78 uint32_t fb_div, ref_div, post_div, mclk;
79
80 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
81 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
82 fb_div <<= 1;
83 fb_div *= mpll->reference_freq;
84
85 ref_div =
86 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
87
88 if (ref_div == 0)
89 return 0;
90
91 mclk = fb_div / ref_div;
92
93 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
94 if (post_div == 2)
95 mclk >>= 1;
96 else if (post_div == 3)
97 mclk >>= 2;
98 else if (post_div == 4)
99 mclk >>= 3;
100
101 return mclk;
102 }
103
104 #ifdef CONFIG_OF
105 /*
106 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
107 * tree. Hopefully, ATI OF driver is kind enough to fill these
108 */
radeon_read_clocks_OF(struct drm_device * dev)109 static bool radeon_read_clocks_OF(struct drm_device *dev)
110 {
111 struct radeon_device *rdev = dev->dev_private;
112 struct device_node *dp = rdev->pdev->dev.of_node;
113 const u32 *val;
114 struct radeon_pll *p1pll = &rdev->clock.p1pll;
115 struct radeon_pll *p2pll = &rdev->clock.p2pll;
116 struct radeon_pll *spll = &rdev->clock.spll;
117 struct radeon_pll *mpll = &rdev->clock.mpll;
118
119 if (dp == NULL)
120 return false;
121 val = of_get_property(dp, "ATY,RefCLK", NULL);
122 if (!val || !*val) {
123 pr_warn("radeonfb: No ATY,RefCLK property !\n");
124 return false;
125 }
126 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
127 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
128 if (p1pll->reference_div < 2)
129 p1pll->reference_div = 12;
130 p2pll->reference_div = p1pll->reference_div;
131
132 /* These aren't in the device-tree */
133 if (rdev->family >= CHIP_R420) {
134 p1pll->pll_in_min = 100;
135 p1pll->pll_in_max = 1350;
136 p1pll->pll_out_min = 20000;
137 p1pll->pll_out_max = 50000;
138 p2pll->pll_in_min = 100;
139 p2pll->pll_in_max = 1350;
140 p2pll->pll_out_min = 20000;
141 p2pll->pll_out_max = 50000;
142 } else {
143 p1pll->pll_in_min = 40;
144 p1pll->pll_in_max = 500;
145 p1pll->pll_out_min = 12500;
146 p1pll->pll_out_max = 35000;
147 p2pll->pll_in_min = 40;
148 p2pll->pll_in_max = 500;
149 p2pll->pll_out_min = 12500;
150 p2pll->pll_out_max = 35000;
151 }
152 /* not sure what the max should be in all cases */
153 rdev->clock.max_pixel_clock = 35000;
154
155 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
156 spll->reference_div = mpll->reference_div =
157 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
158 RADEON_M_SPLL_REF_DIV_MASK;
159
160 val = of_get_property(dp, "ATY,SCLK", NULL);
161 if (val && *val)
162 rdev->clock.default_sclk = (*val) / 10;
163 else
164 rdev->clock.default_sclk =
165 radeon_legacy_get_engine_clock(rdev);
166
167 val = of_get_property(dp, "ATY,MCLK", NULL);
168 if (val && *val)
169 rdev->clock.default_mclk = (*val) / 10;
170 else
171 rdev->clock.default_mclk =
172 radeon_legacy_get_memory_clock(rdev);
173
174 DRM_INFO("Using device-tree clock info\n");
175
176 return true;
177 }
178 #else
radeon_read_clocks_OF(struct drm_device * dev)179 static bool radeon_read_clocks_OF(struct drm_device *dev)
180 {
181 return false;
182 }
183 #endif /* CONFIG_OF */
184
radeon_get_clock_info(struct drm_device * dev)185 void radeon_get_clock_info(struct drm_device *dev)
186 {
187 struct radeon_device *rdev = dev->dev_private;
188 struct radeon_pll *p1pll = &rdev->clock.p1pll;
189 struct radeon_pll *p2pll = &rdev->clock.p2pll;
190 struct radeon_pll *dcpll = &rdev->clock.dcpll;
191 struct radeon_pll *spll = &rdev->clock.spll;
192 struct radeon_pll *mpll = &rdev->clock.mpll;
193 int ret;
194
195 if (rdev->is_atom_bios)
196 ret = radeon_atom_get_clock_info(dev);
197 else
198 ret = radeon_combios_get_clock_info(dev);
199 if (!ret)
200 ret = radeon_read_clocks_OF(dev);
201
202 if (ret) {
203 if (p1pll->reference_div < 2) {
204 if (!ASIC_IS_AVIVO(rdev)) {
205 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
206 if (ASIC_IS_R300(rdev))
207 p1pll->reference_div =
208 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
209 else
210 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
211 if (p1pll->reference_div < 2)
212 p1pll->reference_div = 12;
213 } else
214 p1pll->reference_div = 12;
215 }
216 if (p2pll->reference_div < 2)
217 p2pll->reference_div = 12;
218 if (rdev->family < CHIP_RS600) {
219 if (spll->reference_div < 2)
220 spll->reference_div =
221 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
222 RADEON_M_SPLL_REF_DIV_MASK;
223 }
224 if (mpll->reference_div < 2)
225 mpll->reference_div = spll->reference_div;
226 } else {
227 if (ASIC_IS_AVIVO(rdev)) {
228 /* TODO FALLBACK */
229 } else {
230 DRM_INFO("Using generic clock info\n");
231
232 /* may need to be per card */
233 rdev->clock.max_pixel_clock = 35000;
234
235 if (rdev->flags & RADEON_IS_IGP) {
236 p1pll->reference_freq = 1432;
237 p2pll->reference_freq = 1432;
238 spll->reference_freq = 1432;
239 mpll->reference_freq = 1432;
240 } else {
241 p1pll->reference_freq = 2700;
242 p2pll->reference_freq = 2700;
243 spll->reference_freq = 2700;
244 mpll->reference_freq = 2700;
245 }
246 p1pll->reference_div =
247 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
248 if (p1pll->reference_div < 2)
249 p1pll->reference_div = 12;
250 p2pll->reference_div = p1pll->reference_div;
251
252 if (rdev->family >= CHIP_R420) {
253 p1pll->pll_in_min = 100;
254 p1pll->pll_in_max = 1350;
255 p1pll->pll_out_min = 20000;
256 p1pll->pll_out_max = 50000;
257 p2pll->pll_in_min = 100;
258 p2pll->pll_in_max = 1350;
259 p2pll->pll_out_min = 20000;
260 p2pll->pll_out_max = 50000;
261 } else {
262 p1pll->pll_in_min = 40;
263 p1pll->pll_in_max = 500;
264 p1pll->pll_out_min = 12500;
265 p1pll->pll_out_max = 35000;
266 p2pll->pll_in_min = 40;
267 p2pll->pll_in_max = 500;
268 p2pll->pll_out_min = 12500;
269 p2pll->pll_out_max = 35000;
270 }
271
272 spll->reference_div =
273 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
274 RADEON_M_SPLL_REF_DIV_MASK;
275 mpll->reference_div = spll->reference_div;
276 rdev->clock.default_sclk =
277 radeon_legacy_get_engine_clock(rdev);
278 rdev->clock.default_mclk =
279 radeon_legacy_get_memory_clock(rdev);
280 }
281 }
282
283 /* pixel clocks */
284 if (ASIC_IS_AVIVO(rdev)) {
285 p1pll->min_post_div = 2;
286 p1pll->max_post_div = 0x7f;
287 p1pll->min_frac_feedback_div = 0;
288 p1pll->max_frac_feedback_div = 9;
289 p2pll->min_post_div = 2;
290 p2pll->max_post_div = 0x7f;
291 p2pll->min_frac_feedback_div = 0;
292 p2pll->max_frac_feedback_div = 9;
293 } else {
294 p1pll->min_post_div = 1;
295 p1pll->max_post_div = 16;
296 p1pll->min_frac_feedback_div = 0;
297 p1pll->max_frac_feedback_div = 0;
298 p2pll->min_post_div = 1;
299 p2pll->max_post_div = 12;
300 p2pll->min_frac_feedback_div = 0;
301 p2pll->max_frac_feedback_div = 0;
302 }
303
304 /* dcpll is DCE4 only */
305 dcpll->min_post_div = 2;
306 dcpll->max_post_div = 0x7f;
307 dcpll->min_frac_feedback_div = 0;
308 dcpll->max_frac_feedback_div = 9;
309 dcpll->min_ref_div = 2;
310 dcpll->max_ref_div = 0x3ff;
311 dcpll->min_feedback_div = 4;
312 dcpll->max_feedback_div = 0xfff;
313 dcpll->best_vco = 0;
314
315 p1pll->min_ref_div = 2;
316 p1pll->max_ref_div = 0x3ff;
317 p1pll->min_feedback_div = 4;
318 p1pll->max_feedback_div = 0x7ff;
319 p1pll->best_vco = 0;
320
321 p2pll->min_ref_div = 2;
322 p2pll->max_ref_div = 0x3ff;
323 p2pll->min_feedback_div = 4;
324 p2pll->max_feedback_div = 0x7ff;
325 p2pll->best_vco = 0;
326
327 /* system clock */
328 spll->min_post_div = 1;
329 spll->max_post_div = 1;
330 spll->min_ref_div = 2;
331 spll->max_ref_div = 0xff;
332 spll->min_feedback_div = 4;
333 spll->max_feedback_div = 0xff;
334 spll->best_vco = 0;
335
336 /* memory clock */
337 mpll->min_post_div = 1;
338 mpll->max_post_div = 1;
339 mpll->min_ref_div = 2;
340 mpll->max_ref_div = 0xff;
341 mpll->min_feedback_div = 4;
342 mpll->max_feedback_div = 0xff;
343 mpll->best_vco = 0;
344
345 if (!rdev->clock.default_sclk)
346 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
347 if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
348 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
349
350 rdev->pm.current_sclk = rdev->clock.default_sclk;
351 rdev->pm.current_mclk = rdev->clock.default_mclk;
352
353 }
354
355 /* 10 khz */
calc_eng_mem_clock(struct radeon_device * rdev,uint32_t req_clock,int * fb_div,int * post_div)356 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
357 uint32_t req_clock,
358 int *fb_div, int *post_div)
359 {
360 struct radeon_pll *spll = &rdev->clock.spll;
361 int ref_div = spll->reference_div;
362
363 if (!ref_div)
364 ref_div =
365 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
366 RADEON_M_SPLL_REF_DIV_MASK;
367
368 if (req_clock < 15000) {
369 *post_div = 8;
370 req_clock *= 8;
371 } else if (req_clock < 30000) {
372 *post_div = 4;
373 req_clock *= 4;
374 } else if (req_clock < 60000) {
375 *post_div = 2;
376 req_clock *= 2;
377 } else
378 *post_div = 1;
379
380 req_clock *= ref_div;
381 req_clock += spll->reference_freq;
382 req_clock /= (2 * spll->reference_freq);
383
384 *fb_div = req_clock & 0xff;
385
386 req_clock = (req_clock & 0xffff) << 1;
387 req_clock *= spll->reference_freq;
388 req_clock /= ref_div;
389 req_clock /= *post_div;
390
391 return req_clock;
392 }
393
394 /* 10 khz */
radeon_legacy_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)395 void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
396 uint32_t eng_clock)
397 {
398 uint32_t tmp;
399 int fb_div, post_div;
400
401 /* XXX: wait for idle */
402
403 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
404
405 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
406 tmp &= ~RADEON_DONT_USE_XTALIN;
407 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
408
409 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
410 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
411 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
412
413 udelay(10);
414
415 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
416 tmp |= RADEON_SPLL_SLEEP;
417 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
418
419 udelay(2);
420
421 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
422 tmp |= RADEON_SPLL_RESET;
423 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
424
425 udelay(200);
426
427 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
428 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
429 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
430 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
431
432 /* XXX: verify on different asics */
433 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
434 tmp &= ~RADEON_SPLL_PVG_MASK;
435 if ((eng_clock * post_div) >= 90000)
436 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
437 else
438 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
439 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
440
441 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
442 tmp &= ~RADEON_SPLL_SLEEP;
443 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
444
445 udelay(2);
446
447 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
448 tmp &= ~RADEON_SPLL_RESET;
449 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
450
451 udelay(200);
452
453 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
454 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
455 switch (post_div) {
456 case 1:
457 default:
458 tmp |= 1;
459 break;
460 case 2:
461 tmp |= 2;
462 break;
463 case 4:
464 tmp |= 3;
465 break;
466 case 8:
467 tmp |= 4;
468 break;
469 }
470 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
471
472 udelay(20);
473
474 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
475 tmp |= RADEON_DONT_USE_XTALIN;
476 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
477
478 udelay(10);
479 }
480
radeon_legacy_set_clock_gating(struct radeon_device * rdev,int enable)481 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
482 {
483 uint32_t tmp;
484
485 if (enable) {
486 if (rdev->flags & RADEON_SINGLE_CRTC) {
487 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
488 if ((RREG32(RADEON_CONFIG_CNTL) &
489 RADEON_CFG_ATI_REV_ID_MASK) >
490 RADEON_CFG_ATI_REV_A13) {
491 tmp &=
492 ~(RADEON_SCLK_FORCE_CP |
493 RADEON_SCLK_FORCE_RB);
494 }
495 tmp &=
496 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
497 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
498 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
499 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
500 RADEON_SCLK_FORCE_TDM);
501 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
502 } else if (ASIC_IS_R300(rdev)) {
503 if ((rdev->family == CHIP_RS400) ||
504 (rdev->family == CHIP_RS480)) {
505 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
506 tmp &=
507 ~(RADEON_SCLK_FORCE_DISP2 |
508 RADEON_SCLK_FORCE_CP |
509 RADEON_SCLK_FORCE_HDP |
510 RADEON_SCLK_FORCE_DISP1 |
511 RADEON_SCLK_FORCE_TOP |
512 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
513 | RADEON_SCLK_FORCE_IDCT |
514 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
515 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
516 | R300_SCLK_FORCE_US |
517 RADEON_SCLK_FORCE_TV_SCLK |
518 R300_SCLK_FORCE_SU |
519 RADEON_SCLK_FORCE_OV0);
520 tmp |= RADEON_DYN_STOP_LAT_MASK;
521 tmp |=
522 RADEON_SCLK_FORCE_TOP |
523 RADEON_SCLK_FORCE_VIP;
524 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
525
526 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
527 tmp &= ~RADEON_SCLK_MORE_FORCEON;
528 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
529 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
530
531 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
532 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
533 RADEON_PIXCLK_DAC_ALWAYS_ONb);
534 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
535
536 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
537 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
538 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
539 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
540 R300_DVOCLK_ALWAYS_ONb |
541 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
542 RADEON_PIXCLK_GV_ALWAYS_ONb |
543 R300_PIXCLK_DVO_ALWAYS_ONb |
544 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
545 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
546 R300_PIXCLK_TRANS_ALWAYS_ONb |
547 R300_PIXCLK_TVO_ALWAYS_ONb |
548 R300_P2G2CLK_ALWAYS_ONb |
549 R300_P2G2CLK_DAC_ALWAYS_ONb);
550 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
551 } else if (rdev->family >= CHIP_RV350) {
552 tmp = RREG32_PLL(R300_SCLK_CNTL2);
553 tmp &= ~(R300_SCLK_FORCE_TCL |
554 R300_SCLK_FORCE_GA |
555 R300_SCLK_FORCE_CBA);
556 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
557 R300_SCLK_GA_MAX_DYN_STOP_LAT |
558 R300_SCLK_CBA_MAX_DYN_STOP_LAT);
559 WREG32_PLL(R300_SCLK_CNTL2, tmp);
560
561 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
562 tmp &=
563 ~(RADEON_SCLK_FORCE_DISP2 |
564 RADEON_SCLK_FORCE_CP |
565 RADEON_SCLK_FORCE_HDP |
566 RADEON_SCLK_FORCE_DISP1 |
567 RADEON_SCLK_FORCE_TOP |
568 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
569 | RADEON_SCLK_FORCE_IDCT |
570 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
571 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
572 | R300_SCLK_FORCE_US |
573 RADEON_SCLK_FORCE_TV_SCLK |
574 R300_SCLK_FORCE_SU |
575 RADEON_SCLK_FORCE_OV0);
576 tmp |= RADEON_DYN_STOP_LAT_MASK;
577 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
578
579 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
580 tmp &= ~RADEON_SCLK_MORE_FORCEON;
581 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
582 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
583
584 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
585 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
586 RADEON_PIXCLK_DAC_ALWAYS_ONb);
587 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
588
589 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
590 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
591 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
592 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
593 R300_DVOCLK_ALWAYS_ONb |
594 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
595 RADEON_PIXCLK_GV_ALWAYS_ONb |
596 R300_PIXCLK_DVO_ALWAYS_ONb |
597 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
598 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
599 R300_PIXCLK_TRANS_ALWAYS_ONb |
600 R300_PIXCLK_TVO_ALWAYS_ONb |
601 R300_P2G2CLK_ALWAYS_ONb |
602 R300_P2G2CLK_DAC_ALWAYS_ONb);
603 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
604
605 tmp = RREG32_PLL(RADEON_MCLK_MISC);
606 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
607 RADEON_IO_MCLK_DYN_ENABLE);
608 WREG32_PLL(RADEON_MCLK_MISC, tmp);
609
610 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
611 tmp |= (RADEON_FORCEON_MCLKA |
612 RADEON_FORCEON_MCLKB);
613
614 tmp &= ~(RADEON_FORCEON_YCLKA |
615 RADEON_FORCEON_YCLKB |
616 RADEON_FORCEON_MC);
617
618 /* Some releases of vbios have set DISABLE_MC_MCLKA
619 and DISABLE_MC_MCLKB bits in the vbios table. Setting these
620 bits will cause H/W hang when reading video memory with dynamic clocking
621 enabled. */
622 if ((tmp & R300_DISABLE_MC_MCLKA) &&
623 (tmp & R300_DISABLE_MC_MCLKB)) {
624 /* If both bits are set, then check the active channels */
625 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
626 if (rdev->mc.vram_width == 64) {
627 if (RREG32(RADEON_MEM_CNTL) &
628 R300_MEM_USE_CD_CH_ONLY)
629 tmp &=
630 ~R300_DISABLE_MC_MCLKB;
631 else
632 tmp &=
633 ~R300_DISABLE_MC_MCLKA;
634 } else {
635 tmp &= ~(R300_DISABLE_MC_MCLKA |
636 R300_DISABLE_MC_MCLKB);
637 }
638 }
639
640 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
641 } else {
642 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
643 tmp &= ~(R300_SCLK_FORCE_VAP);
644 tmp |= RADEON_SCLK_FORCE_CP;
645 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
646 mdelay(15);
647
648 tmp = RREG32_PLL(R300_SCLK_CNTL2);
649 tmp &= ~(R300_SCLK_FORCE_TCL |
650 R300_SCLK_FORCE_GA |
651 R300_SCLK_FORCE_CBA);
652 WREG32_PLL(R300_SCLK_CNTL2, tmp);
653 }
654 } else {
655 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
656
657 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
658 RADEON_DISP_DYN_STOP_LAT_MASK |
659 RADEON_DYN_STOP_MODE_MASK);
660
661 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
662 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
663 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
664 mdelay(15);
665
666 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
667 tmp |= RADEON_SCLK_DYN_START_CNTL;
668 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
669 mdelay(15);
670
671 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
672 to lockup randomly, leave them as set by BIOS.
673 */
674 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
675 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
676 tmp &= ~RADEON_SCLK_FORCEON_MASK;
677
678 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
679 if (((rdev->family == CHIP_RV250) &&
680 ((RREG32(RADEON_CONFIG_CNTL) &
681 RADEON_CFG_ATI_REV_ID_MASK) <
682 RADEON_CFG_ATI_REV_A13))
683 || ((rdev->family == CHIP_RV100)
684 &&
685 ((RREG32(RADEON_CONFIG_CNTL) &
686 RADEON_CFG_ATI_REV_ID_MASK) <=
687 RADEON_CFG_ATI_REV_A13))) {
688 tmp |= RADEON_SCLK_FORCE_CP;
689 tmp |= RADEON_SCLK_FORCE_VIP;
690 }
691
692 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
693
694 if ((rdev->family == CHIP_RV200) ||
695 (rdev->family == CHIP_RV250) ||
696 (rdev->family == CHIP_RV280)) {
697 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
698 tmp &= ~RADEON_SCLK_MORE_FORCEON;
699
700 /* RV200::A11 A12 RV250::A11 A12 */
701 if (((rdev->family == CHIP_RV200) ||
702 (rdev->family == CHIP_RV250)) &&
703 ((RREG32(RADEON_CONFIG_CNTL) &
704 RADEON_CFG_ATI_REV_ID_MASK) <
705 RADEON_CFG_ATI_REV_A13)) {
706 tmp |= RADEON_SCLK_MORE_FORCEON;
707 }
708 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
709 mdelay(15);
710 }
711
712 /* RV200::A11 A12, RV250::A11 A12 */
713 if (((rdev->family == CHIP_RV200) ||
714 (rdev->family == CHIP_RV250)) &&
715 ((RREG32(RADEON_CONFIG_CNTL) &
716 RADEON_CFG_ATI_REV_ID_MASK) <
717 RADEON_CFG_ATI_REV_A13)) {
718 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
719 tmp |= RADEON_TCL_BYPASS_DISABLE;
720 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
721 }
722 mdelay(15);
723
724 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
725 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
726 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
727 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
728 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
729 RADEON_PIXCLK_GV_ALWAYS_ONb |
730 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
731 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
732 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
733
734 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
735 mdelay(15);
736
737 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
738 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
739 RADEON_PIXCLK_DAC_ALWAYS_ONb);
740
741 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
742 mdelay(15);
743 }
744 } else {
745 /* Turn everything OFF (ForceON to everything) */
746 if (rdev->flags & RADEON_SINGLE_CRTC) {
747 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
748 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
749 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
750 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
751 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
752 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
753 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
754 RADEON_SCLK_FORCE_RB);
755 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
756 } else if ((rdev->family == CHIP_RS400) ||
757 (rdev->family == CHIP_RS480)) {
758 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
759 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
760 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
761 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
762 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
763 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
764 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
765 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
766 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
767 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
768
769 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
770 tmp |= RADEON_SCLK_MORE_FORCEON;
771 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
772
773 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
774 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
775 RADEON_PIXCLK_DAC_ALWAYS_ONb |
776 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
777 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
778
779 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
780 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
781 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
782 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
783 R300_DVOCLK_ALWAYS_ONb |
784 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
785 RADEON_PIXCLK_GV_ALWAYS_ONb |
786 R300_PIXCLK_DVO_ALWAYS_ONb |
787 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
788 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
789 R300_PIXCLK_TRANS_ALWAYS_ONb |
790 R300_PIXCLK_TVO_ALWAYS_ONb |
791 R300_P2G2CLK_ALWAYS_ONb |
792 R300_P2G2CLK_DAC_ALWAYS_ONb |
793 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
794 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
795 } else if (rdev->family >= CHIP_RV350) {
796 /* for RV350/M10, no delays are required. */
797 tmp = RREG32_PLL(R300_SCLK_CNTL2);
798 tmp |= (R300_SCLK_FORCE_TCL |
799 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
800 WREG32_PLL(R300_SCLK_CNTL2, tmp);
801
802 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
803 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
804 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
805 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
806 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
807 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
808 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
809 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
810 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
811 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
812
813 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
814 tmp |= RADEON_SCLK_MORE_FORCEON;
815 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
816
817 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
818 tmp |= (RADEON_FORCEON_MCLKA |
819 RADEON_FORCEON_MCLKB |
820 RADEON_FORCEON_YCLKA |
821 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
822 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
823
824 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
825 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
826 RADEON_PIXCLK_DAC_ALWAYS_ONb |
827 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
828 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
829
830 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
831 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
832 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
833 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
834 R300_DVOCLK_ALWAYS_ONb |
835 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
836 RADEON_PIXCLK_GV_ALWAYS_ONb |
837 R300_PIXCLK_DVO_ALWAYS_ONb |
838 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
839 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
840 R300_PIXCLK_TRANS_ALWAYS_ONb |
841 R300_PIXCLK_TVO_ALWAYS_ONb |
842 R300_P2G2CLK_ALWAYS_ONb |
843 R300_P2G2CLK_DAC_ALWAYS_ONb |
844 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
845 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
846 } else {
847 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
848 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
849 tmp |= RADEON_SCLK_FORCE_SE;
850
851 if (rdev->flags & RADEON_SINGLE_CRTC) {
852 tmp |= (RADEON_SCLK_FORCE_RB |
853 RADEON_SCLK_FORCE_TDM |
854 RADEON_SCLK_FORCE_TAM |
855 RADEON_SCLK_FORCE_PB |
856 RADEON_SCLK_FORCE_RE |
857 RADEON_SCLK_FORCE_VIP |
858 RADEON_SCLK_FORCE_IDCT |
859 RADEON_SCLK_FORCE_TOP |
860 RADEON_SCLK_FORCE_DISP1 |
861 RADEON_SCLK_FORCE_DISP2 |
862 RADEON_SCLK_FORCE_HDP);
863 } else if ((rdev->family == CHIP_R300) ||
864 (rdev->family == CHIP_R350)) {
865 tmp |= (RADEON_SCLK_FORCE_HDP |
866 RADEON_SCLK_FORCE_DISP1 |
867 RADEON_SCLK_FORCE_DISP2 |
868 RADEON_SCLK_FORCE_TOP |
869 RADEON_SCLK_FORCE_IDCT |
870 RADEON_SCLK_FORCE_VIP);
871 }
872 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
873
874 mdelay(16);
875
876 if ((rdev->family == CHIP_R300) ||
877 (rdev->family == CHIP_R350)) {
878 tmp = RREG32_PLL(R300_SCLK_CNTL2);
879 tmp |= (R300_SCLK_FORCE_TCL |
880 R300_SCLK_FORCE_GA |
881 R300_SCLK_FORCE_CBA);
882 WREG32_PLL(R300_SCLK_CNTL2, tmp);
883 mdelay(16);
884 }
885
886 if (rdev->flags & RADEON_IS_IGP) {
887 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
888 tmp &= ~(RADEON_FORCEON_MCLKA |
889 RADEON_FORCEON_YCLKA);
890 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
891 mdelay(16);
892 }
893
894 if ((rdev->family == CHIP_RV200) ||
895 (rdev->family == CHIP_RV250) ||
896 (rdev->family == CHIP_RV280)) {
897 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
898 tmp |= RADEON_SCLK_MORE_FORCEON;
899 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
900 mdelay(16);
901 }
902
903 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
904 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
905 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
906 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
907 RADEON_PIXCLK_GV_ALWAYS_ONb |
908 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
909 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
910 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
911
912 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
913 mdelay(16);
914
915 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
916 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
917 RADEON_PIXCLK_DAC_ALWAYS_ONb);
918 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
919 }
920 }
921 }
922
923