1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/pci.h>
30
31 #include <drm/drm_device.h>
32 #include <drm/radeon_drm.h>
33
34 #include "atom.h"
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "radeon_reg.h"
38
39 #if defined(__macppc__) || defined(__sparc64__)
40 #include <dev/ofw/openfirm.h>
41 #endif
42
43 /* 10 khz */
radeon_legacy_get_engine_clock(struct radeon_device * rdev)44 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
45 {
46 struct radeon_pll *spll = &rdev->clock.spll;
47 uint32_t fb_div, ref_div, post_div, sclk;
48
49 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
50 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
51 fb_div <<= 1;
52 fb_div *= spll->reference_freq;
53
54 ref_div =
55 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
56
57 if (ref_div == 0)
58 return 0;
59
60 sclk = fb_div / ref_div;
61
62 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
63 if (post_div == 2)
64 sclk >>= 1;
65 else if (post_div == 3)
66 sclk >>= 2;
67 else if (post_div == 4)
68 sclk >>= 3;
69
70 return sclk;
71 }
72
73 /* 10 khz */
radeon_legacy_get_memory_clock(struct radeon_device * rdev)74 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
75 {
76 struct radeon_pll *mpll = &rdev->clock.mpll;
77 uint32_t fb_div, ref_div, post_div, mclk;
78
79 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
80 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
81 fb_div <<= 1;
82 fb_div *= mpll->reference_freq;
83
84 ref_div =
85 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
86
87 if (ref_div == 0)
88 return 0;
89
90 mclk = fb_div / ref_div;
91
92 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
93 if (post_div == 2)
94 mclk >>= 1;
95 else if (post_div == 3)
96 mclk >>= 2;
97 else if (post_div == 4)
98 mclk >>= 3;
99
100 return mclk;
101 }
102
103 #ifdef __linux__
104
105 #ifdef CONFIG_OF
106 /*
107 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
108 * tree. Hopefully, ATI OF driver is kind enough to fill these
109 */
radeon_read_clocks_OF(struct drm_device * dev)110 static bool radeon_read_clocks_OF(struct drm_device *dev)
111 {
112 struct radeon_device *rdev = dev->dev_private;
113 struct device_node *dp = rdev->pdev->dev.of_node;
114 const u32 *val;
115 struct radeon_pll *p1pll = &rdev->clock.p1pll;
116 struct radeon_pll *p2pll = &rdev->clock.p2pll;
117 struct radeon_pll *spll = &rdev->clock.spll;
118 struct radeon_pll *mpll = &rdev->clock.mpll;
119
120 if (dp == NULL)
121 return false;
122 val = of_get_property(dp, "ATY,RefCLK", NULL);
123 if (!val || !*val) {
124 pr_warn("radeonfb: No ATY,RefCLK property !\n");
125 return false;
126 }
127 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
128 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
129 if (p1pll->reference_div < 2)
130 p1pll->reference_div = 12;
131 p2pll->reference_div = p1pll->reference_div;
132
133 /* These aren't in the device-tree */
134 if (rdev->family >= CHIP_R420) {
135 p1pll->pll_in_min = 100;
136 p1pll->pll_in_max = 1350;
137 p1pll->pll_out_min = 20000;
138 p1pll->pll_out_max = 50000;
139 p2pll->pll_in_min = 100;
140 p2pll->pll_in_max = 1350;
141 p2pll->pll_out_min = 20000;
142 p2pll->pll_out_max = 50000;
143 } else {
144 p1pll->pll_in_min = 40;
145 p1pll->pll_in_max = 500;
146 p1pll->pll_out_min = 12500;
147 p1pll->pll_out_max = 35000;
148 p2pll->pll_in_min = 40;
149 p2pll->pll_in_max = 500;
150 p2pll->pll_out_min = 12500;
151 p2pll->pll_out_max = 35000;
152 }
153 /* not sure what the max should be in all cases */
154 rdev->clock.max_pixel_clock = 35000;
155
156 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
157 spll->reference_div = mpll->reference_div =
158 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
159 RADEON_M_SPLL_REF_DIV_MASK;
160
161 val = of_get_property(dp, "ATY,SCLK", NULL);
162 if (val && *val)
163 rdev->clock.default_sclk = (*val) / 10;
164 else
165 rdev->clock.default_sclk =
166 radeon_legacy_get_engine_clock(rdev);
167
168 val = of_get_property(dp, "ATY,MCLK", NULL);
169 if (val && *val)
170 rdev->clock.default_mclk = (*val) / 10;
171 else
172 rdev->clock.default_mclk =
173 radeon_legacy_get_memory_clock(rdev);
174
175 DRM_INFO("Using device-tree clock info\n");
176
177 return true;
178 }
179 #else
radeon_read_clocks_OF(struct drm_device * dev)180 static bool radeon_read_clocks_OF(struct drm_device *dev)
181 {
182 return false;
183 }
184 #endif /* CONFIG_OF */
185
186 #else
187
188 #if defined(__macppc__) || defined(__sparc64__)
189 /*
190 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
191 * tree. Hopefully, ATI OF driver is kind enough to fill these
192 */
radeon_read_clocks_OF(struct drm_device * dev)193 static bool radeon_read_clocks_OF(struct drm_device *dev)
194 {
195 struct radeon_device *rdev = dev->dev_private;
196 int node = PCITAG_NODE(rdev->pa_tag);
197 uint32_t val;
198 struct radeon_pll *p1pll = &rdev->clock.p1pll;
199 struct radeon_pll *p2pll = &rdev->clock.p2pll;
200 struct radeon_pll *spll = &rdev->clock.spll;
201 struct radeon_pll *mpll = &rdev->clock.mpll;
202
203 if (OF_getprop(node, "ATY,RefCLK", &val, sizeof(val)) != sizeof(val) || !val)
204 return false;
205 p1pll->reference_freq = p2pll->reference_freq = (val) / 10;
206 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
207 if (p1pll->reference_div < 2)
208 p1pll->reference_div = 12;
209 p2pll->reference_div = p1pll->reference_div;
210
211 /* These aren't in the device-tree */
212 if (rdev->family >= CHIP_R420) {
213 p1pll->pll_in_min = 100;
214 p1pll->pll_in_max = 1350;
215 p1pll->pll_out_min = 20000;
216 p1pll->pll_out_max = 50000;
217 p2pll->pll_in_min = 100;
218 p2pll->pll_in_max = 1350;
219 p2pll->pll_out_min = 20000;
220 p2pll->pll_out_max = 50000;
221 } else {
222 p1pll->pll_in_min = 40;
223 p1pll->pll_in_max = 500;
224 p1pll->pll_out_min = 12500;
225 p1pll->pll_out_max = 35000;
226 p2pll->pll_in_min = 40;
227 p2pll->pll_in_max = 500;
228 p2pll->pll_out_min = 12500;
229 p2pll->pll_out_max = 35000;
230 }
231 /* not sure what the max should be in all cases */
232 rdev->clock.max_pixel_clock = 35000;
233
234 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
235 spll->reference_div = mpll->reference_div =
236 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
237 RADEON_M_SPLL_REF_DIV_MASK;
238
239 if (OF_getprop(node, "ATY,SCLK", &val, sizeof(val)) == sizeof(val) && val)
240 rdev->clock.default_sclk = (val) / 10;
241 else
242 rdev->clock.default_sclk =
243 radeon_legacy_get_engine_clock(rdev);
244
245 if (OF_getprop(node, "ATY,MCLK", &val, sizeof(val)) == sizeof(val) && val)
246 rdev->clock.default_mclk = (val) / 10;
247 else
248 rdev->clock.default_mclk =
249 radeon_legacy_get_memory_clock(rdev);
250
251 DRM_INFO("Using device-tree clock info\n");
252
253 return true;
254 }
255 #else
radeon_read_clocks_OF(struct drm_device * dev)256 static bool radeon_read_clocks_OF(struct drm_device *dev)
257 {
258 return false;
259 }
260 #endif /* CONFIG_OF */
261
262 #endif /* !__linux__ */
263
radeon_get_clock_info(struct drm_device * dev)264 void radeon_get_clock_info(struct drm_device *dev)
265 {
266 struct radeon_device *rdev = dev->dev_private;
267 struct radeon_pll *p1pll = &rdev->clock.p1pll;
268 struct radeon_pll *p2pll = &rdev->clock.p2pll;
269 struct radeon_pll *dcpll = &rdev->clock.dcpll;
270 struct radeon_pll *spll = &rdev->clock.spll;
271 struct radeon_pll *mpll = &rdev->clock.mpll;
272 int ret;
273
274 if (rdev->is_atom_bios)
275 ret = radeon_atom_get_clock_info(dev);
276 else
277 ret = radeon_combios_get_clock_info(dev);
278 if (!ret)
279 ret = radeon_read_clocks_OF(dev);
280
281 if (ret) {
282 if (p1pll->reference_div < 2) {
283 if (!ASIC_IS_AVIVO(rdev)) {
284 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
285 if (ASIC_IS_R300(rdev))
286 p1pll->reference_div =
287 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
288 else
289 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
290 if (p1pll->reference_div < 2)
291 p1pll->reference_div = 12;
292 } else
293 p1pll->reference_div = 12;
294 }
295 if (p2pll->reference_div < 2)
296 p2pll->reference_div = 12;
297 if (rdev->family < CHIP_RS600) {
298 if (spll->reference_div < 2)
299 spll->reference_div =
300 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
301 RADEON_M_SPLL_REF_DIV_MASK;
302 }
303 if (mpll->reference_div < 2)
304 mpll->reference_div = spll->reference_div;
305 } else {
306 if (ASIC_IS_AVIVO(rdev)) {
307 /* TODO FALLBACK */
308 } else {
309 DRM_INFO("Using generic clock info\n");
310
311 /* may need to be per card */
312 rdev->clock.max_pixel_clock = 35000;
313
314 if (rdev->flags & RADEON_IS_IGP) {
315 p1pll->reference_freq = 1432;
316 p2pll->reference_freq = 1432;
317 spll->reference_freq = 1432;
318 mpll->reference_freq = 1432;
319 } else {
320 p1pll->reference_freq = 2700;
321 p2pll->reference_freq = 2700;
322 spll->reference_freq = 2700;
323 mpll->reference_freq = 2700;
324 }
325 p1pll->reference_div =
326 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
327 if (p1pll->reference_div < 2)
328 p1pll->reference_div = 12;
329 p2pll->reference_div = p1pll->reference_div;
330
331 if (rdev->family >= CHIP_R420) {
332 p1pll->pll_in_min = 100;
333 p1pll->pll_in_max = 1350;
334 p1pll->pll_out_min = 20000;
335 p1pll->pll_out_max = 50000;
336 p2pll->pll_in_min = 100;
337 p2pll->pll_in_max = 1350;
338 p2pll->pll_out_min = 20000;
339 p2pll->pll_out_max = 50000;
340 } else {
341 p1pll->pll_in_min = 40;
342 p1pll->pll_in_max = 500;
343 p1pll->pll_out_min = 12500;
344 p1pll->pll_out_max = 35000;
345 p2pll->pll_in_min = 40;
346 p2pll->pll_in_max = 500;
347 p2pll->pll_out_min = 12500;
348 p2pll->pll_out_max = 35000;
349 }
350
351 spll->reference_div =
352 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
353 RADEON_M_SPLL_REF_DIV_MASK;
354 mpll->reference_div = spll->reference_div;
355 rdev->clock.default_sclk =
356 radeon_legacy_get_engine_clock(rdev);
357 rdev->clock.default_mclk =
358 radeon_legacy_get_memory_clock(rdev);
359 }
360 }
361
362 /* pixel clocks */
363 if (ASIC_IS_AVIVO(rdev)) {
364 p1pll->min_post_div = 2;
365 p1pll->max_post_div = 0x7f;
366 p1pll->min_frac_feedback_div = 0;
367 p1pll->max_frac_feedback_div = 9;
368 p2pll->min_post_div = 2;
369 p2pll->max_post_div = 0x7f;
370 p2pll->min_frac_feedback_div = 0;
371 p2pll->max_frac_feedback_div = 9;
372 } else {
373 p1pll->min_post_div = 1;
374 p1pll->max_post_div = 16;
375 p1pll->min_frac_feedback_div = 0;
376 p1pll->max_frac_feedback_div = 0;
377 p2pll->min_post_div = 1;
378 p2pll->max_post_div = 12;
379 p2pll->min_frac_feedback_div = 0;
380 p2pll->max_frac_feedback_div = 0;
381 }
382
383 /* dcpll is DCE4 only */
384 dcpll->min_post_div = 2;
385 dcpll->max_post_div = 0x7f;
386 dcpll->min_frac_feedback_div = 0;
387 dcpll->max_frac_feedback_div = 9;
388 dcpll->min_ref_div = 2;
389 dcpll->max_ref_div = 0x3ff;
390 dcpll->min_feedback_div = 4;
391 dcpll->max_feedback_div = 0xfff;
392 dcpll->best_vco = 0;
393
394 p1pll->min_ref_div = 2;
395 p1pll->max_ref_div = 0x3ff;
396 p1pll->min_feedback_div = 4;
397 p1pll->max_feedback_div = 0x7ff;
398 p1pll->best_vco = 0;
399
400 p2pll->min_ref_div = 2;
401 p2pll->max_ref_div = 0x3ff;
402 p2pll->min_feedback_div = 4;
403 p2pll->max_feedback_div = 0x7ff;
404 p2pll->best_vco = 0;
405
406 /* system clock */
407 spll->min_post_div = 1;
408 spll->max_post_div = 1;
409 spll->min_ref_div = 2;
410 spll->max_ref_div = 0xff;
411 spll->min_feedback_div = 4;
412 spll->max_feedback_div = 0xff;
413 spll->best_vco = 0;
414
415 /* memory clock */
416 mpll->min_post_div = 1;
417 mpll->max_post_div = 1;
418 mpll->min_ref_div = 2;
419 mpll->max_ref_div = 0xff;
420 mpll->min_feedback_div = 4;
421 mpll->max_feedback_div = 0xff;
422 mpll->best_vco = 0;
423
424 if (!rdev->clock.default_sclk)
425 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
426 if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
427 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
428
429 rdev->pm.current_sclk = rdev->clock.default_sclk;
430 rdev->pm.current_mclk = rdev->clock.default_mclk;
431
432 }
433
434 /* 10 khz */
calc_eng_mem_clock(struct radeon_device * rdev,uint32_t req_clock,int * fb_div,int * post_div)435 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
436 uint32_t req_clock,
437 int *fb_div, int *post_div)
438 {
439 struct radeon_pll *spll = &rdev->clock.spll;
440 int ref_div = spll->reference_div;
441
442 if (!ref_div)
443 ref_div =
444 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
445 RADEON_M_SPLL_REF_DIV_MASK;
446
447 if (req_clock < 15000) {
448 *post_div = 8;
449 req_clock *= 8;
450 } else if (req_clock < 30000) {
451 *post_div = 4;
452 req_clock *= 4;
453 } else if (req_clock < 60000) {
454 *post_div = 2;
455 req_clock *= 2;
456 } else
457 *post_div = 1;
458
459 req_clock *= ref_div;
460 req_clock += spll->reference_freq;
461 req_clock /= (2 * spll->reference_freq);
462
463 *fb_div = req_clock & 0xff;
464
465 req_clock = (req_clock & 0xffff) << 1;
466 req_clock *= spll->reference_freq;
467 req_clock /= ref_div;
468 req_clock /= *post_div;
469
470 return req_clock;
471 }
472
473 /* 10 khz */
radeon_legacy_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)474 void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
475 uint32_t eng_clock)
476 {
477 uint32_t tmp;
478 int fb_div, post_div;
479
480 /* XXX: wait for idle */
481
482 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
483
484 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
485 tmp &= ~RADEON_DONT_USE_XTALIN;
486 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
487
488 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
489 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
490 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
491
492 udelay(10);
493
494 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
495 tmp |= RADEON_SPLL_SLEEP;
496 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
497
498 udelay(2);
499
500 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
501 tmp |= RADEON_SPLL_RESET;
502 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
503
504 udelay(200);
505
506 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
507 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
508 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
509 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
510
511 /* XXX: verify on different asics */
512 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
513 tmp &= ~RADEON_SPLL_PVG_MASK;
514 if ((eng_clock * post_div) >= 90000)
515 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
516 else
517 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
518 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
519
520 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
521 tmp &= ~RADEON_SPLL_SLEEP;
522 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
523
524 udelay(2);
525
526 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
527 tmp &= ~RADEON_SPLL_RESET;
528 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
529
530 udelay(200);
531
532 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
533 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
534 switch (post_div) {
535 case 1:
536 default:
537 tmp |= 1;
538 break;
539 case 2:
540 tmp |= 2;
541 break;
542 case 4:
543 tmp |= 3;
544 break;
545 case 8:
546 tmp |= 4;
547 break;
548 }
549 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
550
551 udelay(20);
552
553 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
554 tmp |= RADEON_DONT_USE_XTALIN;
555 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
556
557 udelay(10);
558 }
559
radeon_legacy_set_clock_gating(struct radeon_device * rdev,int enable)560 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
561 {
562 uint32_t tmp;
563
564 if (enable) {
565 if (rdev->flags & RADEON_SINGLE_CRTC) {
566 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
567 if ((RREG32(RADEON_CONFIG_CNTL) &
568 RADEON_CFG_ATI_REV_ID_MASK) >
569 RADEON_CFG_ATI_REV_A13) {
570 tmp &=
571 ~(RADEON_SCLK_FORCE_CP |
572 RADEON_SCLK_FORCE_RB);
573 }
574 tmp &=
575 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
576 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
577 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
578 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
579 RADEON_SCLK_FORCE_TDM);
580 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
581 } else if (ASIC_IS_R300(rdev)) {
582 if ((rdev->family == CHIP_RS400) ||
583 (rdev->family == CHIP_RS480)) {
584 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
585 tmp &=
586 ~(RADEON_SCLK_FORCE_DISP2 |
587 RADEON_SCLK_FORCE_CP |
588 RADEON_SCLK_FORCE_HDP |
589 RADEON_SCLK_FORCE_DISP1 |
590 RADEON_SCLK_FORCE_TOP |
591 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
592 | RADEON_SCLK_FORCE_IDCT |
593 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
594 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
595 | R300_SCLK_FORCE_US |
596 RADEON_SCLK_FORCE_TV_SCLK |
597 R300_SCLK_FORCE_SU |
598 RADEON_SCLK_FORCE_OV0);
599 tmp |= RADEON_DYN_STOP_LAT_MASK;
600 tmp |=
601 RADEON_SCLK_FORCE_TOP |
602 RADEON_SCLK_FORCE_VIP;
603 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
604
605 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
606 tmp &= ~RADEON_SCLK_MORE_FORCEON;
607 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
608 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
609
610 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
611 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
612 RADEON_PIXCLK_DAC_ALWAYS_ONb);
613 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
614
615 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
616 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
617 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
618 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
619 R300_DVOCLK_ALWAYS_ONb |
620 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
621 RADEON_PIXCLK_GV_ALWAYS_ONb |
622 R300_PIXCLK_DVO_ALWAYS_ONb |
623 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
624 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
625 R300_PIXCLK_TRANS_ALWAYS_ONb |
626 R300_PIXCLK_TVO_ALWAYS_ONb |
627 R300_P2G2CLK_ALWAYS_ONb |
628 R300_P2G2CLK_DAC_ALWAYS_ONb);
629 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
630 } else if (rdev->family >= CHIP_RV350) {
631 tmp = RREG32_PLL(R300_SCLK_CNTL2);
632 tmp &= ~(R300_SCLK_FORCE_TCL |
633 R300_SCLK_FORCE_GA |
634 R300_SCLK_FORCE_CBA);
635 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
636 R300_SCLK_GA_MAX_DYN_STOP_LAT |
637 R300_SCLK_CBA_MAX_DYN_STOP_LAT);
638 WREG32_PLL(R300_SCLK_CNTL2, tmp);
639
640 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
641 tmp &=
642 ~(RADEON_SCLK_FORCE_DISP2 |
643 RADEON_SCLK_FORCE_CP |
644 RADEON_SCLK_FORCE_HDP |
645 RADEON_SCLK_FORCE_DISP1 |
646 RADEON_SCLK_FORCE_TOP |
647 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
648 | RADEON_SCLK_FORCE_IDCT |
649 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
650 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
651 | R300_SCLK_FORCE_US |
652 RADEON_SCLK_FORCE_TV_SCLK |
653 R300_SCLK_FORCE_SU |
654 RADEON_SCLK_FORCE_OV0);
655 tmp |= RADEON_DYN_STOP_LAT_MASK;
656 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
657
658 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
659 tmp &= ~RADEON_SCLK_MORE_FORCEON;
660 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
661 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
662
663 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
664 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
665 RADEON_PIXCLK_DAC_ALWAYS_ONb);
666 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
667
668 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
669 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
670 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
671 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
672 R300_DVOCLK_ALWAYS_ONb |
673 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
674 RADEON_PIXCLK_GV_ALWAYS_ONb |
675 R300_PIXCLK_DVO_ALWAYS_ONb |
676 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
677 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
678 R300_PIXCLK_TRANS_ALWAYS_ONb |
679 R300_PIXCLK_TVO_ALWAYS_ONb |
680 R300_P2G2CLK_ALWAYS_ONb |
681 R300_P2G2CLK_DAC_ALWAYS_ONb);
682 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
683
684 tmp = RREG32_PLL(RADEON_MCLK_MISC);
685 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
686 RADEON_IO_MCLK_DYN_ENABLE);
687 WREG32_PLL(RADEON_MCLK_MISC, tmp);
688
689 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
690 tmp |= (RADEON_FORCEON_MCLKA |
691 RADEON_FORCEON_MCLKB);
692
693 tmp &= ~(RADEON_FORCEON_YCLKA |
694 RADEON_FORCEON_YCLKB |
695 RADEON_FORCEON_MC);
696
697 /* Some releases of vbios have set DISABLE_MC_MCLKA
698 and DISABLE_MC_MCLKB bits in the vbios table. Setting these
699 bits will cause H/W hang when reading video memory with dynamic clocking
700 enabled. */
701 if ((tmp & R300_DISABLE_MC_MCLKA) &&
702 (tmp & R300_DISABLE_MC_MCLKB)) {
703 /* If both bits are set, then check the active channels */
704 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
705 if (rdev->mc.vram_width == 64) {
706 if (RREG32(RADEON_MEM_CNTL) &
707 R300_MEM_USE_CD_CH_ONLY)
708 tmp &=
709 ~R300_DISABLE_MC_MCLKB;
710 else
711 tmp &=
712 ~R300_DISABLE_MC_MCLKA;
713 } else {
714 tmp &= ~(R300_DISABLE_MC_MCLKA |
715 R300_DISABLE_MC_MCLKB);
716 }
717 }
718
719 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
720 } else {
721 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
722 tmp &= ~(R300_SCLK_FORCE_VAP);
723 tmp |= RADEON_SCLK_FORCE_CP;
724 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
725 mdelay(15);
726
727 tmp = RREG32_PLL(R300_SCLK_CNTL2);
728 tmp &= ~(R300_SCLK_FORCE_TCL |
729 R300_SCLK_FORCE_GA |
730 R300_SCLK_FORCE_CBA);
731 WREG32_PLL(R300_SCLK_CNTL2, tmp);
732 }
733 } else {
734 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
735
736 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
737 RADEON_DISP_DYN_STOP_LAT_MASK |
738 RADEON_DYN_STOP_MODE_MASK);
739
740 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
741 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
742 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
743 mdelay(15);
744
745 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
746 tmp |= RADEON_SCLK_DYN_START_CNTL;
747 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
748 mdelay(15);
749
750 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
751 to lockup randomly, leave them as set by BIOS.
752 */
753 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
754 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
755 tmp &= ~RADEON_SCLK_FORCEON_MASK;
756
757 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
758 if (((rdev->family == CHIP_RV250) &&
759 ((RREG32(RADEON_CONFIG_CNTL) &
760 RADEON_CFG_ATI_REV_ID_MASK) <
761 RADEON_CFG_ATI_REV_A13))
762 || ((rdev->family == CHIP_RV100)
763 &&
764 ((RREG32(RADEON_CONFIG_CNTL) &
765 RADEON_CFG_ATI_REV_ID_MASK) <=
766 RADEON_CFG_ATI_REV_A13))) {
767 tmp |= RADEON_SCLK_FORCE_CP;
768 tmp |= RADEON_SCLK_FORCE_VIP;
769 }
770
771 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
772
773 if ((rdev->family == CHIP_RV200) ||
774 (rdev->family == CHIP_RV250) ||
775 (rdev->family == CHIP_RV280)) {
776 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
777 tmp &= ~RADEON_SCLK_MORE_FORCEON;
778
779 /* RV200::A11 A12 RV250::A11 A12 */
780 if (((rdev->family == CHIP_RV200) ||
781 (rdev->family == CHIP_RV250)) &&
782 ((RREG32(RADEON_CONFIG_CNTL) &
783 RADEON_CFG_ATI_REV_ID_MASK) <
784 RADEON_CFG_ATI_REV_A13)) {
785 tmp |= RADEON_SCLK_MORE_FORCEON;
786 }
787 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
788 mdelay(15);
789 }
790
791 /* RV200::A11 A12, RV250::A11 A12 */
792 if (((rdev->family == CHIP_RV200) ||
793 (rdev->family == CHIP_RV250)) &&
794 ((RREG32(RADEON_CONFIG_CNTL) &
795 RADEON_CFG_ATI_REV_ID_MASK) <
796 RADEON_CFG_ATI_REV_A13)) {
797 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
798 tmp |= RADEON_TCL_BYPASS_DISABLE;
799 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
800 }
801 mdelay(15);
802
803 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
804 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
805 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
806 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
807 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
808 RADEON_PIXCLK_GV_ALWAYS_ONb |
809 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
810 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
811 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
812
813 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
814 mdelay(15);
815
816 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
817 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
818 RADEON_PIXCLK_DAC_ALWAYS_ONb);
819
820 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
821 mdelay(15);
822 }
823 } else {
824 /* Turn everything OFF (ForceON to everything) */
825 if (rdev->flags & RADEON_SINGLE_CRTC) {
826 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
827 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
828 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
829 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
830 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
831 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
832 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
833 RADEON_SCLK_FORCE_RB);
834 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
835 } else if ((rdev->family == CHIP_RS400) ||
836 (rdev->family == CHIP_RS480)) {
837 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
838 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
839 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
840 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
841 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
842 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
843 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
844 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
845 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
846 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
847
848 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
849 tmp |= RADEON_SCLK_MORE_FORCEON;
850 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
851
852 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
853 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
854 RADEON_PIXCLK_DAC_ALWAYS_ONb |
855 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
856 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
857
858 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
859 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
860 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
861 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
862 R300_DVOCLK_ALWAYS_ONb |
863 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
864 RADEON_PIXCLK_GV_ALWAYS_ONb |
865 R300_PIXCLK_DVO_ALWAYS_ONb |
866 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
867 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
868 R300_PIXCLK_TRANS_ALWAYS_ONb |
869 R300_PIXCLK_TVO_ALWAYS_ONb |
870 R300_P2G2CLK_ALWAYS_ONb |
871 R300_P2G2CLK_DAC_ALWAYS_ONb |
872 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
873 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
874 } else if (rdev->family >= CHIP_RV350) {
875 /* for RV350/M10, no delays are required. */
876 tmp = RREG32_PLL(R300_SCLK_CNTL2);
877 tmp |= (R300_SCLK_FORCE_TCL |
878 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
879 WREG32_PLL(R300_SCLK_CNTL2, tmp);
880
881 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
882 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
883 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
884 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
885 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
886 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
887 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
888 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
889 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
890 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
891
892 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
893 tmp |= RADEON_SCLK_MORE_FORCEON;
894 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
895
896 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
897 tmp |= (RADEON_FORCEON_MCLKA |
898 RADEON_FORCEON_MCLKB |
899 RADEON_FORCEON_YCLKA |
900 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
901 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
902
903 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
904 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
905 RADEON_PIXCLK_DAC_ALWAYS_ONb |
906 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
907 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
908
909 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
910 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
911 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
912 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
913 R300_DVOCLK_ALWAYS_ONb |
914 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
915 RADEON_PIXCLK_GV_ALWAYS_ONb |
916 R300_PIXCLK_DVO_ALWAYS_ONb |
917 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
918 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
919 R300_PIXCLK_TRANS_ALWAYS_ONb |
920 R300_PIXCLK_TVO_ALWAYS_ONb |
921 R300_P2G2CLK_ALWAYS_ONb |
922 R300_P2G2CLK_DAC_ALWAYS_ONb |
923 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
924 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
925 } else {
926 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
927 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
928 tmp |= RADEON_SCLK_FORCE_SE;
929
930 if (rdev->flags & RADEON_SINGLE_CRTC) {
931 tmp |= (RADEON_SCLK_FORCE_RB |
932 RADEON_SCLK_FORCE_TDM |
933 RADEON_SCLK_FORCE_TAM |
934 RADEON_SCLK_FORCE_PB |
935 RADEON_SCLK_FORCE_RE |
936 RADEON_SCLK_FORCE_VIP |
937 RADEON_SCLK_FORCE_IDCT |
938 RADEON_SCLK_FORCE_TOP |
939 RADEON_SCLK_FORCE_DISP1 |
940 RADEON_SCLK_FORCE_DISP2 |
941 RADEON_SCLK_FORCE_HDP);
942 } else if ((rdev->family == CHIP_R300) ||
943 (rdev->family == CHIP_R350)) {
944 tmp |= (RADEON_SCLK_FORCE_HDP |
945 RADEON_SCLK_FORCE_DISP1 |
946 RADEON_SCLK_FORCE_DISP2 |
947 RADEON_SCLK_FORCE_TOP |
948 RADEON_SCLK_FORCE_IDCT |
949 RADEON_SCLK_FORCE_VIP);
950 }
951 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
952
953 mdelay(16);
954
955 if ((rdev->family == CHIP_R300) ||
956 (rdev->family == CHIP_R350)) {
957 tmp = RREG32_PLL(R300_SCLK_CNTL2);
958 tmp |= (R300_SCLK_FORCE_TCL |
959 R300_SCLK_FORCE_GA |
960 R300_SCLK_FORCE_CBA);
961 WREG32_PLL(R300_SCLK_CNTL2, tmp);
962 mdelay(16);
963 }
964
965 if (rdev->flags & RADEON_IS_IGP) {
966 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
967 tmp &= ~(RADEON_FORCEON_MCLKA |
968 RADEON_FORCEON_YCLKA);
969 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
970 mdelay(16);
971 }
972
973 if ((rdev->family == CHIP_RV200) ||
974 (rdev->family == CHIP_RV250) ||
975 (rdev->family == CHIP_RV280)) {
976 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
977 tmp |= RADEON_SCLK_MORE_FORCEON;
978 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
979 mdelay(16);
980 }
981
982 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
983 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
984 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
985 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
986 RADEON_PIXCLK_GV_ALWAYS_ONb |
987 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
988 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
989 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
990
991 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
992 mdelay(16);
993
994 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
995 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
996 RADEON_PIXCLK_DAC_ALWAYS_ONb);
997 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
998 }
999 }
1000 }
1001
1002