1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 *
32 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ttm.c 254885 2013-08-25 19:37:15Z dumbbell $
33 */
34 #include <drm/ttm/ttm_bo_api.h>
35 #include <drm/ttm/ttm_bo_driver.h>
36 #include <drm/ttm/ttm_placement.h>
37 #include <drm/ttm/ttm_module.h>
38 #include <drm/ttm/ttm_page_alloc.h>
39 #include <drm/drmP.h>
40 #include <drm/radeon_drm.h>
41 #include <linux/seq_file.h>
42 #include <linux/slab.h>
43 #include <linux/swap.h>
44 #include <linux/pagemap.h>
45 #include "radeon_reg.h"
46 #include "radeon.h"
47
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
49
50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
52
radeon_get_rdev(struct ttm_bo_device * bdev)53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
54 {
55 struct radeon_mman *mman;
56 struct radeon_device *rdev;
57
58 mman = container_of(bdev, struct radeon_mman, bdev);
59 rdev = container_of(mman, struct radeon_device, mman);
60 return rdev;
61 }
62
63
64 /*
65 * Global memory.
66 */
radeon_ttm_mem_global_init(struct drm_global_reference * ref)67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
68 {
69 return ttm_mem_global_init(ref->object);
70 }
71
radeon_ttm_mem_global_release(struct drm_global_reference * ref)72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
73 {
74 ttm_mem_global_release(ref->object);
75 }
76
radeon_ttm_global_init(struct radeon_device * rdev)77 static int radeon_ttm_global_init(struct radeon_device *rdev)
78 {
79 struct drm_global_reference *global_ref;
80 int r;
81
82 rdev->mman.mem_global_referenced = false;
83 global_ref = &rdev->mman.mem_global_ref;
84 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
85 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &radeon_ttm_mem_global_init;
87 global_ref->release = &radeon_ttm_mem_global_release;
88 r = drm_global_item_ref(global_ref);
89 if (r != 0) {
90 DRM_ERROR("Failed setting up TTM memory accounting "
91 "subsystem.\n");
92 return r;
93 }
94
95 rdev->mman.bo_global_ref.mem_glob =
96 rdev->mman.mem_global_ref.object;
97 global_ref = &rdev->mman.bo_global_ref.ref;
98 global_ref->global_type = DRM_GLOBAL_TTM_BO;
99 global_ref->size = sizeof(struct ttm_bo_global);
100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
102 r = drm_global_item_ref(global_ref);
103 if (r != 0) {
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
105 drm_global_item_unref(&rdev->mman.mem_global_ref);
106 return r;
107 }
108
109 rdev->mman.mem_global_referenced = true;
110 return 0;
111 }
112
radeon_ttm_global_fini(struct radeon_device * rdev)113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
114 {
115 if (rdev->mman.mem_global_referenced) {
116 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&rdev->mman.mem_global_ref);
118 rdev->mman.mem_global_referenced = false;
119 }
120 }
121
radeon_invalidate_caches(struct ttm_bo_device * bdev,uint32_t flags)122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
123 {
124 return 0;
125 }
126
radeon_init_mem_type(struct ttm_bo_device * bdev,uint32_t type,struct ttm_mem_type_manager * man)127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
129 {
130 struct radeon_device *rdev;
131
132 rdev = radeon_get_rdev(bdev);
133
134 switch (type) {
135 case TTM_PL_SYSTEM:
136 /* System memory */
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
140 break;
141 case TTM_PL_TT:
142 man->func = &ttm_bo_manager_func;
143 man->gpu_offset = rdev->mc.gtt_start;
144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
147 #if IS_ENABLED(CONFIG_AGP)
148 if (rdev->flags & RADEON_IS_AGP) {
149 if (!rdev->ddev->agp) {
150 DRM_ERROR("AGP is not enabled for memory type %u\n",
151 (unsigned)type);
152 return -EINVAL;
153 }
154 if (!rdev->ddev->agp->cant_use_aperture)
155 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
156 man->available_caching = TTM_PL_FLAG_UNCACHED |
157 TTM_PL_FLAG_WC;
158 man->default_caching = TTM_PL_FLAG_WC;
159 }
160 #endif
161 break;
162 case TTM_PL_VRAM:
163 /* "On-card" video ram */
164 man->func = &ttm_bo_manager_func;
165 man->gpu_offset = rdev->mc.vram_start;
166 man->flags = TTM_MEMTYPE_FLAG_FIXED |
167 TTM_MEMTYPE_FLAG_MAPPABLE;
168 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
169 man->default_caching = TTM_PL_FLAG_WC;
170 break;
171 default:
172 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
173 return -EINVAL;
174 }
175 return 0;
176 }
177
radeon_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
179 struct ttm_placement *placement)
180 {
181 static const struct ttm_place placements = {
182 .fpfn = 0,
183 .lpfn = 0,
184 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
185 };
186
187 struct radeon_bo *rbo;
188
189 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
190 placement->placement = &placements;
191 placement->busy_placement = &placements;
192 placement->num_placement = 1;
193 placement->num_busy_placement = 1;
194 return;
195 }
196 rbo = container_of(bo, struct radeon_bo, tbo);
197 switch (bo->mem.mem_type) {
198 case TTM_PL_VRAM:
199 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
200 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
201 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
202 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
203 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
204 int i;
205
206 /* Try evicting to the CPU inaccessible part of VRAM
207 * first, but only set GTT as busy placement, so this
208 * BO will be evicted to GTT rather than causing other
209 * BOs to be evicted from VRAM
210 */
211 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
212 RADEON_GEM_DOMAIN_GTT);
213 rbo->placement.num_busy_placement = 0;
214 for (i = 0; i < rbo->placement.num_placement; i++) {
215 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
216 if (rbo->placements[i].fpfn < fpfn)
217 rbo->placements[i].fpfn = fpfn;
218 } else {
219 rbo->placement.busy_placement =
220 &rbo->placements[i];
221 rbo->placement.num_busy_placement = 1;
222 }
223 }
224 } else
225 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
226 break;
227 case TTM_PL_TT:
228 default:
229 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
230 }
231 *placement = rbo->placement;
232 }
233
radeon_verify_access(struct ttm_buffer_object * bo,struct file * filp)234 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
235 {
236 #if 0
237 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
238 #endif
239
240 if (radeon_ttm_tt_has_userptr(bo->ttm))
241 return -EPERM;
242
243 return 0;
244 }
245
radeon_move_null(struct ttm_buffer_object * bo,struct ttm_mem_reg * new_mem)246 static void radeon_move_null(struct ttm_buffer_object *bo,
247 struct ttm_mem_reg *new_mem)
248 {
249 struct ttm_mem_reg *old_mem = &bo->mem;
250
251 BUG_ON(old_mem->mm_node != NULL);
252 *old_mem = *new_mem;
253 new_mem->mm_node = NULL;
254 }
255
radeon_move_blit(struct ttm_buffer_object * bo,bool evict,bool no_wait_gpu,struct ttm_mem_reg * new_mem,struct ttm_mem_reg * old_mem)256 static int radeon_move_blit(struct ttm_buffer_object *bo,
257 bool evict, bool no_wait_gpu,
258 struct ttm_mem_reg *new_mem,
259 struct ttm_mem_reg *old_mem)
260 {
261 struct radeon_device *rdev;
262 uint64_t old_start, new_start;
263 struct radeon_fence *fence;
264 unsigned num_pages;
265 int r, ridx;
266
267 rdev = radeon_get_rdev(bo->bdev);
268 ridx = radeon_copy_ring_index(rdev);
269 old_start = (u64)old_mem->start << PAGE_SHIFT;
270 new_start = (u64)new_mem->start << PAGE_SHIFT;
271
272 switch (old_mem->mem_type) {
273 case TTM_PL_VRAM:
274 old_start += rdev->mc.vram_start;
275 break;
276 case TTM_PL_TT:
277 old_start += rdev->mc.gtt_start;
278 break;
279 default:
280 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
281 return -EINVAL;
282 }
283 switch (new_mem->mem_type) {
284 case TTM_PL_VRAM:
285 new_start += rdev->mc.vram_start;
286 break;
287 case TTM_PL_TT:
288 new_start += rdev->mc.gtt_start;
289 break;
290 default:
291 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
292 return -EINVAL;
293 }
294 if (!rdev->ring[ridx].ready) {
295 DRM_ERROR("Trying to move memory with ring turned off.\n");
296 return -EINVAL;
297 }
298
299 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
300
301 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
302 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
303 if (IS_ERR(fence))
304 return PTR_ERR(fence);
305
306 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem);
307 radeon_fence_unref(&fence);
308 return r;
309 }
310
radeon_move_vram_ram(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_mem_reg * new_mem)311 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
312 bool evict, bool interruptible,
313 bool no_wait_gpu,
314 struct ttm_mem_reg *new_mem)
315 {
316 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
317 struct radeon_device *rdev;
318 struct ttm_mem_reg *old_mem = &bo->mem;
319 struct ttm_mem_reg tmp_mem;
320 struct ttm_place placements;
321 struct ttm_placement placement;
322 int r;
323
324 rdev = radeon_get_rdev(bo->bdev);
325 tmp_mem = *new_mem;
326 tmp_mem.mm_node = NULL;
327 placement.num_placement = 1;
328 placement.placement = &placements;
329 placement.num_busy_placement = 1;
330 placement.busy_placement = &placements;
331 placements.fpfn = 0;
332 placements.lpfn = 0;
333 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
334 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
335 if (unlikely(r)) {
336 return r;
337 }
338
339 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
340 if (unlikely(r)) {
341 goto out_cleanup;
342 }
343
344 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx);
345 if (unlikely(r)) {
346 goto out_cleanup;
347 }
348 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
349 if (unlikely(r)) {
350 goto out_cleanup;
351 }
352 r = ttm_bo_move_ttm(bo, &ctx, new_mem);
353 out_cleanup:
354 ttm_bo_mem_put(bo, &tmp_mem);
355 return r;
356 }
357
radeon_move_ram_vram(struct ttm_buffer_object * bo,bool evict,bool interruptible,bool no_wait_gpu,struct ttm_mem_reg * new_mem)358 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
359 bool evict, bool interruptible,
360 bool no_wait_gpu,
361 struct ttm_mem_reg *new_mem)
362 {
363 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
364 struct radeon_device *rdev;
365 struct ttm_mem_reg *old_mem = &bo->mem;
366 struct ttm_mem_reg tmp_mem;
367 struct ttm_placement placement;
368 struct ttm_place placements;
369 int r;
370
371 rdev = radeon_get_rdev(bo->bdev);
372 tmp_mem = *new_mem;
373 tmp_mem.mm_node = NULL;
374 placement.num_placement = 1;
375 placement.placement = &placements;
376 placement.num_busy_placement = 1;
377 placement.busy_placement = &placements;
378 placements.fpfn = 0;
379 placements.lpfn = 0;
380 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
381 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
382 if (unlikely(r)) {
383 return r;
384 }
385 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem);
386 if (unlikely(r)) {
387 goto out_cleanup;
388 }
389 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
390 if (unlikely(r)) {
391 goto out_cleanup;
392 }
393 out_cleanup:
394 ttm_bo_mem_put(bo, &tmp_mem);
395 return r;
396 }
397
radeon_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_mem_reg * new_mem)398 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
399 struct ttm_operation_ctx *ctx,
400 struct ttm_mem_reg *new_mem)
401 {
402 struct radeon_device *rdev;
403 struct radeon_bo *rbo;
404 struct ttm_mem_reg *old_mem = &bo->mem;
405 int r;
406
407 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
408 if (r)
409 return r;
410
411 /* Can't move a pinned BO */
412 rbo = container_of(bo, struct radeon_bo, tbo);
413 if (WARN_ON_ONCE(rbo->pin_count > 0))
414 return -EINVAL;
415
416 rdev = radeon_get_rdev(bo->bdev);
417 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
418 radeon_move_null(bo, new_mem);
419 return 0;
420 }
421 if ((old_mem->mem_type == TTM_PL_TT &&
422 new_mem->mem_type == TTM_PL_SYSTEM) ||
423 (old_mem->mem_type == TTM_PL_SYSTEM &&
424 new_mem->mem_type == TTM_PL_TT)) {
425 /* bind is enough */
426 radeon_move_null(bo, new_mem);
427 return 0;
428 }
429 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
430 rdev->asic->copy.copy == NULL) {
431 /* use memcpy */
432 goto memcpy;
433 }
434
435 if (old_mem->mem_type == TTM_PL_VRAM &&
436 new_mem->mem_type == TTM_PL_SYSTEM) {
437 r = radeon_move_vram_ram(bo, evict, ctx->interruptible,
438 ctx->no_wait_gpu, new_mem);
439 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
440 new_mem->mem_type == TTM_PL_VRAM) {
441 r = radeon_move_ram_vram(bo, evict, ctx->interruptible,
442 ctx->no_wait_gpu, new_mem);
443 } else {
444 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu,
445 new_mem, old_mem);
446 }
447
448 if (r) {
449 memcpy:
450 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
451 if (r) {
452 return r;
453 }
454 }
455
456 /* update statistics */
457 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
458 return 0;
459 }
460
radeon_ttm_io_mem_reserve(struct ttm_bo_device * bdev,struct ttm_mem_reg * mem)461 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
462 {
463 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
464 struct radeon_device *rdev = radeon_get_rdev(bdev);
465
466 mem->bus.addr = NULL;
467 mem->bus.offset = 0;
468 mem->bus.size = mem->num_pages << PAGE_SHIFT;
469 mem->bus.base = 0;
470 mem->bus.is_iomem = false;
471 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
472 return -EINVAL;
473 switch (mem->mem_type) {
474 case TTM_PL_SYSTEM:
475 /* system memory */
476 return 0;
477 case TTM_PL_TT:
478 #if IS_ENABLED(CONFIG_AGP)
479 if (rdev->flags & RADEON_IS_AGP) {
480 /* RADEON_IS_AGP is set only if AGP is active */
481 mem->bus.offset = mem->start << PAGE_SHIFT;
482 mem->bus.base = rdev->mc.agp_base;
483 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
484 }
485 #endif
486 break;
487 case TTM_PL_VRAM:
488 mem->bus.offset = mem->start << PAGE_SHIFT;
489 /* check if it's visible */
490 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
491 return -EINVAL;
492 mem->bus.base = rdev->mc.aper_base;
493 mem->bus.is_iomem = true;
494 #ifdef __alpha__
495 /*
496 * Alpha: use bus.addr to hold the ioremap() return,
497 * so we can modify bus.base below.
498 */
499 if (mem->placement & TTM_PL_FLAG_WC)
500 mem->bus.addr =
501 ioremap_wc(mem->bus.base + mem->bus.offset,
502 mem->bus.size);
503 else
504 mem->bus.addr =
505 ioremap_nocache(mem->bus.base + mem->bus.offset,
506 mem->bus.size);
507 if (!mem->bus.addr)
508 return -ENOMEM;
509
510 /*
511 * Alpha: Use just the bus offset plus
512 * the hose/domain memory base for bus.base.
513 * It then can be used to build PTEs for VRAM
514 * access, as done in ttm_bo_vm_fault().
515 */
516 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
517 rdev->ddev->hose->dense_mem_base;
518 #endif
519 break;
520 default:
521 return -EINVAL;
522 }
523 return 0;
524 }
525
radeon_ttm_io_mem_free(struct ttm_bo_device * bdev,struct ttm_mem_reg * mem)526 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
527 {
528 }
529
530 /*
531 * TTM backend functions.
532 */
533 struct radeon_ttm_tt {
534 struct ttm_dma_tt ttm;
535 struct radeon_device *rdev;
536 u64 offset;
537
538 uint64_t userptr;
539 struct mm_struct *usermm;
540 uint32_t userflags;
541 };
542
543 #if 0
544 /* prepare the sg table with the user pages */
545 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
546 {
547 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
548 struct radeon_ttm_tt *gtt = (void *)ttm;
549 unsigned pinned = 0, nents;
550 int r;
551
552 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
553 enum dma_data_direction direction = write ?
554 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
555
556 if (current->mm != gtt->usermm)
557 return -EPERM;
558
559 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
560 /* check that we only pin down anonymous memory
561 to prevent problems with writeback */
562 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
563 struct vm_area_struct *vma;
564 vma = find_vma(gtt->usermm, gtt->userptr);
565 if (!vma || vma->vm_file || vma->vm_end < end)
566 return -EPERM;
567 }
568
569 do {
570 unsigned num_pages = ttm->num_pages - pinned;
571 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
572 struct page **pages = ttm->pages + pinned;
573
574 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
575 pages, NULL);
576 if (r < 0)
577 goto release_pages;
578
579 pinned += r;
580
581 } while (pinned < ttm->num_pages);
582
583 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
584 ttm->num_pages << PAGE_SHIFT,
585 GFP_KERNEL);
586 if (r)
587 goto release_sg;
588
589 r = -ENOMEM;
590 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
591 if (nents != ttm->sg->nents)
592 goto release_sg;
593
594 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
595 gtt->ttm.dma_address, ttm->num_pages);
596
597 return 0;
598
599 release_sg:
600 kfree(ttm->sg);
601
602 release_pages:
603 release_pages(ttm->pages, pinned);
604 return r;
605 }
606
607 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
608 {
609 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
610 struct radeon_ttm_tt *gtt = (void *)ttm;
611 struct sg_page_iter sg_iter;
612
613 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
614 enum dma_data_direction direction = write ?
615 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
616
617 /* double check that we don't free the table twice */
618 if (!ttm->sg->sgl)
619 return;
620
621 /* free the sg table and pages again */
622 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
623
624 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
625 struct page *page = sg_page_iter_page(&sg_iter);
626 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
627 set_page_dirty(page);
628
629 mark_page_accessed(page);
630 put_page(page);
631 }
632
633 sg_free_table(ttm->sg);
634 }
635 #endif
636
radeon_ttm_backend_bind(struct ttm_tt * ttm,struct ttm_mem_reg * bo_mem)637 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
638 struct ttm_mem_reg *bo_mem)
639 {
640 struct radeon_ttm_tt *gtt = (void*)ttm;
641 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
642 RADEON_GART_PAGE_WRITE;
643 int r;
644
645 #if 0
646 if (gtt->userptr) {
647 radeon_ttm_tt_pin_userptr(ttm);
648 flags &= ~RADEON_GART_PAGE_WRITE;
649 }
650 #endif
651
652 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
653 if (!ttm->num_pages) {
654 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
655 ttm->num_pages, bo_mem, ttm);
656 }
657 if (ttm->caching_state == tt_cached)
658 flags |= RADEON_GART_PAGE_SNOOP;
659 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
660 ttm->pages, gtt->ttm.dma_address, flags);
661 if (r) {
662 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
663 ttm->num_pages, (unsigned)gtt->offset);
664 return r;
665 }
666 return 0;
667 }
668
radeon_ttm_backend_unbind(struct ttm_tt * ttm)669 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
670 {
671 struct radeon_ttm_tt *gtt = (void *)ttm;
672
673 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
674 #if 0
675 if (gtt->userptr)
676 radeon_ttm_tt_unpin_userptr(ttm);
677 #endif
678
679 return 0;
680 }
681
radeon_ttm_backend_destroy(struct ttm_tt * ttm)682 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
683 {
684 struct radeon_ttm_tt *gtt = (void *)ttm;
685
686 ttm_dma_tt_fini(>t->ttm);
687 kfree(gtt);
688 }
689
690 static struct ttm_backend_func radeon_backend_func = {
691 .bind = &radeon_ttm_backend_bind,
692 .unbind = &radeon_ttm_backend_unbind,
693 .destroy = &radeon_ttm_backend_destroy,
694 };
695
radeon_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)696 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
697 uint32_t page_flags)
698 {
699 struct radeon_device *rdev;
700 struct radeon_ttm_tt *gtt;
701
702 rdev = radeon_get_rdev(bo->bdev);
703 #if IS_ENABLED(CONFIG_AGP)
704 if (rdev->flags & RADEON_IS_AGP) {
705 return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev,
706 size, page_flags, dummy_read_page);
707 }
708 #endif
709
710 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
711 if (gtt == NULL) {
712 return NULL;
713 }
714 gtt->ttm.ttm.func = &radeon_backend_func;
715 gtt->rdev = rdev;
716 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) {
717 kfree(gtt);
718 return NULL;
719 }
720 return >t->ttm.ttm;
721 }
722
radeon_ttm_tt_to_gtt(struct ttm_tt * ttm)723 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
724 {
725 if (!ttm || ttm->func != &radeon_backend_func)
726 return NULL;
727 return (struct radeon_ttm_tt *)ttm;
728 }
729
radeon_ttm_tt_populate(struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)730 static int radeon_ttm_tt_populate(struct ttm_tt *ttm,
731 struct ttm_operation_ctx *ctx)
732 {
733 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
734 struct radeon_device *rdev;
735 unsigned i;
736 int r;
737 #ifdef DUMBBELL_WIP
738 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
739 #endif /* DUMBBELL_WIP */
740
741 if (ttm->state != tt_unpopulated)
742 return 0;
743
744 #if 0
745 if (gtt && gtt->userptr) {
746 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
747 if (!ttm->sg)
748 return -ENOMEM;
749
750 ttm->page_flags |= TTM_PAGE_FLAG_SG;
751 ttm->state = tt_unbound;
752 return 0;
753 }
754 #endif
755
756 #ifdef DUMBBELL_WIP
757 /*
758 * Maybe unneeded on FreeBSD.
759 * -- dumbbell@
760 */
761 if (slave && ttm->sg) {
762 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
763 gtt->ttm.dma_address, ttm->num_pages);
764 ttm->state = tt_unbound;
765 return 0;
766 }
767 #endif /* DUMBBELL_WIP */
768
769 rdev = radeon_get_rdev(ttm->bdev);
770 #if IS_ENABLED(CONFIG_AGP)
771 if (rdev->flags & RADEON_IS_AGP) {
772 return ttm_agp_tt_populate(ttm);
773 }
774 #endif
775
776 #ifdef CONFIG_SWIOTLB
777 if (swiotlb_nr_tbl()) {
778 return ttm_dma_populate(>t->ttm, rdev->dev);
779 }
780 #endif
781
782 r = ttm_pool_populate(ttm, ctx);
783 if (r) {
784 return r;
785 }
786
787 for (i = 0; i < ttm->num_pages; i++) {
788 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
789 0, PAGE_SIZE,
790 PCI_DMA_BIDIRECTIONAL);
791 #ifdef DUMBBELL_WIP
792 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
793 while (i--) {
794 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
795 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
796 gtt->ttm.dma_address[i] = 0;
797 }
798 ttm_pool_unpopulate(ttm);
799 return -EFAULT;
800 }
801 #endif /* DUMBBELL_WIP */
802 }
803 return 0;
804 }
805
radeon_ttm_tt_unpopulate(struct ttm_tt * ttm)806 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
807 {
808 struct radeon_device *rdev;
809 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
810 unsigned i;
811 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
812
813 #if 0
814 if (gtt && gtt->userptr) {
815 kfree(ttm->sg);
816 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
817 return;
818 }
819 #endif
820
821 if (slave)
822 return;
823
824 rdev = radeon_get_rdev(ttm->bdev);
825 #if IS_ENABLED(CONFIG_AGP)
826 if (rdev->flags & RADEON_IS_AGP) {
827 ttm_agp_tt_unpopulate(ttm);
828 return;
829 }
830 #endif
831
832 #ifdef CONFIG_SWIOTLB
833 if (swiotlb_nr_tbl()) {
834 ttm_dma_unpopulate(>t->ttm, rdev->dev);
835 return;
836 }
837 #endif
838
839 for (i = 0; i < ttm->num_pages; i++) {
840 if (gtt->ttm.dma_address[i]) {
841 gtt->ttm.dma_address[i] = 0;
842 #ifdef DUMBBELL_WIP
843 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
844 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
845 #endif /* DUMBBELL_WIP */
846 }
847 }
848
849 ttm_pool_unpopulate(ttm);
850 }
851
radeon_ttm_tt_has_userptr(struct ttm_tt * ttm)852 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
853 {
854 #if 0
855 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
856
857 if (gtt == NULL)
858 #endif
859 return false;
860
861 #if 0
862 return !!gtt->userptr;
863 #endif
864 }
865
radeon_ttm_tt_is_readonly(struct ttm_tt * ttm)866 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
867 {
868 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
869
870 if (gtt == NULL)
871 return false;
872
873 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
874 }
875
radeon_ttm_io_mem_pfn(struct ttm_buffer_object * bo,unsigned long page_offset)876 static unsigned long radeon_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
877 unsigned long page_offset)
878 {
879 return ((bo->mem.bus.base + bo->mem.bus.offset) >> PAGE_SHIFT)
880 + page_offset;
881 }
882
883 static struct ttm_bo_driver radeon_bo_driver = {
884 .ttm_tt_create = &radeon_ttm_tt_create,
885 .ttm_tt_populate = &radeon_ttm_tt_populate,
886 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
887 .invalidate_caches = &radeon_invalidate_caches,
888 .init_mem_type = &radeon_init_mem_type,
889 .eviction_valuable = ttm_bo_eviction_valuable,
890 .evict_flags = &radeon_evict_flags,
891 .move = &radeon_bo_move,
892 .verify_access = &radeon_verify_access,
893 .move_notify = &radeon_bo_move_notify,
894 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
895 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
896 .io_mem_free = &radeon_ttm_io_mem_free,
897 .io_mem_pfn = &radeon_ttm_io_mem_pfn,
898 };
899
radeon_ttm_init(struct radeon_device * rdev)900 int radeon_ttm_init(struct radeon_device *rdev)
901 {
902 int r;
903
904 r = radeon_ttm_global_init(rdev);
905 if (r) {
906 return r;
907 }
908 /* No others user of address space so set it to 0 */
909 r = ttm_bo_device_init(&rdev->mman.bdev,
910 rdev->mman.bo_global_ref.ref.object,
911 &radeon_bo_driver,
912 #ifdef __DragonFly__
913 NULL,
914 #else
915 rdev->ddev->anon_inode->i_mapping,
916 #endif
917 DRM_FILE_PAGE_OFFSET,
918 rdev->need_dma32);
919 if (r) {
920 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
921 return r;
922 }
923 rdev->mman.initialized = true;
924 rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev;
925 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
926 rdev->mc.real_vram_size >> PAGE_SHIFT);
927 if (r) {
928 DRM_ERROR("Failed initializing VRAM heap.\n");
929 return r;
930 }
931 /* Change the size here instead of the init above so only lpfn is affected */
932 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
933
934 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
935 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
936 NULL, &rdev->stolen_vga_memory);
937 if (r) {
938 return r;
939 }
940 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
941 if (r)
942 return r;
943 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
944 radeon_bo_unreserve(rdev->stolen_vga_memory);
945 if (r) {
946 radeon_bo_unref(&rdev->stolen_vga_memory);
947 return r;
948 }
949 DRM_INFO("radeon: %uM of VRAM memory ready\n",
950 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
951 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
952 rdev->mc.gtt_size >> PAGE_SHIFT);
953 if (r) {
954 DRM_ERROR("Failed initializing GTT heap.\n");
955 return r;
956 }
957 DRM_INFO("radeon: %uM of GTT memory ready.\n",
958 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
959
960 r = radeon_ttm_debugfs_init(rdev);
961 if (r) {
962 DRM_ERROR("Failed to init debugfs\n");
963 return r;
964 }
965 return 0;
966 }
967
radeon_ttm_fini(struct radeon_device * rdev)968 void radeon_ttm_fini(struct radeon_device *rdev)
969 {
970 int r;
971
972 if (!rdev->mman.initialized)
973 return;
974 radeon_ttm_debugfs_fini(rdev);
975 if (rdev->stolen_vga_memory) {
976 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
977 if (r == 0) {
978 radeon_bo_unpin(rdev->stolen_vga_memory);
979 radeon_bo_unreserve(rdev->stolen_vga_memory);
980 }
981 radeon_bo_unref(&rdev->stolen_vga_memory);
982 }
983 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
984 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
985 ttm_bo_device_release(&rdev->mman.bdev);
986 radeon_gart_fini(rdev);
987 radeon_ttm_global_fini(rdev);
988 rdev->mman.initialized = false;
989 DRM_INFO("radeon: ttm finalized\n");
990 }
991
992 /* this should only be called at bootup or when userspace
993 * isn't running */
radeon_ttm_set_active_vram_size(struct radeon_device * rdev,u64 size)994 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
995 {
996 struct ttm_mem_type_manager *man;
997
998 if (!rdev->mman.initialized)
999 return;
1000
1001 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
1002 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1003 man->size = size >> PAGE_SHIFT;
1004 }
1005
1006 #ifdef DUMBBELL_WIP
1007 static struct vm_operations_struct radeon_ttm_vm_ops;
1008 static const struct vm_operations_struct *ttm_vm_ops = NULL;
1009
radeon_ttm_fault(struct vm_fault * vmf)1010 static int radeon_ttm_fault(struct vm_fault *vmf)
1011 {
1012 struct ttm_buffer_object *bo;
1013 struct radeon_device *rdev;
1014 int r;
1015
1016 bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data;
1017 if (bo == NULL) {
1018 return VM_FAULT_NOPAGE;
1019 }
1020 rdev = radeon_get_rdev(bo->bdev);
1021 down_read(&rdev->pm.mclk_lock);
1022 r = ttm_vm_ops->fault(vmf);
1023 up_read(&rdev->pm.mclk_lock);
1024 return r;
1025 }
1026
radeon_mmap(struct file * filp,struct vm_area_struct * vma)1027 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
1028 {
1029 struct drm_file *file_priv;
1030 struct radeon_device *rdev;
1031 int r;
1032
1033 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
1034 return -EINVAL;
1035 }
1036
1037 file_priv = filp->private_data;
1038 rdev = file_priv->minor->dev->dev_private;
1039 if (rdev == NULL) {
1040 return -EINVAL;
1041 }
1042 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1043 if (unlikely(r != 0)) {
1044 return r;
1045 }
1046 if (unlikely(ttm_vm_ops == NULL)) {
1047 ttm_vm_ops = vma->vm_ops;
1048 radeon_ttm_vm_ops = *ttm_vm_ops;
1049 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1050 }
1051 vma->vm_ops = &radeon_ttm_vm_ops;
1052 return 0;
1053 }
1054 #endif /* DUMBBELL_WIP */
1055
1056 #if defined(CONFIG_DEBUG_FS)
1057
radeon_mm_dump_table(struct seq_file * m,void * data)1058 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1059 {
1060 struct drm_info_node *node = (struct drm_info_node *)m->private;
1061 unsigned ttm_pl = *(int*)node->info_ent->data;
1062 struct drm_device *dev = node->minor->dev;
1063 struct radeon_device *rdev = dev->dev_private;
1064 struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl];
1065 struct drm_printer p = drm_seq_file_printer(m);
1066
1067 man->func->debug(man, &p);
1068 return 0;
1069 }
1070
1071 static int ttm_pl_vram = TTM_PL_VRAM;
1072 static int ttm_pl_tt = TTM_PL_TT;
1073
1074 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1075 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1076 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1077 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1078 #ifdef CONFIG_SWIOTLB
1079 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1080 #endif
1081 };
1082
radeon_ttm_vram_open(struct inode * inode,struct file * filep)1083 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1084 {
1085 struct radeon_device *rdev = inode->i_private;
1086 i_size_write(inode, rdev->mc.mc_vram_size);
1087 filep->private_data = inode->i_private;
1088 return 0;
1089 }
1090
radeon_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1091 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1092 size_t size, loff_t *pos)
1093 {
1094 struct radeon_device *rdev = f->private_data;
1095 ssize_t result = 0;
1096 int r;
1097
1098 if (size & 0x3 || *pos & 0x3)
1099 return -EINVAL;
1100
1101 while (size) {
1102 unsigned long flags;
1103 uint32_t value;
1104
1105 if (*pos >= rdev->mc.mc_vram_size)
1106 return result;
1107
1108 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1109 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1110 if (rdev->family >= CHIP_CEDAR)
1111 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1112 value = RREG32(RADEON_MM_DATA);
1113 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1114
1115 r = put_user(value, (uint32_t *)buf);
1116 if (r)
1117 return r;
1118
1119 result += 4;
1120 buf += 4;
1121 *pos += 4;
1122 size -= 4;
1123 }
1124
1125 return result;
1126 }
1127
1128 static const struct file_operations radeon_ttm_vram_fops = {
1129 .owner = THIS_MODULE,
1130 .open = radeon_ttm_vram_open,
1131 .read = radeon_ttm_vram_read,
1132 .llseek = default_llseek
1133 };
1134
radeon_ttm_gtt_open(struct inode * inode,struct file * filep)1135 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1136 {
1137 struct radeon_device *rdev = inode->i_private;
1138 i_size_write(inode, rdev->mc.gtt_size);
1139 filep->private_data = inode->i_private;
1140 return 0;
1141 }
1142
radeon_ttm_gtt_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1143 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1144 size_t size, loff_t *pos)
1145 {
1146 struct radeon_device *rdev = f->private_data;
1147 ssize_t result = 0;
1148 int r;
1149
1150 while (size) {
1151 loff_t p = *pos / PAGE_SIZE;
1152 unsigned off = *pos & ~LINUX_PAGE_MASK;
1153 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1154 struct page *page;
1155 void *ptr;
1156
1157 if (p >= rdev->gart.num_cpu_pages)
1158 return result;
1159
1160 page = rdev->gart.pages[p];
1161 if (page) {
1162 ptr = kmap(page);
1163 ptr += off;
1164
1165 r = copy_to_user(buf, ptr, cur_size);
1166 kunmap(rdev->gart.pages[p]);
1167 } else
1168 r = clear_user(buf, cur_size);
1169
1170 if (r)
1171 return -EFAULT;
1172
1173 result += cur_size;
1174 buf += cur_size;
1175 *pos += cur_size;
1176 size -= cur_size;
1177 }
1178
1179 return result;
1180 }
1181
1182 static const struct file_operations radeon_ttm_gtt_fops = {
1183 .owner = THIS_MODULE,
1184 .open = radeon_ttm_gtt_open,
1185 .read = radeon_ttm_gtt_read,
1186 .llseek = default_llseek
1187 };
1188
1189 #endif
1190
radeon_ttm_debugfs_init(struct radeon_device * rdev)1191 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1192 {
1193 #if defined(CONFIG_DEBUG_FS)
1194 unsigned count;
1195
1196 struct drm_minor *minor = rdev->ddev->primary;
1197 struct dentry *ent, *root = minor->debugfs_root;
1198
1199 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1200 rdev, &radeon_ttm_vram_fops);
1201 if (IS_ERR(ent))
1202 return PTR_ERR(ent);
1203 rdev->mman.vram = ent;
1204
1205 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1206 rdev, &radeon_ttm_gtt_fops);
1207 if (IS_ERR(ent))
1208 return PTR_ERR(ent);
1209 rdev->mman.gtt = ent;
1210
1211 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1212
1213 #ifdef CONFIG_SWIOTLB
1214 if (!swiotlb_nr_tbl())
1215 --count;
1216 #endif
1217
1218 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1219 #else
1220
1221 return 0;
1222 #endif
1223 }
1224
radeon_ttm_debugfs_fini(struct radeon_device * rdev)1225 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1226 {
1227 #if defined(CONFIG_DEBUG_FS)
1228
1229 debugfs_remove(rdev->mman.vram);
1230 rdev->mman.vram = NULL;
1231
1232 debugfs_remove(rdev->mman.gtt);
1233 rdev->mman.gtt = NULL;
1234 #endif
1235 }
1236