xref: /openbsd/sys/dev/pci/drm/radeon/radeon_ttm.c (revision f005ef32)
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 
33 #include <linux/dma-mapping.h>
34 #include <linux/pagemap.h>
35 #include <linux/pci.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 
40 #include <drm/drm_device.h>
41 #include <drm/drm_file.h>
42 #include <drm/drm_prime.h>
43 #include <drm/radeon_drm.h>
44 #include <drm/ttm/ttm_bo.h>
45 #include <drm/ttm/ttm_placement.h>
46 #include <drm/ttm/ttm_range_manager.h>
47 #include <drm/ttm/ttm_tt.h>
48 
49 #include "radeon_reg.h"
50 #include "radeon.h"
51 #include "radeon_ttm.h"
52 
53 #ifdef __amd64__
54 #include "efifb.h"
55 #endif
56 
57 #if NEFIFB > 0
58 #include <machine/efifbvar.h>
59 #endif
60 
61 static void radeon_ttm_debugfs_init(struct radeon_device *rdev);
62 
63 static int radeon_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
64 			      struct ttm_resource *bo_mem);
65 static void radeon_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
66 
radeon_get_rdev(struct ttm_device * bdev)67 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev)
68 {
69 	struct radeon_mman *mman;
70 	struct radeon_device *rdev;
71 
72 	mman = container_of(bdev, struct radeon_mman, bdev);
73 	rdev = container_of(mman, struct radeon_device, mman);
74 	return rdev;
75 }
76 
radeon_ttm_init_vram(struct radeon_device * rdev)77 static int radeon_ttm_init_vram(struct radeon_device *rdev)
78 {
79 	return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
80 				  false, rdev->mc.real_vram_size >> PAGE_SHIFT);
81 }
82 
radeon_ttm_init_gtt(struct radeon_device * rdev)83 static int radeon_ttm_init_gtt(struct radeon_device *rdev)
84 {
85 	return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
86 				  true, rdev->mc.gtt_size >> PAGE_SHIFT);
87 }
88 
radeon_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)89 static void radeon_evict_flags(struct ttm_buffer_object *bo,
90 				struct ttm_placement *placement)
91 {
92 	static const struct ttm_place placements = {
93 		.fpfn = 0,
94 		.lpfn = 0,
95 		.mem_type = TTM_PL_SYSTEM,
96 		.flags = 0
97 	};
98 
99 	struct radeon_bo *rbo;
100 
101 	if (!radeon_ttm_bo_is_radeon_bo(bo)) {
102 		placement->placement = &placements;
103 		placement->busy_placement = &placements;
104 		placement->num_placement = 1;
105 		placement->num_busy_placement = 1;
106 		return;
107 	}
108 	rbo = container_of(bo, struct radeon_bo, tbo);
109 	switch (bo->resource->mem_type) {
110 	case TTM_PL_VRAM:
111 		if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
112 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
113 		else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
114 			 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
115 			unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
116 			int i;
117 
118 			/* Try evicting to the CPU inaccessible part of VRAM
119 			 * first, but only set GTT as busy placement, so this
120 			 * BO will be evicted to GTT rather than causing other
121 			 * BOs to be evicted from VRAM
122 			 */
123 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
124 							 RADEON_GEM_DOMAIN_GTT);
125 			rbo->placement.num_busy_placement = 0;
126 			for (i = 0; i < rbo->placement.num_placement; i++) {
127 				if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
128 					if (rbo->placements[i].fpfn < fpfn)
129 						rbo->placements[i].fpfn = fpfn;
130 				} else {
131 					rbo->placement.busy_placement =
132 						&rbo->placements[i];
133 					rbo->placement.num_busy_placement = 1;
134 				}
135 			}
136 		} else
137 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
138 		break;
139 	case TTM_PL_TT:
140 	default:
141 		radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
142 	}
143 	*placement = rbo->placement;
144 }
145 
radeon_move_blit(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_mem,struct ttm_resource * old_mem)146 static int radeon_move_blit(struct ttm_buffer_object *bo,
147 			bool evict,
148 			struct ttm_resource *new_mem,
149 			struct ttm_resource *old_mem)
150 {
151 	struct radeon_device *rdev;
152 	uint64_t old_start, new_start;
153 	struct radeon_fence *fence;
154 	unsigned num_pages;
155 	int r, ridx;
156 
157 	rdev = radeon_get_rdev(bo->bdev);
158 	ridx = radeon_copy_ring_index(rdev);
159 	old_start = (u64)old_mem->start << PAGE_SHIFT;
160 	new_start = (u64)new_mem->start << PAGE_SHIFT;
161 
162 	switch (old_mem->mem_type) {
163 	case TTM_PL_VRAM:
164 		old_start += rdev->mc.vram_start;
165 		break;
166 	case TTM_PL_TT:
167 		old_start += rdev->mc.gtt_start;
168 		break;
169 	default:
170 		DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
171 		return -EINVAL;
172 	}
173 	switch (new_mem->mem_type) {
174 	case TTM_PL_VRAM:
175 		new_start += rdev->mc.vram_start;
176 		break;
177 	case TTM_PL_TT:
178 		new_start += rdev->mc.gtt_start;
179 		break;
180 	default:
181 		DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
182 		return -EINVAL;
183 	}
184 	if (!rdev->ring[ridx].ready) {
185 		DRM_ERROR("Trying to move memory with ring turned off.\n");
186 		return -EINVAL;
187 	}
188 
189 	BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
190 
191 	num_pages = PFN_UP(new_mem->size) * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
192 	fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
193 	if (IS_ERR(fence))
194 		return PTR_ERR(fence);
195 
196 	r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
197 	radeon_fence_unref(&fence);
198 	return r;
199 }
200 
radeon_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_mem,struct ttm_place * hop)201 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
202 			  struct ttm_operation_ctx *ctx,
203 			  struct ttm_resource *new_mem,
204 			  struct ttm_place *hop)
205 {
206 	struct ttm_resource *old_mem = bo->resource;
207 	struct radeon_device *rdev;
208 	struct radeon_bo *rbo;
209 	int r;
210 
211 	if (new_mem->mem_type == TTM_PL_TT) {
212 		r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem);
213 		if (r)
214 			return r;
215 	}
216 
217 	r = ttm_bo_wait_ctx(bo, ctx);
218 	if (r)
219 		return r;
220 
221 	rbo = container_of(bo, struct radeon_bo, tbo);
222 	rdev = radeon_get_rdev(bo->bdev);
223 	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
224 			 bo->ttm == NULL)) {
225 		ttm_bo_move_null(bo, new_mem);
226 		goto out;
227 	}
228 	if (old_mem->mem_type == TTM_PL_SYSTEM &&
229 	    new_mem->mem_type == TTM_PL_TT) {
230 		ttm_bo_move_null(bo, new_mem);
231 		goto out;
232 	}
233 
234 	if (old_mem->mem_type == TTM_PL_TT &&
235 	    new_mem->mem_type == TTM_PL_SYSTEM) {
236 		radeon_ttm_tt_unbind(bo->bdev, bo->ttm);
237 		ttm_resource_free(bo, &bo->resource);
238 		ttm_bo_assign_mem(bo, new_mem);
239 		goto out;
240 	}
241 	if (rdev->ring[radeon_copy_ring_index(rdev)].ready &&
242 	    rdev->asic->copy.copy != NULL) {
243 		if ((old_mem->mem_type == TTM_PL_SYSTEM &&
244 		     new_mem->mem_type == TTM_PL_VRAM) ||
245 		    (old_mem->mem_type == TTM_PL_VRAM &&
246 		     new_mem->mem_type == TTM_PL_SYSTEM)) {
247 			hop->fpfn = 0;
248 			hop->lpfn = 0;
249 			hop->mem_type = TTM_PL_TT;
250 			hop->flags = 0;
251 			return -EMULTIHOP;
252 		}
253 
254 		r = radeon_move_blit(bo, evict, new_mem, old_mem);
255 	} else {
256 		r = -ENODEV;
257 	}
258 
259 	if (r) {
260 		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
261 		if (r)
262 			return r;
263 	}
264 
265 out:
266 	/* update statistics */
267 	atomic64_add(bo->base.size, &rdev->num_bytes_moved);
268 	radeon_bo_move_notify(bo);
269 	return 0;
270 }
271 
radeon_ttm_io_mem_reserve(struct ttm_device * bdev,struct ttm_resource * mem)272 static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
273 {
274 	struct radeon_device *rdev = radeon_get_rdev(bdev);
275 	size_t bus_size = (size_t)mem->size;
276 
277 	switch (mem->mem_type) {
278 	case TTM_PL_SYSTEM:
279 		/* system memory */
280 		return 0;
281 	case TTM_PL_TT:
282 #if IS_ENABLED(CONFIG_AGP)
283 		if (rdev->flags & RADEON_IS_AGP) {
284 			/* RADEON_IS_AGP is set only if AGP is active */
285 			mem->bus.offset = (mem->start << PAGE_SHIFT) +
286 				rdev->mc.agp_base;
287 			mem->bus.is_iomem = !rdev->agp->cant_use_aperture;
288 			mem->bus.caching = ttm_write_combined;
289 		}
290 #endif
291 		break;
292 	case TTM_PL_VRAM:
293 		mem->bus.offset = mem->start << PAGE_SHIFT;
294 		/* check if it's visible */
295 		if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
296 			return -EINVAL;
297 		mem->bus.offset += rdev->mc.aper_base;
298 		mem->bus.is_iomem = true;
299 		mem->bus.caching = ttm_write_combined;
300 #ifdef __alpha__
301 		/*
302 		 * Alpha: use bus.addr to hold the ioremap() return,
303 		 * so we can modify bus.base below.
304 		 */
305 		mem->bus.addr = ioremap_wc(mem->bus.offset, bus_size);
306 		if (!mem->bus.addr)
307 			return -ENOMEM;
308 
309 		/*
310 		 * Alpha: Use just the bus offset plus
311 		 * the hose/domain memory base for bus.base.
312 		 * It then can be used to build PTEs for VRAM
313 		 * access, as done in ttm_bo_vm_fault().
314 		 */
315 		mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
316 			rdev->hose->dense_mem_base;
317 #endif
318 		break;
319 	default:
320 		return -EINVAL;
321 	}
322 	return 0;
323 }
324 
325 /*
326  * TTM backend functions.
327  */
328 struct radeon_ttm_tt {
329 	struct ttm_tt		ttm;
330 	u64				offset;
331 
332 	uint64_t			userptr;
333 	struct mm_struct		*usermm;
334 	uint32_t			userflags;
335 	bool bound;
336 };
337 
338 /* prepare the sg table with the user pages */
radeon_ttm_tt_pin_userptr(struct ttm_device * bdev,struct ttm_tt * ttm)339 static int radeon_ttm_tt_pin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
340 {
341 	STUB();
342 	return -ENOSYS;
343 #ifdef notyet
344 	struct radeon_device *rdev = radeon_get_rdev(bdev);
345 	struct radeon_ttm_tt *gtt = (void *)ttm;
346 	unsigned pinned = 0;
347 	int r;
348 
349 	int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
350 	enum dma_data_direction direction = write ?
351 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
352 
353 	if (current->mm != gtt->usermm)
354 		return -EPERM;
355 
356 	if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
357 		/* check that we only pin down anonymous memory
358 		   to prevent problems with writeback */
359 		unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;
360 		struct vm_area_struct *vma;
361 		vma = find_vma(gtt->usermm, gtt->userptr);
362 		if (!vma || vma->vm_file || vma->vm_end < end)
363 			return -EPERM;
364 	}
365 
366 	do {
367 		unsigned num_pages = ttm->num_pages - pinned;
368 		uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
369 		struct vm_page **pages = ttm->pages + pinned;
370 
371 		r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
372 				   pages);
373 		if (r < 0)
374 			goto release_pages;
375 
376 		pinned += r;
377 
378 	} while (pinned < ttm->num_pages);
379 
380 	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
381 				      (u64)ttm->num_pages << PAGE_SHIFT,
382 				      GFP_KERNEL);
383 	if (r)
384 		goto release_sg;
385 
386 	r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0);
387 	if (r)
388 		goto release_sg;
389 
390 	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
391 				       ttm->num_pages);
392 
393 	return 0;
394 
395 release_sg:
396 	kfree(ttm->sg);
397 
398 release_pages:
399 	release_pages(ttm->pages, pinned);
400 	return r;
401 #endif
402 }
403 
radeon_ttm_tt_unpin_userptr(struct ttm_device * bdev,struct ttm_tt * ttm)404 static void radeon_ttm_tt_unpin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
405 {
406 	STUB();
407 #ifdef notyet
408 	struct radeon_device *rdev = radeon_get_rdev(bdev);
409 	struct radeon_ttm_tt *gtt = (void *)ttm;
410 	struct sg_page_iter sg_iter;
411 
412 	int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
413 	enum dma_data_direction direction = write ?
414 		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
415 
416 	/* double check that we don't free the table twice */
417 	if (!ttm->sg || !ttm->sg->sgl)
418 		return;
419 
420 	/* free the sg table and pages again */
421 	dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0);
422 
423 	for_each_sgtable_page(ttm->sg, &sg_iter, 0) {
424 		struct vm_page *page = sg_page_iter_page(&sg_iter);
425 		if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
426 			set_page_dirty(page);
427 
428 		mark_page_accessed(page);
429 		put_page(page);
430 	}
431 
432 	sg_free_table(ttm->sg);
433 #endif
434 }
435 
radeon_ttm_backend_is_bound(struct ttm_tt * ttm)436 static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
437 {
438 	struct radeon_ttm_tt *gtt = (void*)ttm;
439 
440 	return (gtt->bound);
441 }
442 
radeon_ttm_backend_bind(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_resource * bo_mem)443 static int radeon_ttm_backend_bind(struct ttm_device *bdev,
444 				   struct ttm_tt *ttm,
445 				   struct ttm_resource *bo_mem)
446 {
447 	struct radeon_ttm_tt *gtt = (void*)ttm;
448 	struct radeon_device *rdev = radeon_get_rdev(bdev);
449 	uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
450 		RADEON_GART_PAGE_WRITE;
451 	int r;
452 
453 	if (gtt->bound)
454 		return 0;
455 
456 	if (gtt->userptr) {
457 		radeon_ttm_tt_pin_userptr(bdev, ttm);
458 		flags &= ~RADEON_GART_PAGE_WRITE;
459 	}
460 
461 	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
462 	if (!ttm->num_pages) {
463 		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
464 		     ttm->num_pages, bo_mem, ttm);
465 	}
466 	if (ttm->caching == ttm_cached)
467 		flags |= RADEON_GART_PAGE_SNOOP;
468 	r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages,
469 			     ttm->pages, gtt->ttm.dma_address, flags);
470 	if (r) {
471 		DRM_ERROR("failed to bind %u pages at 0x%08X\n",
472 			  ttm->num_pages, (unsigned)gtt->offset);
473 		return r;
474 	}
475 	gtt->bound = true;
476 	return 0;
477 }
478 
radeon_ttm_backend_unbind(struct ttm_device * bdev,struct ttm_tt * ttm)479 static void radeon_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
480 {
481 	struct radeon_ttm_tt *gtt = (void *)ttm;
482 	struct radeon_device *rdev = radeon_get_rdev(bdev);
483 
484 	if (gtt->userptr)
485 		radeon_ttm_tt_unpin_userptr(bdev, ttm);
486 
487 	if (!gtt->bound)
488 		return;
489 
490 	radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages);
491 
492 	gtt->bound = false;
493 }
494 
radeon_ttm_backend_destroy(struct ttm_device * bdev,struct ttm_tt * ttm)495 static void radeon_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *ttm)
496 {
497 	struct radeon_ttm_tt *gtt = (void *)ttm;
498 
499 	ttm_tt_fini(&gtt->ttm);
500 	kfree(gtt);
501 }
502 
radeon_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)503 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
504 					   uint32_t page_flags)
505 {
506 	struct radeon_ttm_tt *gtt;
507 	enum ttm_caching caching;
508 	struct radeon_bo *rbo;
509 #if IS_ENABLED(CONFIG_AGP)
510 	struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
511 
512 	if (rdev->flags & RADEON_IS_AGP) {
513 		return ttm_agp_tt_create(bo, rdev->agp->bridge, page_flags);
514 	}
515 #endif
516 	rbo = container_of(bo, struct radeon_bo, tbo);
517 
518 	gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
519 	if (gtt == NULL) {
520 		return NULL;
521 	}
522 
523 	if (rbo->flags & RADEON_GEM_GTT_UC)
524 		caching = ttm_uncached;
525 	else if (rbo->flags & RADEON_GEM_GTT_WC)
526 		caching = ttm_write_combined;
527 	else
528 		caching = ttm_cached;
529 
530 	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
531 		kfree(gtt);
532 		return NULL;
533 	}
534 	return &gtt->ttm;
535 }
536 
radeon_ttm_tt_to_gtt(struct radeon_device * rdev,struct ttm_tt * ttm)537 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev,
538 						  struct ttm_tt *ttm)
539 {
540 #if IS_ENABLED(CONFIG_AGP)
541 	if (rdev->flags & RADEON_IS_AGP)
542 		return NULL;
543 #endif
544 
545 	if (!ttm)
546 		return NULL;
547 	return container_of(ttm, struct radeon_ttm_tt, ttm);
548 }
549 
radeon_ttm_tt_populate(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)550 static int radeon_ttm_tt_populate(struct ttm_device *bdev,
551 				  struct ttm_tt *ttm,
552 				  struct ttm_operation_ctx *ctx)
553 {
554 	struct radeon_device *rdev = radeon_get_rdev(bdev);
555 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
556 	bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
557 
558 	if (gtt && gtt->userptr) {
559 		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
560 		if (!ttm->sg)
561 			return -ENOMEM;
562 
563 		ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
564 		return 0;
565 	}
566 
567 	if (slave && ttm->sg) {
568 		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
569 					       ttm->num_pages);
570 		return 0;
571 	}
572 
573 	return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx);
574 }
575 
radeon_ttm_tt_unpopulate(struct ttm_device * bdev,struct ttm_tt * ttm)576 static void radeon_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)
577 {
578 	struct radeon_device *rdev = radeon_get_rdev(bdev);
579 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
580 	bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
581 
582 	radeon_ttm_tt_unbind(bdev, ttm);
583 
584 	if (gtt && gtt->userptr) {
585 		kfree(ttm->sg);
586 		ttm->page_flags &= ~TTM_TT_FLAG_EXTERNAL;
587 		return;
588 	}
589 
590 	if (slave)
591 		return;
592 
593 	return ttm_pool_free(&rdev->mman.bdev.pool, ttm);
594 }
595 
radeon_ttm_tt_set_userptr(struct radeon_device * rdev,struct ttm_tt * ttm,uint64_t addr,uint32_t flags)596 int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
597 			      struct ttm_tt *ttm, uint64_t addr,
598 			      uint32_t flags)
599 {
600 	STUB();
601 	return -ENOSYS;
602 #ifdef notyet
603 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
604 
605 	if (gtt == NULL)
606 		return -EINVAL;
607 
608 	gtt->userptr = addr;
609 	gtt->usermm = current->mm;
610 	gtt->userflags = flags;
611 	return 0;
612 #endif
613 }
614 
radeon_ttm_tt_is_bound(struct ttm_device * bdev,struct ttm_tt * ttm)615 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev,
616 			    struct ttm_tt *ttm)
617 {
618 #if IS_ENABLED(CONFIG_AGP)
619 	struct radeon_device *rdev = radeon_get_rdev(bdev);
620 	if (rdev->flags & RADEON_IS_AGP)
621 		return ttm_agp_is_bound(ttm);
622 #endif
623 	return radeon_ttm_backend_is_bound(ttm);
624 }
625 
radeon_ttm_tt_bind(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_resource * bo_mem)626 static int radeon_ttm_tt_bind(struct ttm_device *bdev,
627 			      struct ttm_tt *ttm,
628 			      struct ttm_resource *bo_mem)
629 {
630 #if IS_ENABLED(CONFIG_AGP)
631 	struct radeon_device *rdev = radeon_get_rdev(bdev);
632 #endif
633 
634 	if (!bo_mem)
635 		return -EINVAL;
636 #if IS_ENABLED(CONFIG_AGP)
637 	if (rdev->flags & RADEON_IS_AGP)
638 		return ttm_agp_bind(ttm, bo_mem);
639 #endif
640 
641 	return radeon_ttm_backend_bind(bdev, ttm, bo_mem);
642 }
643 
radeon_ttm_tt_unbind(struct ttm_device * bdev,struct ttm_tt * ttm)644 static void radeon_ttm_tt_unbind(struct ttm_device *bdev,
645 				 struct ttm_tt *ttm)
646 {
647 #if IS_ENABLED(CONFIG_AGP)
648 	struct radeon_device *rdev = radeon_get_rdev(bdev);
649 
650 	if (rdev->flags & RADEON_IS_AGP) {
651 		ttm_agp_unbind(ttm);
652 		return;
653 	}
654 #endif
655 	radeon_ttm_backend_unbind(bdev, ttm);
656 }
657 
radeon_ttm_tt_destroy(struct ttm_device * bdev,struct ttm_tt * ttm)658 static void radeon_ttm_tt_destroy(struct ttm_device *bdev,
659 				  struct ttm_tt *ttm)
660 {
661 #if IS_ENABLED(CONFIG_AGP)
662 	struct radeon_device *rdev = radeon_get_rdev(bdev);
663 
664 	if (rdev->flags & RADEON_IS_AGP) {
665 		ttm_agp_destroy(ttm);
666 		return;
667 	}
668 #endif
669 	radeon_ttm_backend_destroy(bdev, ttm);
670 }
671 
radeon_ttm_tt_has_userptr(struct radeon_device * rdev,struct ttm_tt * ttm)672 bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
673 			       struct ttm_tt *ttm)
674 {
675 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
676 
677 	if (gtt == NULL)
678 		return false;
679 
680 	return !!gtt->userptr;
681 }
682 
radeon_ttm_tt_is_readonly(struct radeon_device * rdev,struct ttm_tt * ttm)683 bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
684 			       struct ttm_tt *ttm)
685 {
686 	struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
687 
688 	if (gtt == NULL)
689 		return false;
690 
691 	return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
692 }
693 
694 static struct ttm_device_funcs radeon_bo_driver = {
695 	.ttm_tt_create = &radeon_ttm_tt_create,
696 	.ttm_tt_populate = &radeon_ttm_tt_populate,
697 	.ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
698 	.ttm_tt_destroy = &radeon_ttm_tt_destroy,
699 	.eviction_valuable = ttm_bo_eviction_valuable,
700 	.evict_flags = &radeon_evict_flags,
701 	.move = &radeon_bo_move,
702 	.io_mem_reserve = &radeon_ttm_io_mem_reserve,
703 };
704 
radeon_ttm_init(struct radeon_device * rdev)705 int radeon_ttm_init(struct radeon_device *rdev)
706 {
707 	int r;
708 	unsigned long stolen_size = 0;
709 
710 #if NEFIFB > 0
711 	stolen_size = efifb_stolen();
712 #endif
713 	if (stolen_size == 0)
714 		stolen_size = 256 * 1024;
715 
716 	/* No others user of address space so set it to 0 */
717 #ifdef notyet
718 	r = ttm_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev,
719 			       rdev->ddev->anon_inode->i_mapping,
720 			       rdev->ddev->vma_offset_manager,
721 			       rdev->need_swiotlb,
722 			       dma_addressing_limited(&rdev->pdev->dev));
723 #else
724 	r = ttm_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev,
725 			       /*rdev->ddev->anon_inode->i_mapping*/NULL,
726 			       rdev->ddev->vma_offset_manager,
727 			       rdev->need_swiotlb,
728 			       dma_addressing_limited(&rdev->pdev->dev));
729 #endif
730 	if (r) {
731 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
732 		return r;
733 	}
734 	rdev->mman.bdev.iot = rdev->iot;
735 	rdev->mman.bdev.memt = rdev->memt;
736 	rdev->mman.bdev.dmat = rdev->dmat;
737 	rdev->mman.initialized = true;
738 
739 	r = radeon_ttm_init_vram(rdev);
740 	if (r) {
741 		DRM_ERROR("Failed initializing VRAM heap.\n");
742 		return r;
743 	}
744 	/* Change the size here instead of the init above so only lpfn is affected */
745 	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
746 
747 #ifdef __sparc64__
748 	r = radeon_bo_create(rdev, rdev->fb_offset, PAGE_SIZE, true,
749 			     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
750 			     NULL, &rdev->stolen_vga_memory);
751 #else
752 	r = radeon_bo_create(rdev, stolen_size, PAGE_SIZE, true,
753 			     RADEON_GEM_DOMAIN_VRAM, 0, NULL,
754 			     NULL, &rdev->stolen_vga_memory);
755 #endif
756 	if (r) {
757 		return r;
758 	}
759 	r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
760 	if (r)
761 		return r;
762 	r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
763 	radeon_bo_unreserve(rdev->stolen_vga_memory);
764 	if (r) {
765 		radeon_bo_unref(&rdev->stolen_vga_memory);
766 		return r;
767 	}
768 	DRM_INFO("radeon: %uM of VRAM memory ready\n",
769 		 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
770 
771 	r = radeon_ttm_init_gtt(rdev);
772 	if (r) {
773 		DRM_ERROR("Failed initializing GTT heap.\n");
774 		return r;
775 	}
776 	DRM_INFO("radeon: %uM of GTT memory ready.\n",
777 		 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
778 
779 	radeon_ttm_debugfs_init(rdev);
780 
781 	return 0;
782 }
783 
radeon_ttm_fini(struct radeon_device * rdev)784 void radeon_ttm_fini(struct radeon_device *rdev)
785 {
786 	int r;
787 
788 	if (!rdev->mman.initialized)
789 		return;
790 
791 	if (rdev->stolen_vga_memory) {
792 		r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
793 		if (r == 0) {
794 			radeon_bo_unpin(rdev->stolen_vga_memory);
795 			radeon_bo_unreserve(rdev->stolen_vga_memory);
796 		}
797 		radeon_bo_unref(&rdev->stolen_vga_memory);
798 	}
799 	ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM);
800 	ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT);
801 	ttm_device_fini(&rdev->mman.bdev);
802 	radeon_gart_fini(rdev);
803 	rdev->mman.initialized = false;
804 	DRM_INFO("radeon: ttm finalized\n");
805 }
806 
807 /* this should only be called at bootup or when userspace
808  * isn't running */
radeon_ttm_set_active_vram_size(struct radeon_device * rdev,u64 size)809 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
810 {
811 	struct ttm_resource_manager *man;
812 
813 	if (!rdev->mman.initialized)
814 		return;
815 
816 	man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
817 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
818 	man->size = size >> PAGE_SHIFT;
819 }
820 
821 #if defined(CONFIG_DEBUG_FS)
822 
radeon_ttm_page_pool_show(struct seq_file * m,void * data)823 static int radeon_ttm_page_pool_show(struct seq_file *m, void *data)
824 {
825 	struct radeon_device *rdev = m->private;
826 
827 	return ttm_pool_debugfs(&rdev->mman.bdev.pool, m);
828 }
829 
830 DEFINE_SHOW_ATTRIBUTE(radeon_ttm_page_pool);
831 
radeon_ttm_vram_open(struct inode * inode,struct file * filep)832 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
833 {
834 	struct radeon_device *rdev = inode->i_private;
835 	i_size_write(inode, rdev->mc.mc_vram_size);
836 	filep->private_data = inode->i_private;
837 	return 0;
838 }
839 
radeon_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)840 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
841 				    size_t size, loff_t *pos)
842 {
843 	struct radeon_device *rdev = f->private_data;
844 	ssize_t result = 0;
845 	int r;
846 
847 	if (size & 0x3 || *pos & 0x3)
848 		return -EINVAL;
849 
850 	while (size) {
851 		unsigned long flags;
852 		uint32_t value;
853 
854 		if (*pos >= rdev->mc.mc_vram_size)
855 			return result;
856 
857 		spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
858 		WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
859 		if (rdev->family >= CHIP_CEDAR)
860 			WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
861 		value = RREG32(RADEON_MM_DATA);
862 		spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
863 
864 		r = put_user(value, (uint32_t __user *)buf);
865 		if (r)
866 			return r;
867 
868 		result += 4;
869 		buf += 4;
870 		*pos += 4;
871 		size -= 4;
872 	}
873 
874 	return result;
875 }
876 
877 static const struct file_operations radeon_ttm_vram_fops = {
878 	.owner = THIS_MODULE,
879 	.open = radeon_ttm_vram_open,
880 	.read = radeon_ttm_vram_read,
881 	.llseek = default_llseek
882 };
883 
radeon_ttm_gtt_open(struct inode * inode,struct file * filep)884 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
885 {
886 	struct radeon_device *rdev = inode->i_private;
887 	i_size_write(inode, rdev->mc.gtt_size);
888 	filep->private_data = inode->i_private;
889 	return 0;
890 }
891 
radeon_ttm_gtt_read(struct file * f,char __user * buf,size_t size,loff_t * pos)892 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
893 				   size_t size, loff_t *pos)
894 {
895 	struct radeon_device *rdev = f->private_data;
896 	ssize_t result = 0;
897 	int r;
898 
899 	while (size) {
900 		loff_t p = *pos / PAGE_SIZE;
901 		unsigned off = *pos & ~LINUX_PAGE_MASK;
902 		size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
903 		struct vm_page *page;
904 		void *ptr;
905 
906 		if (p >= rdev->gart.num_cpu_pages)
907 			return result;
908 
909 		page = rdev->gart.pages[p];
910 		if (page) {
911 			ptr = kmap_local_page(page);
912 			ptr += off;
913 
914 			r = copy_to_user(buf, ptr, cur_size);
915 			kunmap_local(ptr);
916 		} else
917 			r = clear_user(buf, cur_size);
918 
919 		if (r)
920 			return -EFAULT;
921 
922 		result += cur_size;
923 		buf += cur_size;
924 		*pos += cur_size;
925 		size -= cur_size;
926 	}
927 
928 	return result;
929 }
930 
931 static const struct file_operations radeon_ttm_gtt_fops = {
932 	.owner = THIS_MODULE,
933 	.open = radeon_ttm_gtt_open,
934 	.read = radeon_ttm_gtt_read,
935 	.llseek = default_llseek
936 };
937 
938 #endif
939 
radeon_ttm_debugfs_init(struct radeon_device * rdev)940 static void radeon_ttm_debugfs_init(struct radeon_device *rdev)
941 {
942 #if defined(CONFIG_DEBUG_FS)
943 	struct drm_minor *minor = rdev->ddev->primary;
944 	struct dentry *root = minor->debugfs_root;
945 
946 	debugfs_create_file("radeon_vram", 0444, root, rdev,
947 			    &radeon_ttm_vram_fops);
948 	debugfs_create_file("radeon_gtt", 0444, root, rdev,
949 			    &radeon_ttm_gtt_fops);
950 	debugfs_create_file("ttm_page_pool", 0444, root, rdev,
951 			    &radeon_ttm_page_pool_fops);
952 	ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
953 							     TTM_PL_VRAM),
954 					    root, "radeon_vram_mm");
955 	ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
956 							     TTM_PL_TT),
957 					    root, "radeon_gtt_mm");
958 #endif
959 }
960