1 /*	$NetBSD: amdgpu_psp.h,v 1.3 2021/12/19 12:21:29 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2016 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Author: Huang Rui
25  *
26  */
27 #ifndef __AMDGPU_PSP_H__
28 #define __AMDGPU_PSP_H__
29 
30 #include "amdgpu.h"
31 #include "psp_gfx_if.h"
32 #include "ta_xgmi_if.h"
33 #include "ta_ras_if.h"
34 
35 #define PSP_FENCE_BUFFER_SIZE	0x1000
36 #define PSP_CMD_BUFFER_SIZE	0x1000
37 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
38 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
39 #define PSP_1_MEG		0x100000
40 #define PSP_TMR_SIZE	0x400000
41 #define PSP_HDCP_SHARED_MEM_SIZE	0x4000
42 #define PSP_DTM_SHARED_MEM_SIZE	0x4000
43 #define PSP_SHARED_MEM_SIZE		0x4000
44 
45 struct psp_context;
46 struct psp_xgmi_node_info;
47 struct psp_xgmi_topology_info;
48 
49 enum psp_bootloader_cmd {
50 	PSP_BL__LOAD_SYSDRV		= 0x10000,
51 	PSP_BL__LOAD_SOSDRV		= 0x20000,
52 	PSP_BL__LOAD_KEY_DATABASE	= 0x80000,
53 	PSP_BL__DRAM_LONG_TRAIN		= 0x100000,
54 	PSP_BL__DRAM_SHORT_TRAIN	= 0x200000,
55 };
56 
57 enum psp_ring_type
58 {
59 	PSP_RING_TYPE__INVALID = 0,
60 	/*
61 	 * These values map to the way the PSP kernel identifies the
62 	 * rings.
63 	 */
64 	PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
65 	PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
66 };
67 
68 struct psp_ring
69 {
70 	enum psp_ring_type		ring_type;
71 	struct psp_gfx_rb_frame		*ring_mem;
72 	uint64_t			ring_mem_mc_addr;
73 	void				*ring_mem_handle;
74 	uint32_t			ring_size;
75 };
76 
77 /* More registers may will be supported */
78 enum psp_reg_prog_id {
79 	PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
80 	PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
81 	PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
82 	PSP_REG_LAST
83 };
84 
85 struct psp_funcs
86 {
87 	int (*init_microcode)(struct psp_context *psp);
88 	int (*bootloader_load_kdb)(struct psp_context *psp);
89 	int (*bootloader_load_sysdrv)(struct psp_context *psp);
90 	int (*bootloader_load_sos)(struct psp_context *psp);
91 	int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
92 	int (*ring_create)(struct psp_context *psp,
93 			   enum psp_ring_type ring_type);
94 	int (*ring_stop)(struct psp_context *psp,
95 			    enum psp_ring_type ring_type);
96 	int (*ring_destroy)(struct psp_context *psp,
97 			    enum psp_ring_type ring_type);
98 	bool (*compare_sram_data)(struct psp_context *psp,
99 				  struct amdgpu_firmware_info *ucode,
100 				  enum AMDGPU_UCODE_ID ucode_type);
101 	bool (*smu_reload_quirk)(struct psp_context *psp);
102 	int (*mode1_reset)(struct psp_context *psp);
103 	int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
104 	int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
105 	int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
106 				      struct psp_xgmi_topology_info *topology);
107 	int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
108 				      struct psp_xgmi_topology_info *topology);
109 	bool (*support_vmr_ring)(struct psp_context *psp);
110 	int (*ras_trigger_error)(struct psp_context *psp,
111 			struct ta_ras_trigger_error_input *info);
112 	int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
113 	int (*rlc_autoload_start)(struct psp_context *psp);
114 	int (*mem_training_init)(struct psp_context *psp);
115 	void (*mem_training_fini)(struct psp_context *psp);
116 	int (*mem_training)(struct psp_context *psp, uint32_t ops);
117 	uint32_t (*ring_get_wptr)(struct psp_context *psp);
118 	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
119 };
120 
121 #define AMDGPU_XGMI_MAX_CONNECTED_NODES		64
122 struct psp_xgmi_node_info {
123 	uint64_t				node_id;
124 	uint8_t					num_hops;
125 	uint8_t					is_sharing_enabled;
126 	enum ta_xgmi_assigned_sdma_engine	sdma_engine;
127 };
128 
129 struct psp_xgmi_topology_info {
130 	uint32_t			num_nodes;
131 	struct psp_xgmi_node_info	nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
132 };
133 
134 struct psp_asd_context {
135 	bool			asd_initialized;
136 	uint32_t		session_id;
137 };
138 
139 struct psp_xgmi_context {
140 	uint8_t				initialized;
141 	uint32_t			session_id;
142 	struct amdgpu_bo                *xgmi_shared_bo;
143 	uint64_t                        xgmi_shared_mc_addr;
144 	void                            *xgmi_shared_buf;
145 	struct psp_xgmi_topology_info	top_info;
146 };
147 
148 struct psp_ras_context {
149 	/*ras fw*/
150 	bool			ras_initialized;
151 	uint32_t		session_id;
152 	struct amdgpu_bo	*ras_shared_bo;
153 	uint64_t		ras_shared_mc_addr;
154 	void			*ras_shared_buf;
155 	struct amdgpu_ras	*ras;
156 };
157 
158 struct psp_hdcp_context {
159 	bool			hdcp_initialized;
160 	uint32_t		session_id;
161 	struct amdgpu_bo	*hdcp_shared_bo;
162 	uint64_t		hdcp_shared_mc_addr;
163 	void			*hdcp_shared_buf;
164 };
165 
166 struct psp_dtm_context {
167 	bool			dtm_initialized;
168 	uint32_t		session_id;
169 	struct amdgpu_bo	*dtm_shared_bo;
170 	uint64_t		dtm_shared_mc_addr;
171 	void			*dtm_shared_buf;
172 };
173 
174 #define MEM_TRAIN_SYSTEM_SIGNATURE		0x54534942
175 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES	0x1000
176 #define GDDR6_MEM_TRAINING_OFFSET		0x8000
177 /*Define the VRAM size that will be encroached by BIST training.*/
178 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE	0x2000000
179 
180 enum psp_memory_training_init_flag {
181 	PSP_MEM_TRAIN_NOT_SUPPORT	= 0x0,
182 	PSP_MEM_TRAIN_SUPPORT		= 0x1,
183 	PSP_MEM_TRAIN_INIT_FAILED	= 0x2,
184 	PSP_MEM_TRAIN_RESERVE_SUCCESS	= 0x4,
185 	PSP_MEM_TRAIN_INIT_SUCCESS	= 0x8,
186 };
187 
188 enum psp_memory_training_ops {
189 	PSP_MEM_TRAIN_SEND_LONG_MSG	= 0x1,
190 	PSP_MEM_TRAIN_SAVE		= 0x2,
191 	PSP_MEM_TRAIN_RESTORE		= 0x4,
192 	PSP_MEM_TRAIN_SEND_SHORT_MSG	= 0x8,
193 	PSP_MEM_TRAIN_COLD_BOOT		= PSP_MEM_TRAIN_SEND_LONG_MSG,
194 	PSP_MEM_TRAIN_RESUME		= PSP_MEM_TRAIN_SEND_SHORT_MSG,
195 };
196 
197 struct psp_memory_training_context {
198 	/*training data size*/
199 	u64 train_data_size;
200 	/*
201 	 * sys_cache
202 	 * cpu virtual address
203 	 * system memory buffer that used to store the training data.
204 	 */
205 	void *sys_cache;
206 
207 	/*vram offset of the p2c training data*/
208 	u64 p2c_train_data_offset;
209 
210 	/*vram offset of the c2p training data*/
211 	u64 c2p_train_data_offset;
212 	struct amdgpu_bo *c2p_bo;
213 
214 	enum psp_memory_training_init_flag init;
215 	u32 training_cnt;
216 };
217 
218 struct psp_context
219 {
220 	struct amdgpu_device            *adev;
221 	struct psp_ring                 km_ring;
222 	struct psp_gfx_cmd_resp		*cmd;
223 
224 	const struct psp_funcs		*funcs;
225 
226 	/* firmware buffer */
227 	struct amdgpu_bo		*fw_pri_bo;
228 	uint64_t			fw_pri_mc_addr;
229 	void				*fw_pri_buf;
230 
231 	/* sos firmware */
232 	const struct firmware		*sos_fw;
233 	uint32_t			sos_fw_version;
234 	uint32_t			sos_feature_version;
235 	uint32_t			sys_bin_size;
236 	uint32_t			sos_bin_size;
237 	uint32_t			toc_bin_size;
238 	uint32_t			kdb_bin_size;
239 	const uint8_t			*sys_start_addr;
240 	const uint8_t			*sos_start_addr;
241 	const uint8_t			*toc_start_addr;
242 	const uint8_t			*kdb_start_addr;
243 
244 	/* tmr buffer */
245 	struct amdgpu_bo		*tmr_bo;
246 	uint64_t			tmr_mc_addr;
247 
248 	/* asd firmware */
249 	const struct firmware		*asd_fw;
250 	uint32_t			asd_fw_version;
251 	uint32_t			asd_feature_version;
252 	uint32_t			asd_ucode_size;
253 	const uint8_t			*asd_start_addr;
254 
255 	/* fence buffer */
256 	struct amdgpu_bo		*fence_buf_bo;
257 	uint64_t			fence_buf_mc_addr;
258 	void				*fence_buf;
259 
260 	/* cmd buffer */
261 	struct amdgpu_bo		*cmd_buf_bo;
262 	uint64_t			cmd_buf_mc_addr;
263 	struct psp_gfx_cmd_resp		*cmd_buf_mem;
264 
265 	/* fence value associated with cmd buffer */
266 	atomic_t			fence_value;
267 	/* flag to mark whether gfx fw autoload is supported or not */
268 	bool				autoload_supported;
269 
270 	/* xgmi ta firmware and buffer */
271 	const struct firmware		*ta_fw;
272 	uint32_t			ta_fw_version;
273 	uint32_t			ta_xgmi_ucode_version;
274 	uint32_t			ta_xgmi_ucode_size;
275 	const uint8_t			*ta_xgmi_start_addr;
276 	uint32_t			ta_ras_ucode_version;
277 	uint32_t			ta_ras_ucode_size;
278 	const uint8_t			*ta_ras_start_addr;
279 
280 	uint32_t			ta_hdcp_ucode_version;
281 	uint32_t			ta_hdcp_ucode_size;
282 	const uint8_t			*ta_hdcp_start_addr;
283 
284 	uint32_t			ta_dtm_ucode_version;
285 	uint32_t			ta_dtm_ucode_size;
286 	const uint8_t			*ta_dtm_start_addr;
287 
288 	struct psp_asd_context		asd_context;
289 	struct psp_xgmi_context		xgmi_context;
290 	struct psp_ras_context		ras;
291 	struct psp_hdcp_context 	hdcp_context;
292 	struct psp_dtm_context		dtm_context;
293 	struct mutex			mutex;
294 	struct psp_memory_training_context mem_train_ctx;
295 };
296 
297 struct amdgpu_psp_funcs {
298 	bool (*check_fw_loading_status)(struct amdgpu_device *adev,
299 					enum AMDGPU_UCODE_ID);
300 };
301 
302 
303 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
304 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
305 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
306 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
307 #define psp_compare_sram_data(psp, ucode, type) \
308 		(psp)->funcs->compare_sram_data((psp), (ucode), (type))
309 #define psp_init_microcode(psp) \
310 		((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
311 #define psp_bootloader_load_kdb(psp) \
312 		((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
313 #define psp_bootloader_load_sysdrv(psp) \
314 		((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
315 #define psp_bootloader_load_sos(psp) \
316 		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
317 #define psp_smu_reload_quirk(psp) \
318 		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
319 #define psp_support_vmr_ring(psp) \
320 		((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
321 #define psp_mode1_reset(psp) \
322 		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
323 #define psp_xgmi_get_node_id(psp, node_id) \
324 		((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
325 #define psp_xgmi_get_hive_id(psp, hive_id) \
326 		((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
327 #define psp_xgmi_get_topology_info(psp, num_device, topology) \
328 		((psp)->funcs->xgmi_get_topology_info ? \
329 		(psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
330 #define psp_xgmi_set_topology_info(psp, num_device, topology) \
331 		((psp)->funcs->xgmi_set_topology_info ?	 \
332 		(psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
333 #define psp_rlc_autoload(psp) \
334 		((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
335 #define psp_mem_training_init(psp) \
336 	((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0)
337 #define psp_mem_training_fini(psp) \
338 	((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0)
339 #define psp_mem_training(psp, ops) \
340 	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
341 
342 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
343 
344 #define psp_ras_trigger_error(psp, info) \
345 	((psp)->funcs->ras_trigger_error ? \
346 	(psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL)
347 #define psp_ras_cure_posion(psp, addr) \
348 	((psp)->funcs->ras_cure_posion ? \
349 	(psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
350 
351 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
352 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
353 
354 extern const struct amd_ip_funcs psp_ip_funcs;
355 
356 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
357 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
358 			uint32_t field_val, uint32_t mask, bool check_changed);
359 
360 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
361 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
362 
363 int psp_gpu_reset(struct amdgpu_device *adev);
364 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
365 			uint64_t cmd_gpu_addr, int cmd_size);
366 
367 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
368 
369 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
370 int psp_ras_enable_features(struct psp_context *psp,
371 		union ta_ras_cmd_input *info, bool enable);
372 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
373 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
374 
375 int psp_rlc_autoload_start(struct psp_context *psp);
376 
377 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
378 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
379 		uint32_t value);
380 int psp_ring_cmd_submit(struct psp_context *psp,
381 			uint64_t cmd_buf_mc_addr,
382 			uint64_t fence_mc_addr,
383 			int index);
384 #endif
385