Searched defs:reg_rd_req (Results 1 – 16 of 16) sorted by relevance
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | ctrlport_to_regport.v | 44 output reg reg_rd_req = 1'b0, port
|
| H A D | regport_to_xbar_settingsbus.v | 38 input reg_rd_req, port
|
| H A D | axi_crossbar_regport.v | 30 input reg_rd_req, port
|
| H A D | axil_regport_master.v | 82 output reg_rd_req, port
|
| H A D | mdio_master.v | 25 input reg_rd_req, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/ |
| H A D | demo_one_gig_pcs_pma_mdio.v | 224 reg reg_rd_req; register
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/ |
| H A D | eth_ipv4_interface.sv | 55 input logic reg_rd_req, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/ |
| H A D | eth_ifc_synth_test.sv | 43 input logic reg_rd_req, port
|
| H A D | eth_ifc_tb.sv | 105 reg reg_rd_req = 1'b0; register
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport/ |
| H A D | eth_interface.v | 26 input reg_rd_req, port
|
| H A D | eth_internal.v | 93 wire reg_rd_req; net
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
| H A D | n3xx_mgt_wrapper.v | 41 input wire reg_rd_req, port
|
| H A D | n3xx_mgt_channel_wrapper.v | 195 wire reg_rd_req; net
|
| H A D | n3xx_mgt_io_core.v | 59 input reg_rd_req, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
| H A D | n3xx_mgt_io_core.v | 56 input reg_rd_req, port
|
| H A D | n3xx_sfp_wrapper.v | 170 wire reg_rd_req; net
|