xref: /qemu/target/arm/vfp_helper.c (revision 8b0898f8)
1 /*
2  * ARM VFP floating-point operations
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
24 #include "cpu-features.h"
25 #ifdef CONFIG_TCG
26 #include "qemu/log.h"
27 #include "fpu/softfloat.h"
28 #endif
29 
30 /* VFP support.  We follow the convention used for VFP instructions:
31    Single precision routines have a "s" suffix, double precision a
32    "d" suffix.  */
33 
34 #ifdef CONFIG_TCG
35 
36 /* Convert host exception flags to vfp form.  */
vfp_exceptbits_from_host(int host_bits)37 static inline int vfp_exceptbits_from_host(int host_bits)
38 {
39     int target_bits = 0;
40 
41     if (host_bits & float_flag_invalid) {
42         target_bits |= 1;
43     }
44     if (host_bits & float_flag_divbyzero) {
45         target_bits |= 2;
46     }
47     if (host_bits & float_flag_overflow) {
48         target_bits |= 4;
49     }
50     if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
51         target_bits |= 8;
52     }
53     if (host_bits & float_flag_inexact) {
54         target_bits |= 0x10;
55     }
56     if (host_bits & float_flag_input_denormal) {
57         target_bits |= 0x80;
58     }
59     return target_bits;
60 }
61 
62 /* Convert vfp exception flags to target form.  */
vfp_exceptbits_to_host(int target_bits)63 static inline int vfp_exceptbits_to_host(int target_bits)
64 {
65     int host_bits = 0;
66 
67     if (target_bits & 1) {
68         host_bits |= float_flag_invalid;
69     }
70     if (target_bits & 2) {
71         host_bits |= float_flag_divbyzero;
72     }
73     if (target_bits & 4) {
74         host_bits |= float_flag_overflow;
75     }
76     if (target_bits & 8) {
77         host_bits |= float_flag_underflow;
78     }
79     if (target_bits & 0x10) {
80         host_bits |= float_flag_inexact;
81     }
82     if (target_bits & 0x80) {
83         host_bits |= float_flag_input_denormal;
84     }
85     return host_bits;
86 }
87 
vfp_get_fpsr_from_host(CPUARMState * env)88 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
89 {
90     uint32_t i;
91 
92     i = get_float_exception_flags(&env->vfp.fp_status);
93     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
94     /* FZ16 does not generate an input denormal exception.  */
95     i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
96           & ~float_flag_input_denormal);
97     i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
98           & ~float_flag_input_denormal);
99     return vfp_exceptbits_from_host(i);
100 }
101 
vfp_set_fpsr_to_host(CPUARMState * env,uint32_t val)102 static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
103 {
104     /*
105      * The exception flags are ORed together when we read fpscr so we
106      * only need to preserve the current state in one of our
107      * float_status values.
108      */
109     int i = vfp_exceptbits_to_host(val);
110     set_float_exception_flags(i, &env->vfp.fp_status);
111     set_float_exception_flags(0, &env->vfp.fp_status_f16);
112     set_float_exception_flags(0, &env->vfp.standard_fp_status);
113     set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
114 }
115 
vfp_set_fpcr_to_host(CPUARMState * env,uint32_t val,uint32_t mask)116 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
117 {
118     uint64_t changed = env->vfp.fpcr;
119 
120     changed ^= val;
121     changed &= mask;
122     if (changed & (3 << 22)) {
123         int i = (val >> 22) & 3;
124         switch (i) {
125         case FPROUNDING_TIEEVEN:
126             i = float_round_nearest_even;
127             break;
128         case FPROUNDING_POSINF:
129             i = float_round_up;
130             break;
131         case FPROUNDING_NEGINF:
132             i = float_round_down;
133             break;
134         case FPROUNDING_ZERO:
135             i = float_round_to_zero;
136             break;
137         }
138         set_float_rounding_mode(i, &env->vfp.fp_status);
139         set_float_rounding_mode(i, &env->vfp.fp_status_f16);
140     }
141     if (changed & FPCR_FZ16) {
142         bool ftz_enabled = val & FPCR_FZ16;
143         set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
144         set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
145         set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
146         set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
147     }
148     if (changed & FPCR_FZ) {
149         bool ftz_enabled = val & FPCR_FZ;
150         set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
151         set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
152     }
153     if (changed & FPCR_DN) {
154         bool dnan_enabled = val & FPCR_DN;
155         set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
156         set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
157     }
158 }
159 
160 #else
161 
vfp_get_fpsr_from_host(CPUARMState * env)162 static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
163 {
164     return 0;
165 }
166 
vfp_set_fpsr_to_host(CPUARMState * env,uint32_t val)167 static void vfp_set_fpsr_to_host(CPUARMState *env, uint32_t val)
168 {
169 }
170 
vfp_set_fpcr_to_host(CPUARMState * env,uint32_t val,uint32_t mask)171 static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
172 {
173 }
174 
175 #endif
176 
vfp_get_fpcr(CPUARMState * env)177 uint32_t vfp_get_fpcr(CPUARMState *env)
178 {
179     uint32_t fpcr = env->vfp.fpcr
180         | (env->vfp.vec_len << 16)
181         | (env->vfp.vec_stride << 20);
182 
183     /*
184      * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever
185      * of the two is not applicable to this CPU will always be zero.
186      */
187     fpcr |= env->v7m.ltpsize << 16;
188 
189     return fpcr;
190 }
191 
vfp_get_fpsr(CPUARMState * env)192 uint32_t vfp_get_fpsr(CPUARMState *env)
193 {
194     uint32_t fpsr = env->vfp.fpsr;
195     uint32_t i;
196 
197     fpsr |= vfp_get_fpsr_from_host(env);
198 
199     i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
200     fpsr |= i ? FPSR_QC : 0;
201     return fpsr;
202 }
203 
HELPER(vfp_get_fpscr)204 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
205 {
206     return (vfp_get_fpcr(env) & FPSCR_FPCR_MASK) |
207         (vfp_get_fpsr(env) & FPSCR_FPSR_MASK);
208 }
209 
vfp_get_fpscr(CPUARMState * env)210 uint32_t vfp_get_fpscr(CPUARMState *env)
211 {
212     return HELPER(vfp_get_fpscr)(env);
213 }
214 
vfp_set_fpsr(CPUARMState * env,uint32_t val)215 void vfp_set_fpsr(CPUARMState *env, uint32_t val)
216 {
217     ARMCPU *cpu = env_archcpu(env);
218 
219     vfp_set_fpsr_to_host(env, val);
220 
221     if (arm_feature(env, ARM_FEATURE_NEON) ||
222         cpu_isar_feature(aa32_mve, cpu)) {
223         /*
224          * The bit we set within vfp.qc[] is arbitrary; the array as a
225          * whole being zero/non-zero is what counts.
226          */
227         env->vfp.qc[0] = val & FPSR_QC;
228         env->vfp.qc[1] = 0;
229         env->vfp.qc[2] = 0;
230         env->vfp.qc[3] = 0;
231     }
232 
233     /*
234      * The only FPSR bits we keep in vfp.fpsr are NZCV:
235      * the exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
236      * fp_status, and QC is in vfp.qc[]. Store the NZCV bits there,
237      * and zero any of the other FPSR bits.
238      */
239     val &= FPSR_NZCV_MASK;
240     env->vfp.fpsr = val;
241 }
242 
vfp_set_fpcr_masked(CPUARMState * env,uint32_t val,uint32_t mask)243 static void vfp_set_fpcr_masked(CPUARMState *env, uint32_t val, uint32_t mask)
244 {
245     /*
246      * We only set FPCR bits defined by mask, and leave the others alone.
247      * We assume the mask is sensible (e.g. doesn't try to set only
248      * part of a field)
249      */
250     ARMCPU *cpu = env_archcpu(env);
251 
252     /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */
253     if (!cpu_isar_feature(any_fp16, cpu)) {
254         val &= ~FPCR_FZ16;
255     }
256 
257     if (!cpu_isar_feature(aa64_ebf16, cpu)) {
258         val &= ~FPCR_EBF;
259     }
260 
261     vfp_set_fpcr_to_host(env, val, mask);
262 
263     if (mask & (FPCR_LEN_MASK | FPCR_STRIDE_MASK)) {
264         if (!arm_feature(env, ARM_FEATURE_M)) {
265             /*
266              * Short-vector length and stride; on M-profile these bits
267              * are used for different purposes.
268              * We can't make this conditional be "if MVFR0.FPShVec != 0",
269              * because in v7A no-short-vector-support cores still had to
270              * allow Stride/Len to be written with the only effect that
271              * some insns are required to UNDEF if the guest sets them.
272              */
273             env->vfp.vec_len = extract32(val, 16, 3);
274             env->vfp.vec_stride = extract32(val, 20, 2);
275         } else if (cpu_isar_feature(aa32_mve, cpu)) {
276             env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT,
277                                          FPCR_LTPSIZE_LENGTH);
278         }
279     }
280 
281     /*
282      * We don't implement trapped exception handling, so the
283      * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
284      *
285      * The FPCR bits we keep in vfp.fpcr are AHP, DN, FZ, RMode, EBF
286      * and FZ16. Len, Stride and LTPSIZE we just handled. Store those bits
287      * there, and zero any of the other FPCR bits and the RES0 and RAZ/WI
288      * bits.
289      */
290     val &= FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK | FPCR_FZ16 | FPCR_EBF;
291     env->vfp.fpcr &= ~mask;
292     env->vfp.fpcr |= val;
293 }
294 
vfp_set_fpcr(CPUARMState * env,uint32_t val)295 void vfp_set_fpcr(CPUARMState *env, uint32_t val)
296 {
297     vfp_set_fpcr_masked(env, val, MAKE_64BIT_MASK(0, 32));
298 }
299 
HELPER(vfp_set_fpscr)300 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
301 {
302     vfp_set_fpcr_masked(env, val, FPSCR_FPCR_MASK);
303     vfp_set_fpsr(env, val & FPSCR_FPSR_MASK);
304 }
305 
vfp_set_fpscr(CPUARMState * env,uint32_t val)306 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
307 {
308     HELPER(vfp_set_fpscr)(env, val);
309 }
310 
311 #ifdef CONFIG_TCG
312 
313 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
314 
315 #define VFP_BINOP(name) \
316 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
317 { \
318     float_status *fpst = fpstp; \
319     return float16_ ## name(a, b, fpst); \
320 } \
321 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
322 { \
323     float_status *fpst = fpstp; \
324     return float32_ ## name(a, b, fpst); \
325 } \
326 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
327 { \
328     float_status *fpst = fpstp; \
329     return float64_ ## name(a, b, fpst); \
330 }
331 VFP_BINOP(add)
VFP_BINOP(sub)332 VFP_BINOP(sub)
333 VFP_BINOP(mul)
334 VFP_BINOP(div)
335 VFP_BINOP(min)
336 VFP_BINOP(max)
337 VFP_BINOP(minnum)
338 VFP_BINOP(maxnum)
339 #undef VFP_BINOP
340 
341 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
342 {
343     return float16_sqrt(a, &env->vfp.fp_status_f16);
344 }
345 
VFP_HELPER(sqrt,s)346 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
347 {
348     return float32_sqrt(a, &env->vfp.fp_status);
349 }
350 
VFP_HELPER(sqrt,d)351 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
352 {
353     return float64_sqrt(a, &env->vfp.fp_status);
354 }
355 
softfloat_to_vfp_compare(CPUARMState * env,FloatRelation cmp)356 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
357 {
358     uint32_t flags;
359     switch (cmp) {
360     case float_relation_equal:
361         flags = 0x6;
362         break;
363     case float_relation_less:
364         flags = 0x8;
365         break;
366     case float_relation_greater:
367         flags = 0x2;
368         break;
369     case float_relation_unordered:
370         flags = 0x3;
371         break;
372     default:
373         g_assert_not_reached();
374     }
375     env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */
376 }
377 
378 /* XXX: check quiet/signaling case */
379 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
380 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env)  \
381 { \
382     softfloat_to_vfp_compare(env, \
383         FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
384 } \
385 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
386 { \
387     softfloat_to_vfp_compare(env, \
388         FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
389 }
DO_VFP_cmp(h,float16,dh_ctype_f16,fp_status_f16)390 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
391 DO_VFP_cmp(s, float32, float32, fp_status)
392 DO_VFP_cmp(d, float64, float64, fp_status)
393 #undef DO_VFP_cmp
394 
395 /* Integer to float and float to integer conversions */
396 
397 #define CONV_ITOF(name, ftype, fsz, sign)                           \
398 ftype HELPER(name)(uint32_t x, void *fpstp)                         \
399 {                                                                   \
400     float_status *fpst = fpstp;                                     \
401     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
402 }
403 
404 #define CONV_FTOI(name, ftype, fsz, sign, round)                \
405 sign##int32_t HELPER(name)(ftype x, void *fpstp)                \
406 {                                                               \
407     float_status *fpst = fpstp;                                 \
408     if (float##fsz##_is_any_nan(x)) {                           \
409         float_raise(float_flag_invalid, fpst);                  \
410         return 0;                                               \
411     }                                                           \
412     return float##fsz##_to_##sign##int32##round(x, fpst);       \
413 }
414 
415 #define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
416     CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
417     CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
418     CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
419 
420 FLOAT_CONVS(si, h, uint32_t, 16, )
421 FLOAT_CONVS(si, s, float32, 32, )
422 FLOAT_CONVS(si, d, float64, 64, )
423 FLOAT_CONVS(ui, h, uint32_t, 16, u)
424 FLOAT_CONVS(ui, s, float32, 32, u)
425 FLOAT_CONVS(ui, d, float64, 64, u)
426 
427 #undef CONV_ITOF
428 #undef CONV_FTOI
429 #undef FLOAT_CONVS
430 
431 /* floating point conversion */
432 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
433 {
434     return float32_to_float64(x, &env->vfp.fp_status);
435 }
436 
VFP_HELPER(fcvts,d)437 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
438 {
439     return float64_to_float32(x, &env->vfp.fp_status);
440 }
441 
HELPER(bfcvt)442 uint32_t HELPER(bfcvt)(float32 x, void *status)
443 {
444     return float32_to_bfloat16(x, status);
445 }
446 
HELPER(bfcvt_pair)447 uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
448 {
449     bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
450     bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
451     return deposit32(lo, 16, 16, hi);
452 }
453 
454 /*
455  * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
456  * must always round-to-nearest; the AArch64 ones honour the FPSCR
457  * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
458  * round-to-nearest so either helper will work.) AArch32 float-to-fix
459  * must round-to-zero.
460  */
461 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype)            \
462 ftype HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift,      \
463                                      void *fpstp) \
464 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
465 
466 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype)      \
467     ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t  x, \
468                                                      uint32_t shift,   \
469                                                      void *fpstp)      \
470     {                                                                  \
471         ftype ret;                                                     \
472         float_status *fpst = fpstp;                                    \
473         FloatRoundMode oldmode = fpst->float_rounding_mode;            \
474         fpst->float_rounding_mode = float_round_nearest_even;          \
475         ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp);      \
476         fpst->float_rounding_mode = oldmode;                           \
477         return ret;                                                    \
478     }
479 
480 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
481 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift,      \
482                                             void *fpst)                   \
483 {                                                                         \
484     if (unlikely(float##fsz##_is_any_nan(x))) {                           \
485         float_raise(float_flag_invalid, fpst);                            \
486         return 0;                                                         \
487     }                                                                     \
488     return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst);       \
489 }
490 
491 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype)            \
492 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype)              \
493 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype)        \
494 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype,        \
495                          float_round_to_zero, _round_to_zero)    \
496 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype,        \
497                          get_float_rounding_mode(fpst), )
498 
499 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype)        \
500 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype)              \
501 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype,        \
502                          get_float_rounding_mode(fpst), )
503 
504 VFP_CONV_FIX(sh, d, 64, float64, 64, int16)
505 VFP_CONV_FIX(sl, d, 64, float64, 64, int32)
506 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
507 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16)
508 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32)
509 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64)
510 VFP_CONV_FIX(sh, s, 32, float32, 32, int16)
511 VFP_CONV_FIX(sl, s, 32, float32, 32, int32)
512 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
513 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
514 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
515 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
516 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16)
517 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32)
518 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
519 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
520 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
521 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
522 
523 #undef VFP_CONV_FIX
524 #undef VFP_CONV_FIX_FLOAT
525 #undef VFP_CONV_FLOAT_FIX_ROUND
526 #undef VFP_CONV_FIX_A64
527 
528 /* Set the current fp rounding mode and return the old one.
529  * The argument is a softfloat float_round_ value.
530  */
HELPER(set_rmode)531 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
532 {
533     float_status *fp_status = fpstp;
534 
535     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
536     set_float_rounding_mode(rmode, fp_status);
537 
538     return prev_rmode;
539 }
540 
541 /* Half precision conversions.  */
HELPER(vfp_fcvt_f16_to_f32)542 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
543 {
544     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
545      * it would affect flushing input denormals.
546      */
547     float_status *fpst = fpstp;
548     bool save = get_flush_inputs_to_zero(fpst);
549     set_flush_inputs_to_zero(false, fpst);
550     float32 r = float16_to_float32(a, !ahp_mode, fpst);
551     set_flush_inputs_to_zero(save, fpst);
552     return r;
553 }
554 
HELPER(vfp_fcvt_f32_to_f16)555 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
556 {
557     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
558      * it would affect flushing output denormals.
559      */
560     float_status *fpst = fpstp;
561     bool save = get_flush_to_zero(fpst);
562     set_flush_to_zero(false, fpst);
563     float16 r = float32_to_float16(a, !ahp_mode, fpst);
564     set_flush_to_zero(save, fpst);
565     return r;
566 }
567 
HELPER(vfp_fcvt_f16_to_f64)568 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
569 {
570     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
571      * it would affect flushing input denormals.
572      */
573     float_status *fpst = fpstp;
574     bool save = get_flush_inputs_to_zero(fpst);
575     set_flush_inputs_to_zero(false, fpst);
576     float64 r = float16_to_float64(a, !ahp_mode, fpst);
577     set_flush_inputs_to_zero(save, fpst);
578     return r;
579 }
580 
HELPER(vfp_fcvt_f64_to_f16)581 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
582 {
583     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
584      * it would affect flushing output denormals.
585      */
586     float_status *fpst = fpstp;
587     bool save = get_flush_to_zero(fpst);
588     set_flush_to_zero(false, fpst);
589     float16 r = float64_to_float16(a, !ahp_mode, fpst);
590     set_flush_to_zero(save, fpst);
591     return r;
592 }
593 
594 /* NEON helpers.  */
595 
596 /* Constants 256 and 512 are used in some helpers; we avoid relying on
597  * int->float conversions at run-time.  */
598 #define float64_256 make_float64(0x4070000000000000LL)
599 #define float64_512 make_float64(0x4080000000000000LL)
600 #define float16_maxnorm make_float16(0x7bff)
601 #define float32_maxnorm make_float32(0x7f7fffff)
602 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
603 
604 /* Reciprocal functions
605  *
606  * The algorithm that must be used to calculate the estimate
607  * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
608  */
609 
610 /* See RecipEstimate()
611  *
612  * input is a 9 bit fixed point number
613  * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
614  * result range 256 .. 511 for a number from 1.0 to 511/256.
615  */
616 
recip_estimate(int input)617 static int recip_estimate(int input)
618 {
619     int a, b, r;
620     assert(256 <= input && input < 512);
621     a = (input * 2) + 1;
622     b = (1 << 19) / a;
623     r = (b + 1) >> 1;
624     assert(256 <= r && r < 512);
625     return r;
626 }
627 
628 /*
629  * Common wrapper to call recip_estimate
630  *
631  * The parameters are exponent and 64 bit fraction (without implicit
632  * bit) where the binary point is nominally at bit 52. Returns a
633  * float64 which can then be rounded to the appropriate size by the
634  * callee.
635  */
636 
call_recip_estimate(int * exp,int exp_off,uint64_t frac)637 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
638 {
639     uint32_t scaled, estimate;
640     uint64_t result_frac;
641     int result_exp;
642 
643     /* Handle sub-normals */
644     if (*exp == 0) {
645         if (extract64(frac, 51, 1) == 0) {
646             *exp = -1;
647             frac <<= 2;
648         } else {
649             frac <<= 1;
650         }
651     }
652 
653     /* scaled = UInt('1':fraction<51:44>) */
654     scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
655     estimate = recip_estimate(scaled);
656 
657     result_exp = exp_off - *exp;
658     result_frac = deposit64(0, 44, 8, estimate);
659     if (result_exp == 0) {
660         result_frac = deposit64(result_frac >> 1, 51, 1, 1);
661     } else if (result_exp == -1) {
662         result_frac = deposit64(result_frac >> 2, 50, 2, 1);
663         result_exp = 0;
664     }
665 
666     *exp = result_exp;
667 
668     return result_frac;
669 }
670 
round_to_inf(float_status * fpst,bool sign_bit)671 static bool round_to_inf(float_status *fpst, bool sign_bit)
672 {
673     switch (fpst->float_rounding_mode) {
674     case float_round_nearest_even: /* Round to Nearest */
675         return true;
676     case float_round_up: /* Round to +Inf */
677         return !sign_bit;
678     case float_round_down: /* Round to -Inf */
679         return sign_bit;
680     case float_round_to_zero: /* Round to Zero */
681         return false;
682     default:
683         g_assert_not_reached();
684     }
685 }
686 
HELPER(recpe_f16)687 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
688 {
689     float_status *fpst = fpstp;
690     float16 f16 = float16_squash_input_denormal(input, fpst);
691     uint32_t f16_val = float16_val(f16);
692     uint32_t f16_sign = float16_is_neg(f16);
693     int f16_exp = extract32(f16_val, 10, 5);
694     uint32_t f16_frac = extract32(f16_val, 0, 10);
695     uint64_t f64_frac;
696 
697     if (float16_is_any_nan(f16)) {
698         float16 nan = f16;
699         if (float16_is_signaling_nan(f16, fpst)) {
700             float_raise(float_flag_invalid, fpst);
701             if (!fpst->default_nan_mode) {
702                 nan = float16_silence_nan(f16, fpst);
703             }
704         }
705         if (fpst->default_nan_mode) {
706             nan =  float16_default_nan(fpst);
707         }
708         return nan;
709     } else if (float16_is_infinity(f16)) {
710         return float16_set_sign(float16_zero, float16_is_neg(f16));
711     } else if (float16_is_zero(f16)) {
712         float_raise(float_flag_divbyzero, fpst);
713         return float16_set_sign(float16_infinity, float16_is_neg(f16));
714     } else if (float16_abs(f16) < (1 << 8)) {
715         /* Abs(value) < 2.0^-16 */
716         float_raise(float_flag_overflow | float_flag_inexact, fpst);
717         if (round_to_inf(fpst, f16_sign)) {
718             return float16_set_sign(float16_infinity, f16_sign);
719         } else {
720             return float16_set_sign(float16_maxnorm, f16_sign);
721         }
722     } else if (f16_exp >= 29 && fpst->flush_to_zero) {
723         float_raise(float_flag_underflow, fpst);
724         return float16_set_sign(float16_zero, float16_is_neg(f16));
725     }
726 
727     f64_frac = call_recip_estimate(&f16_exp, 29,
728                                    ((uint64_t) f16_frac) << (52 - 10));
729 
730     /* result = sign : result_exp<4:0> : fraction<51:42> */
731     f16_val = deposit32(0, 15, 1, f16_sign);
732     f16_val = deposit32(f16_val, 10, 5, f16_exp);
733     f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
734     return make_float16(f16_val);
735 }
736 
HELPER(recpe_f32)737 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
738 {
739     float_status *fpst = fpstp;
740     float32 f32 = float32_squash_input_denormal(input, fpst);
741     uint32_t f32_val = float32_val(f32);
742     bool f32_sign = float32_is_neg(f32);
743     int f32_exp = extract32(f32_val, 23, 8);
744     uint32_t f32_frac = extract32(f32_val, 0, 23);
745     uint64_t f64_frac;
746 
747     if (float32_is_any_nan(f32)) {
748         float32 nan = f32;
749         if (float32_is_signaling_nan(f32, fpst)) {
750             float_raise(float_flag_invalid, fpst);
751             if (!fpst->default_nan_mode) {
752                 nan = float32_silence_nan(f32, fpst);
753             }
754         }
755         if (fpst->default_nan_mode) {
756             nan =  float32_default_nan(fpst);
757         }
758         return nan;
759     } else if (float32_is_infinity(f32)) {
760         return float32_set_sign(float32_zero, float32_is_neg(f32));
761     } else if (float32_is_zero(f32)) {
762         float_raise(float_flag_divbyzero, fpst);
763         return float32_set_sign(float32_infinity, float32_is_neg(f32));
764     } else if (float32_abs(f32) < (1ULL << 21)) {
765         /* Abs(value) < 2.0^-128 */
766         float_raise(float_flag_overflow | float_flag_inexact, fpst);
767         if (round_to_inf(fpst, f32_sign)) {
768             return float32_set_sign(float32_infinity, f32_sign);
769         } else {
770             return float32_set_sign(float32_maxnorm, f32_sign);
771         }
772     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
773         float_raise(float_flag_underflow, fpst);
774         return float32_set_sign(float32_zero, float32_is_neg(f32));
775     }
776 
777     f64_frac = call_recip_estimate(&f32_exp, 253,
778                                    ((uint64_t) f32_frac) << (52 - 23));
779 
780     /* result = sign : result_exp<7:0> : fraction<51:29> */
781     f32_val = deposit32(0, 31, 1, f32_sign);
782     f32_val = deposit32(f32_val, 23, 8, f32_exp);
783     f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
784     return make_float32(f32_val);
785 }
786 
HELPER(recpe_f64)787 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
788 {
789     float_status *fpst = fpstp;
790     float64 f64 = float64_squash_input_denormal(input, fpst);
791     uint64_t f64_val = float64_val(f64);
792     bool f64_sign = float64_is_neg(f64);
793     int f64_exp = extract64(f64_val, 52, 11);
794     uint64_t f64_frac = extract64(f64_val, 0, 52);
795 
796     /* Deal with any special cases */
797     if (float64_is_any_nan(f64)) {
798         float64 nan = f64;
799         if (float64_is_signaling_nan(f64, fpst)) {
800             float_raise(float_flag_invalid, fpst);
801             if (!fpst->default_nan_mode) {
802                 nan = float64_silence_nan(f64, fpst);
803             }
804         }
805         if (fpst->default_nan_mode) {
806             nan =  float64_default_nan(fpst);
807         }
808         return nan;
809     } else if (float64_is_infinity(f64)) {
810         return float64_set_sign(float64_zero, float64_is_neg(f64));
811     } else if (float64_is_zero(f64)) {
812         float_raise(float_flag_divbyzero, fpst);
813         return float64_set_sign(float64_infinity, float64_is_neg(f64));
814     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
815         /* Abs(value) < 2.0^-1024 */
816         float_raise(float_flag_overflow | float_flag_inexact, fpst);
817         if (round_to_inf(fpst, f64_sign)) {
818             return float64_set_sign(float64_infinity, f64_sign);
819         } else {
820             return float64_set_sign(float64_maxnorm, f64_sign);
821         }
822     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
823         float_raise(float_flag_underflow, fpst);
824         return float64_set_sign(float64_zero, float64_is_neg(f64));
825     }
826 
827     f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
828 
829     /* result = sign : result_exp<10:0> : fraction<51:0>; */
830     f64_val = deposit64(0, 63, 1, f64_sign);
831     f64_val = deposit64(f64_val, 52, 11, f64_exp);
832     f64_val = deposit64(f64_val, 0, 52, f64_frac);
833     return make_float64(f64_val);
834 }
835 
836 /* The algorithm that must be used to calculate the estimate
837  * is specified by the ARM ARM.
838  */
839 
do_recip_sqrt_estimate(int a)840 static int do_recip_sqrt_estimate(int a)
841 {
842     int b, estimate;
843 
844     assert(128 <= a && a < 512);
845     if (a < 256) {
846         a = a * 2 + 1;
847     } else {
848         a = (a >> 1) << 1;
849         a = (a + 1) * 2;
850     }
851     b = 512;
852     while (a * (b + 1) * (b + 1) < (1 << 28)) {
853         b += 1;
854     }
855     estimate = (b + 1) / 2;
856     assert(256 <= estimate && estimate < 512);
857 
858     return estimate;
859 }
860 
861 
recip_sqrt_estimate(int * exp,int exp_off,uint64_t frac)862 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
863 {
864     int estimate;
865     uint32_t scaled;
866 
867     if (*exp == 0) {
868         while (extract64(frac, 51, 1) == 0) {
869             frac = frac << 1;
870             *exp -= 1;
871         }
872         frac = extract64(frac, 0, 51) << 1;
873     }
874 
875     if (*exp & 1) {
876         /* scaled = UInt('01':fraction<51:45>) */
877         scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
878     } else {
879         /* scaled = UInt('1':fraction<51:44>) */
880         scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
881     }
882     estimate = do_recip_sqrt_estimate(scaled);
883 
884     *exp = (exp_off - *exp) / 2;
885     return extract64(estimate, 0, 8) << 44;
886 }
887 
HELPER(rsqrte_f16)888 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
889 {
890     float_status *s = fpstp;
891     float16 f16 = float16_squash_input_denormal(input, s);
892     uint16_t val = float16_val(f16);
893     bool f16_sign = float16_is_neg(f16);
894     int f16_exp = extract32(val, 10, 5);
895     uint16_t f16_frac = extract32(val, 0, 10);
896     uint64_t f64_frac;
897 
898     if (float16_is_any_nan(f16)) {
899         float16 nan = f16;
900         if (float16_is_signaling_nan(f16, s)) {
901             float_raise(float_flag_invalid, s);
902             if (!s->default_nan_mode) {
903                 nan = float16_silence_nan(f16, fpstp);
904             }
905         }
906         if (s->default_nan_mode) {
907             nan =  float16_default_nan(s);
908         }
909         return nan;
910     } else if (float16_is_zero(f16)) {
911         float_raise(float_flag_divbyzero, s);
912         return float16_set_sign(float16_infinity, f16_sign);
913     } else if (f16_sign) {
914         float_raise(float_flag_invalid, s);
915         return float16_default_nan(s);
916     } else if (float16_is_infinity(f16)) {
917         return float16_zero;
918     }
919 
920     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
921      * preserving the parity of the exponent.  */
922 
923     f64_frac = ((uint64_t) f16_frac) << (52 - 10);
924 
925     f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
926 
927     /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
928     val = deposit32(0, 15, 1, f16_sign);
929     val = deposit32(val, 10, 5, f16_exp);
930     val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
931     return make_float16(val);
932 }
933 
HELPER(rsqrte_f32)934 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
935 {
936     float_status *s = fpstp;
937     float32 f32 = float32_squash_input_denormal(input, s);
938     uint32_t val = float32_val(f32);
939     uint32_t f32_sign = float32_is_neg(f32);
940     int f32_exp = extract32(val, 23, 8);
941     uint32_t f32_frac = extract32(val, 0, 23);
942     uint64_t f64_frac;
943 
944     if (float32_is_any_nan(f32)) {
945         float32 nan = f32;
946         if (float32_is_signaling_nan(f32, s)) {
947             float_raise(float_flag_invalid, s);
948             if (!s->default_nan_mode) {
949                 nan = float32_silence_nan(f32, fpstp);
950             }
951         }
952         if (s->default_nan_mode) {
953             nan =  float32_default_nan(s);
954         }
955         return nan;
956     } else if (float32_is_zero(f32)) {
957         float_raise(float_flag_divbyzero, s);
958         return float32_set_sign(float32_infinity, float32_is_neg(f32));
959     } else if (float32_is_neg(f32)) {
960         float_raise(float_flag_invalid, s);
961         return float32_default_nan(s);
962     } else if (float32_is_infinity(f32)) {
963         return float32_zero;
964     }
965 
966     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
967      * preserving the parity of the exponent.  */
968 
969     f64_frac = ((uint64_t) f32_frac) << 29;
970 
971     f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
972 
973     /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
974     val = deposit32(0, 31, 1, f32_sign);
975     val = deposit32(val, 23, 8, f32_exp);
976     val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
977     return make_float32(val);
978 }
979 
HELPER(rsqrte_f64)980 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
981 {
982     float_status *s = fpstp;
983     float64 f64 = float64_squash_input_denormal(input, s);
984     uint64_t val = float64_val(f64);
985     bool f64_sign = float64_is_neg(f64);
986     int f64_exp = extract64(val, 52, 11);
987     uint64_t f64_frac = extract64(val, 0, 52);
988 
989     if (float64_is_any_nan(f64)) {
990         float64 nan = f64;
991         if (float64_is_signaling_nan(f64, s)) {
992             float_raise(float_flag_invalid, s);
993             if (!s->default_nan_mode) {
994                 nan = float64_silence_nan(f64, fpstp);
995             }
996         }
997         if (s->default_nan_mode) {
998             nan =  float64_default_nan(s);
999         }
1000         return nan;
1001     } else if (float64_is_zero(f64)) {
1002         float_raise(float_flag_divbyzero, s);
1003         return float64_set_sign(float64_infinity, float64_is_neg(f64));
1004     } else if (float64_is_neg(f64)) {
1005         float_raise(float_flag_invalid, s);
1006         return float64_default_nan(s);
1007     } else if (float64_is_infinity(f64)) {
1008         return float64_zero;
1009     }
1010 
1011     f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
1012 
1013     /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
1014     val = deposit64(0, 61, 1, f64_sign);
1015     val = deposit64(val, 52, 11, f64_exp);
1016     val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
1017     return make_float64(val);
1018 }
1019 
HELPER(recpe_u32)1020 uint32_t HELPER(recpe_u32)(uint32_t a)
1021 {
1022     int input, estimate;
1023 
1024     if ((a & 0x80000000) == 0) {
1025         return 0xffffffff;
1026     }
1027 
1028     input = extract32(a, 23, 9);
1029     estimate = recip_estimate(input);
1030 
1031     return deposit32(0, (32 - 9), 9, estimate);
1032 }
1033 
HELPER(rsqrte_u32)1034 uint32_t HELPER(rsqrte_u32)(uint32_t a)
1035 {
1036     int estimate;
1037 
1038     if ((a & 0xc0000000) == 0) {
1039         return 0xffffffff;
1040     }
1041 
1042     estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
1043 
1044     return deposit32(0, 23, 9, estimate);
1045 }
1046 
1047 /* VFPv4 fused multiply-accumulate */
VFP_HELPER(muladd,h)1048 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
1049                                    dh_ctype_f16 c, void *fpstp)
1050 {
1051     float_status *fpst = fpstp;
1052     return float16_muladd(a, b, c, 0, fpst);
1053 }
1054 
VFP_HELPER(muladd,s)1055 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
1056 {
1057     float_status *fpst = fpstp;
1058     return float32_muladd(a, b, c, 0, fpst);
1059 }
1060 
VFP_HELPER(muladd,d)1061 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
1062 {
1063     float_status *fpst = fpstp;
1064     return float64_muladd(a, b, c, 0, fpst);
1065 }
1066 
1067 /* ARMv8 round to integral */
HELPER(rinth_exact)1068 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
1069 {
1070     return float16_round_to_int(x, fp_status);
1071 }
1072 
HELPER(rints_exact)1073 float32 HELPER(rints_exact)(float32 x, void *fp_status)
1074 {
1075     return float32_round_to_int(x, fp_status);
1076 }
1077 
HELPER(rintd_exact)1078 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
1079 {
1080     return float64_round_to_int(x, fp_status);
1081 }
1082 
HELPER(rinth)1083 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
1084 {
1085     int old_flags = get_float_exception_flags(fp_status), new_flags;
1086     float16 ret;
1087 
1088     ret = float16_round_to_int(x, fp_status);
1089 
1090     /* Suppress any inexact exceptions the conversion produced */
1091     if (!(old_flags & float_flag_inexact)) {
1092         new_flags = get_float_exception_flags(fp_status);
1093         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1094     }
1095 
1096     return ret;
1097 }
1098 
HELPER(rints)1099 float32 HELPER(rints)(float32 x, void *fp_status)
1100 {
1101     int old_flags = get_float_exception_flags(fp_status), new_flags;
1102     float32 ret;
1103 
1104     ret = float32_round_to_int(x, fp_status);
1105 
1106     /* Suppress any inexact exceptions the conversion produced */
1107     if (!(old_flags & float_flag_inexact)) {
1108         new_flags = get_float_exception_flags(fp_status);
1109         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1110     }
1111 
1112     return ret;
1113 }
1114 
HELPER(rintd)1115 float64 HELPER(rintd)(float64 x, void *fp_status)
1116 {
1117     int old_flags = get_float_exception_flags(fp_status), new_flags;
1118     float64 ret;
1119 
1120     ret = float64_round_to_int(x, fp_status);
1121 
1122     new_flags = get_float_exception_flags(fp_status);
1123 
1124     /* Suppress any inexact exceptions the conversion produced */
1125     if (!(old_flags & float_flag_inexact)) {
1126         new_flags = get_float_exception_flags(fp_status);
1127         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1128     }
1129 
1130     return ret;
1131 }
1132 
1133 /* Convert ARM rounding mode to softfloat */
1134 const FloatRoundMode arm_rmode_to_sf_map[] = {
1135     [FPROUNDING_TIEEVEN] = float_round_nearest_even,
1136     [FPROUNDING_POSINF] = float_round_up,
1137     [FPROUNDING_NEGINF] = float_round_down,
1138     [FPROUNDING_ZERO] = float_round_to_zero,
1139     [FPROUNDING_TIEAWAY] = float_round_ties_away,
1140     [FPROUNDING_ODD] = float_round_to_odd,
1141 };
1142 
1143 /*
1144  * Implement float64 to int32_t conversion without saturation;
1145  * the result is supplied modulo 2^32.
1146  */
HELPER(fjcvtzs)1147 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
1148 {
1149     float_status *status = vstatus;
1150     uint32_t frac, e_old, e_new;
1151     bool inexact;
1152 
1153     e_old = get_float_exception_flags(status);
1154     set_float_exception_flags(0, status);
1155     frac = float64_to_int32_modulo(value, float_round_to_zero, status);
1156     e_new = get_float_exception_flags(status);
1157     set_float_exception_flags(e_old | e_new, status);
1158 
1159     /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */
1160     inexact = e_new & (float_flag_inexact |
1161                        float_flag_input_denormal |
1162                        float_flag_invalid);
1163 
1164     /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1165     inexact |= value == float64_chs(float64_zero);
1166 
1167     /* Pack the result and the env->ZF representation of Z together.  */
1168     return deposit64(frac, 32, 32, inexact);
1169 }
1170 
HELPER(vjcvt)1171 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
1172 {
1173     uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
1174     uint32_t result = pair;
1175     uint32_t z = (pair >> 32) == 0;
1176 
1177     /* Store Z, clear NCV, in FPSCR.NZCV.  */
1178     env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z);
1179 
1180     return result;
1181 }
1182 
1183 /* Round a float32 to an integer that fits in int32_t or int64_t.  */
frint_s(float32 f,float_status * fpst,int intsize)1184 static float32 frint_s(float32 f, float_status *fpst, int intsize)
1185 {
1186     int old_flags = get_float_exception_flags(fpst);
1187     uint32_t exp = extract32(f, 23, 8);
1188 
1189     if (unlikely(exp == 0xff)) {
1190         /* NaN or Inf.  */
1191         goto overflow;
1192     }
1193 
1194     /* Round and re-extract the exponent.  */
1195     f = float32_round_to_int(f, fpst);
1196     exp = extract32(f, 23, 8);
1197 
1198     /* Validate the range of the result.  */
1199     if (exp < 126 + intsize) {
1200         /* abs(F) <= INT{N}_MAX */
1201         return f;
1202     }
1203     if (exp == 126 + intsize) {
1204         uint32_t sign = extract32(f, 31, 1);
1205         uint32_t frac = extract32(f, 0, 23);
1206         if (sign && frac == 0) {
1207             /* F == INT{N}_MIN */
1208             return f;
1209         }
1210     }
1211 
1212  overflow:
1213     /*
1214      * Raise Invalid and return INT{N}_MIN as a float.  Revert any
1215      * inexact exception float32_round_to_int may have raised.
1216      */
1217     set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1218     return (0x100u + 126u + intsize) << 23;
1219 }
1220 
HELPER(frint32_s)1221 float32 HELPER(frint32_s)(float32 f, void *fpst)
1222 {
1223     return frint_s(f, fpst, 32);
1224 }
1225 
HELPER(frint64_s)1226 float32 HELPER(frint64_s)(float32 f, void *fpst)
1227 {
1228     return frint_s(f, fpst, 64);
1229 }
1230 
1231 /* Round a float64 to an integer that fits in int32_t or int64_t.  */
frint_d(float64 f,float_status * fpst,int intsize)1232 static float64 frint_d(float64 f, float_status *fpst, int intsize)
1233 {
1234     int old_flags = get_float_exception_flags(fpst);
1235     uint32_t exp = extract64(f, 52, 11);
1236 
1237     if (unlikely(exp == 0x7ff)) {
1238         /* NaN or Inf.  */
1239         goto overflow;
1240     }
1241 
1242     /* Round and re-extract the exponent.  */
1243     f = float64_round_to_int(f, fpst);
1244     exp = extract64(f, 52, 11);
1245 
1246     /* Validate the range of the result.  */
1247     if (exp < 1022 + intsize) {
1248         /* abs(F) <= INT{N}_MAX */
1249         return f;
1250     }
1251     if (exp == 1022 + intsize) {
1252         uint64_t sign = extract64(f, 63, 1);
1253         uint64_t frac = extract64(f, 0, 52);
1254         if (sign && frac == 0) {
1255             /* F == INT{N}_MIN */
1256             return f;
1257         }
1258     }
1259 
1260  overflow:
1261     /*
1262      * Raise Invalid and return INT{N}_MIN as a float.  Revert any
1263      * inexact exception float64_round_to_int may have raised.
1264      */
1265     set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1266     return (uint64_t)(0x800 + 1022 + intsize) << 52;
1267 }
1268 
HELPER(frint32_d)1269 float64 HELPER(frint32_d)(float64 f, void *fpst)
1270 {
1271     return frint_d(f, fpst, 32);
1272 }
1273 
HELPER(frint64_d)1274 float64 HELPER(frint64_d)(float64 f, void *fpst)
1275 {
1276     return frint_d(f, fpst, 64);
1277 }
1278 
HELPER(check_hcr_el2_trap)1279 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
1280 {
1281     uint32_t syndrome;
1282 
1283     switch (reg) {
1284     case ARM_VFP_MVFR0:
1285     case ARM_VFP_MVFR1:
1286     case ARM_VFP_MVFR2:
1287         if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
1288             return;
1289         }
1290         break;
1291     case ARM_VFP_FPSID:
1292         if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
1293             return;
1294         }
1295         break;
1296     default:
1297         g_assert_not_reached();
1298     }
1299 
1300     syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
1301                 | ARM_EL_IL
1302                 | (1 << 24) | (0xe << 20) | (7 << 14)
1303                 | (reg << 10) | (rt << 5) | 1);
1304 
1305     raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
1306 }
1307 
1308 #endif
1309