1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2 |* *| 3 |* Intrinsic Function Source Fragment *| 4 |* *| 5 |* Automatically generated file, do not edit! *| 6 |* *| 7 \*===----------------------------------------------------------------------===*/ 8 9 #ifndef LLVM_IR_INTRINSIC_RISCV_ENUMS_H 10 #define LLVM_IR_INTRINSIC_RISCV_ENUMS_H 11 12 namespace llvm { 13 namespace Intrinsic { 14 enum RISCVIntrinsics : unsigned { 15 // Enum values for intrinsics 16 riscv_masked_atomicrmw_add_i32 = 6039, // llvm.riscv.masked.atomicrmw.add.i32 17 riscv_masked_atomicrmw_add_i64, // llvm.riscv.masked.atomicrmw.add.i64 18 riscv_masked_atomicrmw_max_i32, // llvm.riscv.masked.atomicrmw.max.i32 19 riscv_masked_atomicrmw_max_i64, // llvm.riscv.masked.atomicrmw.max.i64 20 riscv_masked_atomicrmw_min_i32, // llvm.riscv.masked.atomicrmw.min.i32 21 riscv_masked_atomicrmw_min_i64, // llvm.riscv.masked.atomicrmw.min.i64 22 riscv_masked_atomicrmw_nand_i32, // llvm.riscv.masked.atomicrmw.nand.i32 23 riscv_masked_atomicrmw_nand_i64, // llvm.riscv.masked.atomicrmw.nand.i64 24 riscv_masked_atomicrmw_sub_i32, // llvm.riscv.masked.atomicrmw.sub.i32 25 riscv_masked_atomicrmw_sub_i64, // llvm.riscv.masked.atomicrmw.sub.i64 26 riscv_masked_atomicrmw_umax_i32, // llvm.riscv.masked.atomicrmw.umax.i32 27 riscv_masked_atomicrmw_umax_i64, // llvm.riscv.masked.atomicrmw.umax.i64 28 riscv_masked_atomicrmw_umin_i32, // llvm.riscv.masked.atomicrmw.umin.i32 29 riscv_masked_atomicrmw_umin_i64, // llvm.riscv.masked.atomicrmw.umin.i64 30 riscv_masked_atomicrmw_xchg_i32, // llvm.riscv.masked.atomicrmw.xchg.i32 31 riscv_masked_atomicrmw_xchg_i64, // llvm.riscv.masked.atomicrmw.xchg.i64 32 riscv_masked_cmpxchg_i32, // llvm.riscv.masked.cmpxchg.i32 33 riscv_masked_cmpxchg_i64, // llvm.riscv.masked.cmpxchg.i64 34 }; // enum 35 } // namespace Intrinsic 36 } // namespace llvm 37 38 #endif 39