1 /* $OpenBSD: if_rsu.c,v 1.53 2024/05/23 03:21:08 jsg Exp $ */
2
3 /*-
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Driver for Realtek RTL8188SU/RTL8191SU/RTL8192SU.
21 */
22
23 #include "bpfilter.h"
24
25 #include <sys/param.h>
26 #include <sys/sockio.h>
27 #include <sys/mbuf.h>
28 #include <sys/systm.h>
29 #include <sys/timeout.h>
30 #include <sys/device.h>
31 #include <sys/endian.h>
32
33 #include <machine/intr.h>
34
35 #if NBPFILTER > 0
36 #include <net/bpf.h>
37 #endif
38 #include <net/if.h>
39 #include <net/if_dl.h>
40 #include <net/if_media.h>
41
42 #include <netinet/in.h>
43 #include <netinet/if_ether.h>
44
45 #include <net80211/ieee80211_var.h>
46 #include <net80211/ieee80211_radiotap.h>
47
48 #include <dev/usb/usb.h>
49 #include <dev/usb/usbdi.h>
50 #include <dev/usb/usbdi_util.h>
51 #include <dev/usb/usbdevs.h>
52
53 #include <dev/usb/if_rsureg.h>
54
55 #ifdef RSU_DEBUG
56 #define DPRINTF(x) do { if (rsu_debug) printf x; } while (0)
57 #define DPRINTFN(n, x) do { if (rsu_debug >= (n)) printf x; } while (0)
58 int rsu_debug = 4;
59 #else
60 #define DPRINTF(x)
61 #define DPRINTFN(n, x)
62 #endif
63
64 /*
65 * NB: When updating this list of devices, beware to also update the list
66 * of devices that have HT support disabled below, if applicable.
67 */
68 static const struct usb_devno rsu_devs[] = {
69 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_RTL8192SU },
70 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_USBN10 },
71 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 },
72 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_1 },
73 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_2 },
74 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_3 },
75 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 },
76 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_5 },
77 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_1 },
78 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_2 },
79 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192SU_3 },
80 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_1 },
81 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_2 },
82 { USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_RTL8192SU_3 },
83 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192SU },
84 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA131A1 },
85 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_1 },
86 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_RTL8192SU_2 },
87 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_1 },
88 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_2 },
89 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192SU_3 },
90 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUN54 },
91 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUM300 },
92 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_1 },
93 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192SU_2 },
94 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GWUSNANO },
95 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8171 },
96 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8172 },
97 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8173 },
98 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8174 },
99 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192SU },
100 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8712 },
101 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8713 },
102 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_1 },
103 { USB_VENDOR_SENAO, USB_PRODUCT_SENAO_RTL8192SU_2 },
104 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL349V1 },
105 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WL353 },
106 { USB_VENDOR_SWEEX2, USB_PRODUCT_SWEEX2_LW154 }
107 };
108
109 /* List of devices that have HT support disabled. */
110 static const struct usb_devno rsu_devs_noht[] = {
111 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192SU_1 },
112 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8192SU_4 }
113 };
114
115 int rsu_match(struct device *, void *, void *);
116 void rsu_attach(struct device *, struct device *, void *);
117 int rsu_detach(struct device *, int);
118 int rsu_open_pipes(struct rsu_softc *);
119 void rsu_close_pipes(struct rsu_softc *);
120 int rsu_alloc_rx_list(struct rsu_softc *);
121 void rsu_free_rx_list(struct rsu_softc *);
122 int rsu_alloc_tx_list(struct rsu_softc *);
123 void rsu_free_tx_list(struct rsu_softc *);
124 void rsu_task(void *);
125 void rsu_do_async(struct rsu_softc *,
126 void (*)(struct rsu_softc *, void *), void *, int);
127 void rsu_wait_async(struct rsu_softc *);
128 int rsu_write_region_1(struct rsu_softc *, uint16_t, uint8_t *,
129 int);
130 void rsu_write_1(struct rsu_softc *, uint16_t, uint8_t);
131 void rsu_write_2(struct rsu_softc *, uint16_t, uint16_t);
132 void rsu_write_4(struct rsu_softc *, uint16_t, uint32_t);
133 int rsu_read_region_1(struct rsu_softc *, uint16_t, uint8_t *,
134 int);
135 uint8_t rsu_read_1(struct rsu_softc *, uint16_t);
136 uint16_t rsu_read_2(struct rsu_softc *, uint16_t);
137 uint32_t rsu_read_4(struct rsu_softc *, uint16_t);
138 int rsu_fw_iocmd(struct rsu_softc *, uint32_t);
139 uint8_t rsu_efuse_read_1(struct rsu_softc *, uint16_t);
140 int rsu_read_rom(struct rsu_softc *);
141 int rsu_fw_cmd(struct rsu_softc *, uint8_t, void *, int);
142 int rsu_media_change(struct ifnet *);
143 void rsu_calib_to(void *);
144 void rsu_calib_cb(struct rsu_softc *, void *);
145 int rsu_newstate(struct ieee80211com *, enum ieee80211_state, int);
146 void rsu_newstate_cb(struct rsu_softc *, void *);
147 int rsu_set_key(struct ieee80211com *, struct ieee80211_node *,
148 struct ieee80211_key *);
149 void rsu_set_key_cb(struct rsu_softc *, void *);
150 void rsu_delete_key(struct ieee80211com *, struct ieee80211_node *,
151 struct ieee80211_key *);
152 void rsu_delete_key_cb(struct rsu_softc *, void *);
153 int rsu_site_survey(struct rsu_softc *);
154 int rsu_join_bss(struct rsu_softc *, struct ieee80211_node *);
155 int rsu_disconnect(struct rsu_softc *);
156 void rsu_event_survey(struct rsu_softc *, uint8_t *, int);
157 void rsu_event_join_bss(struct rsu_softc *, uint8_t *, int);
158 void rsu_rx_event(struct rsu_softc *, uint8_t, uint8_t *, int);
159 void rsu_rx_multi_event(struct rsu_softc *, uint8_t *, int);
160 int8_t rsu_get_rssi(struct rsu_softc *, int, void *);
161 void rsu_rx_frame(struct rsu_softc *, uint8_t *, int,
162 struct mbuf_list *);
163 void rsu_rx_multi_frame(struct rsu_softc *, uint8_t *, int);
164 void rsu_rxeof(struct usbd_xfer *, void *, usbd_status);
165 void rsu_txeof(struct usbd_xfer *, void *, usbd_status);
166 int rsu_tx(struct rsu_softc *, struct mbuf *,
167 struct ieee80211_node *);
168 int rsu_send_mgmt(struct ieee80211com *, struct ieee80211_node *,
169 int, int, int);
170 void rsu_start(struct ifnet *);
171 void rsu_watchdog(struct ifnet *);
172 int rsu_ioctl(struct ifnet *, u_long, caddr_t);
173 void rsu_power_on_acut(struct rsu_softc *);
174 void rsu_power_on_bcut(struct rsu_softc *);
175 void rsu_power_off(struct rsu_softc *);
176 int rsu_fw_loadsection(struct rsu_softc *, uint8_t *, int);
177 int rsu_load_firmware(struct rsu_softc *);
178 int rsu_init(struct ifnet *);
179 void rsu_stop(struct ifnet *);
180
181 struct cfdriver rsu_cd = {
182 NULL, "rsu", DV_IFNET
183 };
184
185 const struct cfattach rsu_ca = {
186 sizeof(struct rsu_softc), rsu_match, rsu_attach, rsu_detach,
187 };
188
189 int
rsu_match(struct device * parent,void * match,void * aux)190 rsu_match(struct device *parent, void *match, void *aux)
191 {
192 struct usb_attach_arg *uaa = aux;
193
194 if (uaa->iface == NULL || uaa->configno != 1)
195 return (UMATCH_NONE);
196
197 return ((usb_lookup(rsu_devs, uaa->vendor, uaa->product) != NULL) ?
198 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE);
199 }
200
201 void
rsu_attach(struct device * parent,struct device * self,void * aux)202 rsu_attach(struct device *parent, struct device *self, void *aux)
203 {
204 struct rsu_softc *sc = (struct rsu_softc *)self;
205 struct usb_attach_arg *uaa = aux;
206 struct ieee80211com *ic = &sc->sc_ic;
207 struct ifnet *ifp = &ic->ic_if;
208 int i, error;
209
210 sc->sc_udev = uaa->device;
211 sc->sc_iface = uaa->iface;
212
213 usb_init_task(&sc->sc_task, rsu_task, sc, USB_TASK_TYPE_GENERIC);
214 timeout_set(&sc->calib_to, rsu_calib_to, sc);
215
216 /* Read chip revision. */
217 sc->cut = MS(rsu_read_4(sc, R92S_PMC_FSM), R92S_PMC_FSM_CUT);
218 if (sc->cut != 3)
219 sc->cut = (sc->cut >> 1) + 1;
220
221 error = rsu_read_rom(sc);
222 if (error != 0) {
223 printf("%s: could not read ROM\n", sc->sc_dev.dv_xname);
224 return;
225 }
226 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->rom[0x12]);
227
228 printf("%s: MAC/BB RTL8712 cut %d, address %s\n",
229 sc->sc_dev.dv_xname, sc->cut, ether_sprintf(ic->ic_myaddr));
230
231 if (rsu_open_pipes(sc) != 0)
232 return;
233
234 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */
235 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */
236 ic->ic_state = IEEE80211_S_INIT;
237
238 /* Set device capabilities. */
239 ic->ic_caps =
240 IEEE80211_C_SCANALL | /* Hardware scan. */
241 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
242 IEEE80211_C_SHSLOT | /* Short slot time supported. */
243 IEEE80211_C_WEP | /* WEP. */
244 IEEE80211_C_RSN; /* WPA/RSN. */
245 /* Check if HT support is present. */
246 if (usb_lookup(rsu_devs_noht, uaa->vendor, uaa->product) == NULL) {
247 #ifdef notyet
248 /* Set HT capabilities. */
249 ic->ic_htcaps =
250 IEEE80211_HTCAP_CBW20_40 |
251 IEEE80211_HTCAP_DSSSCCK40;
252 /* Set supported HT rates. */
253 for (i = 0; i < 2; i++)
254 ic->ic_sup_mcs[i] = 0xff;
255 #endif
256 }
257
258 /* Set supported .11b and .11g rates. */
259 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
260 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
261
262 /* Set supported .11b and .11g channels (1 through 14). */
263 for (i = 1; i <= 14; i++) {
264 ic->ic_channels[i].ic_freq =
265 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
266 ic->ic_channels[i].ic_flags =
267 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
268 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
269 }
270
271 ifp->if_softc = sc;
272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
273 ifp->if_ioctl = rsu_ioctl;
274 ifp->if_start = rsu_start;
275 ifp->if_watchdog = rsu_watchdog;
276 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
277
278 if_attach(ifp);
279 ieee80211_ifattach(ifp);
280 #ifdef notyet
281 ic->ic_set_key = rsu_set_key;
282 ic->ic_delete_key = rsu_delete_key;
283 #endif
284 /* Override state transition machine. */
285 sc->sc_newstate = ic->ic_newstate;
286 ic->ic_newstate = rsu_newstate;
287 ic->ic_send_mgmt = rsu_send_mgmt;
288 ieee80211_media_init(ifp, rsu_media_change, ieee80211_media_status);
289
290 #if NBPFILTER > 0
291 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO,
292 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN);
293
294 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
295 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
296 sc->sc_rxtap.wr_ihdr.it_present = htole32(RSU_RX_RADIOTAP_PRESENT);
297
298 sc->sc_txtap_len = sizeof(sc->sc_txtapu);
299 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
300 sc->sc_txtap.wt_ihdr.it_present = htole32(RSU_TX_RADIOTAP_PRESENT);
301 #endif
302 }
303
304 int
rsu_detach(struct device * self,int flags)305 rsu_detach(struct device *self, int flags)
306 {
307 struct rsu_softc *sc = (struct rsu_softc *)self;
308 struct ifnet *ifp = &sc->sc_ic.ic_if;
309 int s;
310
311 s = splusb();
312
313 if (timeout_initialized(&sc->calib_to))
314 timeout_del(&sc->calib_to);
315
316 /* Wait for all async commands to complete. */
317 usb_rem_wait_task(sc->sc_udev, &sc->sc_task);
318
319 usbd_ref_wait(sc->sc_udev);
320
321 if (ifp->if_softc != NULL) {
322 ieee80211_ifdetach(ifp);
323 if_detach(ifp);
324 }
325
326 /* Abort and close Tx/Rx pipes. */
327 rsu_close_pipes(sc);
328
329 /* Free Tx/Rx buffers. */
330 rsu_free_tx_list(sc);
331 rsu_free_rx_list(sc);
332 splx(s);
333
334 return (0);
335 }
336
337 int
rsu_open_pipes(struct rsu_softc * sc)338 rsu_open_pipes(struct rsu_softc *sc)
339 {
340 usb_interface_descriptor_t *id;
341 int i, error;
342
343 /*
344 * Determine the number of Tx/Rx endpoints (there are chips with
345 * 4, 6 or 11 endpoints).
346 */
347 id = usbd_get_interface_descriptor(sc->sc_iface);
348 sc->npipes = id->bNumEndpoints;
349 if (sc->npipes == 4)
350 sc->qid2idx = rsu_qid2idx_4ep;
351 else if (sc->npipes == 6)
352 sc->qid2idx = rsu_qid2idx_6ep;
353 else /* Assume npipes==11; will fail below otherwise. */
354 sc->qid2idx = rsu_qid2idx_11ep;
355 DPRINTF(("%d endpoints configuration\n", sc->npipes));
356
357 /* Open all pipes. */
358 for (i = 0; i < MIN(sc->npipes, nitems(r92s_epaddr)); i++) {
359 error = usbd_open_pipe(sc->sc_iface, r92s_epaddr[i], 0,
360 &sc->pipe[i]);
361 if (error != 0) {
362 printf("%s: could not open bulk pipe 0x%02x\n",
363 sc->sc_dev.dv_xname, r92s_epaddr[i]);
364 break;
365 }
366 }
367 if (error != 0)
368 rsu_close_pipes(sc);
369 return (error);
370 }
371
372 void
rsu_close_pipes(struct rsu_softc * sc)373 rsu_close_pipes(struct rsu_softc *sc)
374 {
375 int i;
376
377 /* Close all pipes. */
378 for (i = 0; i < sc->npipes; i++) {
379 if (sc->pipe[i] == NULL)
380 continue;
381 usbd_close_pipe(sc->pipe[i]);
382 }
383 }
384
385 int
rsu_alloc_rx_list(struct rsu_softc * sc)386 rsu_alloc_rx_list(struct rsu_softc *sc)
387 {
388 struct rsu_rx_data *data;
389 int i, error = 0;
390
391 for (i = 0; i < RSU_RX_LIST_COUNT; i++) {
392 data = &sc->rx_data[i];
393
394 data->sc = sc; /* Backpointer for callbacks. */
395
396 data->xfer = usbd_alloc_xfer(sc->sc_udev);
397 if (data->xfer == NULL) {
398 printf("%s: could not allocate xfer\n",
399 sc->sc_dev.dv_xname);
400 error = ENOMEM;
401 break;
402 }
403 data->buf = usbd_alloc_buffer(data->xfer, RSU_RXBUFSZ);
404 if (data->buf == NULL) {
405 printf("%s: could not allocate xfer buffer\n",
406 sc->sc_dev.dv_xname);
407 error = ENOMEM;
408 break;
409 }
410 }
411 if (error != 0)
412 rsu_free_rx_list(sc);
413 return (error);
414 }
415
416 void
rsu_free_rx_list(struct rsu_softc * sc)417 rsu_free_rx_list(struct rsu_softc *sc)
418 {
419 int i;
420
421 /* NB: Caller must abort pipe first. */
422 for (i = 0; i < RSU_RX_LIST_COUNT; i++) {
423 if (sc->rx_data[i].xfer != NULL)
424 usbd_free_xfer(sc->rx_data[i].xfer);
425 sc->rx_data[i].xfer = NULL;
426 }
427 }
428
429 int
rsu_alloc_tx_list(struct rsu_softc * sc)430 rsu_alloc_tx_list(struct rsu_softc *sc)
431 {
432 struct rsu_tx_data *data;
433 int i, error = 0;
434
435 TAILQ_INIT(&sc->tx_free_list);
436 for (i = 0; i < RSU_TX_LIST_COUNT; i++) {
437 data = &sc->tx_data[i];
438
439 data->sc = sc; /* Backpointer for callbacks. */
440
441 data->xfer = usbd_alloc_xfer(sc->sc_udev);
442 if (data->xfer == NULL) {
443 printf("%s: could not allocate xfer\n",
444 sc->sc_dev.dv_xname);
445 error = ENOMEM;
446 break;
447 }
448 data->buf = usbd_alloc_buffer(data->xfer, RSU_TXBUFSZ);
449 if (data->buf == NULL) {
450 printf("%s: could not allocate xfer buffer\n",
451 sc->sc_dev.dv_xname);
452 error = ENOMEM;
453 break;
454 }
455 /* Append this Tx buffer to our free list. */
456 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next);
457 }
458 if (error != 0)
459 rsu_free_tx_list(sc);
460 return (error);
461 }
462
463 void
rsu_free_tx_list(struct rsu_softc * sc)464 rsu_free_tx_list(struct rsu_softc *sc)
465 {
466 int i;
467
468 /* NB: Caller must abort pipe first. */
469 for (i = 0; i < RSU_TX_LIST_COUNT; i++) {
470 if (sc->tx_data[i].xfer != NULL)
471 usbd_free_xfer(sc->tx_data[i].xfer);
472 sc->tx_data[i].xfer = NULL;
473 }
474 }
475
476 void
rsu_task(void * arg)477 rsu_task(void *arg)
478 {
479 struct rsu_softc *sc = arg;
480 struct rsu_host_cmd_ring *ring = &sc->cmdq;
481 struct rsu_host_cmd *cmd;
482 int s;
483
484 /* Process host commands. */
485 s = splusb();
486 while (ring->next != ring->cur) {
487 cmd = &ring->cmd[ring->next];
488 splx(s);
489 /* Invoke callback. */
490 cmd->cb(sc, cmd->data);
491 s = splusb();
492 ring->queued--;
493 ring->next = (ring->next + 1) % RSU_HOST_CMD_RING_COUNT;
494 }
495 splx(s);
496 }
497
498 void
rsu_do_async(struct rsu_softc * sc,void (* cb)(struct rsu_softc *,void *),void * arg,int len)499 rsu_do_async(struct rsu_softc *sc,
500 void (*cb)(struct rsu_softc *, void *), void *arg, int len)
501 {
502 struct rsu_host_cmd_ring *ring = &sc->cmdq;
503 struct rsu_host_cmd *cmd;
504 int s;
505
506 s = splusb();
507 cmd = &ring->cmd[ring->cur];
508 cmd->cb = cb;
509 KASSERT(len <= sizeof(cmd->data));
510 memcpy(cmd->data, arg, len);
511 ring->cur = (ring->cur + 1) % RSU_HOST_CMD_RING_COUNT;
512
513 /* If there is no pending command already, schedule a task. */
514 if (++ring->queued == 1)
515 usb_add_task(sc->sc_udev, &sc->sc_task);
516 splx(s);
517 }
518
519 void
rsu_wait_async(struct rsu_softc * sc)520 rsu_wait_async(struct rsu_softc *sc)
521 {
522 /* Wait for all queued asynchronous commands to complete. */
523 usb_wait_task(sc->sc_udev, &sc->sc_task);
524 }
525
526 int
rsu_write_region_1(struct rsu_softc * sc,uint16_t addr,uint8_t * buf,int len)527 rsu_write_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf,
528 int len)
529 {
530 usb_device_request_t req;
531
532 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
533 req.bRequest = R92S_REQ_REGS;
534 USETW(req.wValue, addr);
535 USETW(req.wIndex, 0);
536 USETW(req.wLength, len);
537 return (usbd_do_request(sc->sc_udev, &req, buf));
538 }
539
540 void
rsu_write_1(struct rsu_softc * sc,uint16_t addr,uint8_t val)541 rsu_write_1(struct rsu_softc *sc, uint16_t addr, uint8_t val)
542 {
543 rsu_write_region_1(sc, addr, &val, 1);
544 }
545
546 void
rsu_write_2(struct rsu_softc * sc,uint16_t addr,uint16_t val)547 rsu_write_2(struct rsu_softc *sc, uint16_t addr, uint16_t val)
548 {
549 val = htole16(val);
550 rsu_write_region_1(sc, addr, (uint8_t *)&val, 2);
551 }
552
553 void
rsu_write_4(struct rsu_softc * sc,uint16_t addr,uint32_t val)554 rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val)
555 {
556 val = htole32(val);
557 rsu_write_region_1(sc, addr, (uint8_t *)&val, 4);
558 }
559
560 int
rsu_read_region_1(struct rsu_softc * sc,uint16_t addr,uint8_t * buf,int len)561 rsu_read_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf,
562 int len)
563 {
564 usb_device_request_t req;
565
566 req.bmRequestType = UT_READ_VENDOR_DEVICE;
567 req.bRequest = R92S_REQ_REGS;
568 USETW(req.wValue, addr);
569 USETW(req.wIndex, 0);
570 USETW(req.wLength, len);
571 return (usbd_do_request(sc->sc_udev, &req, buf));
572 }
573
574 uint8_t
rsu_read_1(struct rsu_softc * sc,uint16_t addr)575 rsu_read_1(struct rsu_softc *sc, uint16_t addr)
576 {
577 uint8_t val;
578
579 if (rsu_read_region_1(sc, addr, &val, 1) != 0)
580 return (0xff);
581 return (val);
582 }
583
584 uint16_t
rsu_read_2(struct rsu_softc * sc,uint16_t addr)585 rsu_read_2(struct rsu_softc *sc, uint16_t addr)
586 {
587 uint16_t val;
588
589 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
590 return (0xffff);
591 return (letoh16(val));
592 }
593
594 uint32_t
rsu_read_4(struct rsu_softc * sc,uint16_t addr)595 rsu_read_4(struct rsu_softc *sc, uint16_t addr)
596 {
597 uint32_t val;
598
599 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
600 return (0xffffffff);
601 return (letoh32(val));
602 }
603
604 int
rsu_fw_iocmd(struct rsu_softc * sc,uint32_t iocmd)605 rsu_fw_iocmd(struct rsu_softc *sc, uint32_t iocmd)
606 {
607 int ntries;
608
609 rsu_write_4(sc, R92S_IOCMD_CTRL, iocmd);
610 DELAY(100);
611 for (ntries = 0; ntries < 50; ntries++) {
612 if (rsu_read_4(sc, R92S_IOCMD_CTRL) == 0)
613 return (0);
614 DELAY(10);
615 }
616 return (ETIMEDOUT);
617 }
618
619 uint8_t
rsu_efuse_read_1(struct rsu_softc * sc,uint16_t addr)620 rsu_efuse_read_1(struct rsu_softc *sc, uint16_t addr)
621 {
622 uint32_t reg;
623 int ntries;
624
625 reg = rsu_read_4(sc, R92S_EFUSE_CTRL);
626 reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr);
627 reg &= ~R92S_EFUSE_CTRL_VALID;
628 rsu_write_4(sc, R92S_EFUSE_CTRL, reg);
629 /* Wait for read operation to complete. */
630 for (ntries = 0; ntries < 100; ntries++) {
631 reg = rsu_read_4(sc, R92S_EFUSE_CTRL);
632 if (reg & R92S_EFUSE_CTRL_VALID)
633 return (MS(reg, R92S_EFUSE_CTRL_DATA));
634 DELAY(5);
635 }
636 printf("%s: could not read efuse byte at address 0x%x\n",
637 sc->sc_dev.dv_xname, addr);
638 return (0xff);
639 }
640
641 int
rsu_read_rom(struct rsu_softc * sc)642 rsu_read_rom(struct rsu_softc *sc)
643 {
644 uint8_t *rom = sc->rom;
645 uint16_t addr = 0;
646 uint32_t reg;
647 uint8_t off, msk;
648 int i;
649
650 /* Make sure that ROM type is eFuse and that autoload succeeded. */
651 reg = rsu_read_1(sc, R92S_EE_9346CR);
652 if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN)
653 return (EIO);
654
655 /* Turn on 2.5V to prevent eFuse leakage. */
656 reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3);
657 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80);
658 DELAY(1000);
659 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80);
660
661 /* Read full ROM image. */
662 memset(&sc->rom, 0xff, sizeof(sc->rom));
663 while (addr < 512) {
664 reg = rsu_efuse_read_1(sc, addr);
665 if (reg == 0xff)
666 break;
667 addr++;
668 off = reg >> 4;
669 msk = reg & 0xf;
670 for (i = 0; i < 4; i++) {
671 if (msk & (1 << i))
672 continue;
673 rom[off * 8 + i * 2 + 0] =
674 rsu_efuse_read_1(sc, addr);
675 addr++;
676 rom[off * 8 + i * 2 + 1] =
677 rsu_efuse_read_1(sc, addr);
678 addr++;
679 }
680 }
681 #ifdef RSU_DEBUG
682 if (rsu_debug >= 5) {
683 /* Dump ROM content. */
684 printf("\n");
685 for (i = 0; i < sizeof(sc->rom); i++)
686 printf("%02x:", rom[i]);
687 printf("\n");
688 }
689 #endif
690 return (0);
691 }
692
693 int
rsu_fw_cmd(struct rsu_softc * sc,uint8_t code,void * buf,int len)694 rsu_fw_cmd(struct rsu_softc *sc, uint8_t code, void *buf, int len)
695 {
696 struct rsu_tx_data *data;
697 struct r92s_tx_desc *txd;
698 struct r92s_fw_cmd_hdr *cmd;
699 struct usbd_pipe *pipe;
700 int cmdsz, xferlen;
701
702 data = sc->fwcmd_data;
703
704 /* Round-up command length to a multiple of 8 bytes. */
705 cmdsz = (len + 7) & ~7;
706
707 xferlen = sizeof(*txd) + sizeof(*cmd) + cmdsz;
708 KASSERT(xferlen <= RSU_TXBUFSZ);
709 memset(data->buf, 0, xferlen);
710
711 /* Setup Tx descriptor. */
712 txd = (struct r92s_tx_desc *)data->buf;
713 txd->txdw0 = htole32(
714 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) |
715 SM(R92S_TXDW0_PKTLEN, sizeof(*cmd) + cmdsz) |
716 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG);
717 txd->txdw1 = htole32(SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_H2C));
718
719 /* Setup command header. */
720 cmd = (struct r92s_fw_cmd_hdr *)&txd[1];
721 cmd->len = htole16(cmdsz);
722 cmd->code = code;
723 cmd->seq = sc->cmd_seq;
724 sc->cmd_seq = (sc->cmd_seq + 1) & 0x7f;
725
726 /* Copy command payload. */
727 memcpy(&cmd[1], buf, len);
728
729 DPRINTFN(2, ("Tx cmd code=%d len=%d\n", code, cmdsz));
730 pipe = sc->pipe[sc->qid2idx[RSU_QID_H2C]];
731 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf, xferlen,
732 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS,
733 RSU_CMD_TIMEOUT, NULL);
734 return (usbd_transfer(data->xfer));
735 }
736
737 int
rsu_media_change(struct ifnet * ifp)738 rsu_media_change(struct ifnet *ifp)
739 {
740 int error;
741
742 error = ieee80211_media_change(ifp);
743 if (error != ENETRESET)
744 return (error);
745
746 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
747 (IFF_UP | IFF_RUNNING)) {
748 rsu_stop(ifp);
749 error = rsu_init(ifp);
750 }
751 return (error);
752 }
753
754 void
rsu_calib_to(void * arg)755 rsu_calib_to(void *arg)
756 {
757 struct rsu_softc *sc = arg;
758
759 if (usbd_is_dying(sc->sc_udev))
760 return;
761
762 usbd_ref_incr(sc->sc_udev);
763
764 /* Do it in a process context. */
765 rsu_do_async(sc, rsu_calib_cb, NULL, 0);
766
767 usbd_ref_decr(sc->sc_udev);
768 }
769
770 void
rsu_calib_cb(struct rsu_softc * sc,void * arg)771 rsu_calib_cb(struct rsu_softc *sc, void *arg)
772 {
773 uint32_t reg;
774
775 #ifdef notyet
776 /* Read WPS PBC status. */
777 rsu_write_1(sc, R92S_MAC_PINMUX_CTRL,
778 R92S_GPIOMUX_EN | SM(R92S_GPIOSEL_GPIO, R92S_GPIOSEL_GPIO_JTAG));
779 rsu_write_1(sc, R92S_GPIO_IO_SEL,
780 rsu_read_1(sc, R92S_GPIO_IO_SEL) & ~R92S_GPIO_WPS);
781 reg = rsu_read_1(sc, R92S_GPIO_CTRL);
782 if (reg != 0xff && (reg & R92S_GPIO_WPS))
783 DPRINTF(("WPS PBC is pushed\n"));
784 #endif
785 /* Read current signal level. */
786 if (rsu_fw_iocmd(sc, 0xf4000001) == 0) {
787 reg = rsu_read_4(sc, R92S_IOCMD_DATA);
788 DPRINTFN(8, ("RSSI=%d%%\n", reg >> 4));
789 }
790
791 if (!usbd_is_dying(sc->sc_udev))
792 timeout_add_sec(&sc->calib_to, 2);
793 }
794
795 int
rsu_newstate(struct ieee80211com * ic,enum ieee80211_state nstate,int arg)796 rsu_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
797 {
798 struct rsu_softc *sc = ic->ic_softc;
799 struct rsu_cmd_newstate cmd;
800
801 /* Do it in a process context. */
802 cmd.state = nstate;
803 cmd.arg = arg;
804 rsu_do_async(sc, rsu_newstate_cb, &cmd, sizeof(cmd));
805 return (0);
806 }
807
808 void
rsu_newstate_cb(struct rsu_softc * sc,void * arg)809 rsu_newstate_cb(struct rsu_softc *sc, void *arg)
810 {
811 struct rsu_cmd_newstate *cmd = arg;
812 struct ieee80211com *ic = &sc->sc_ic;
813 struct ifnet *ifp = &ic->ic_if;
814 enum ieee80211_state ostate;
815 int error, s;
816
817 s = splnet();
818 ostate = ic->ic_state;
819
820 if (ostate == IEEE80211_S_RUN) {
821 /* Stop calibration. */
822 timeout_del(&sc->calib_to);
823 /* Disassociate from our current BSS. */
824 (void)rsu_disconnect(sc);
825 }
826 switch (cmd->state) {
827 case IEEE80211_S_INIT:
828 break;
829 case IEEE80211_S_SCAN:
830 error = rsu_site_survey(sc);
831 if (error != 0) {
832 printf("%s: could not send site survey command\n",
833 sc->sc_dev.dv_xname);
834 }
835 if (ifp->if_flags & IFF_DEBUG)
836 printf("%s: %s -> %s\n", ifp->if_xname,
837 ieee80211_state_name[ic->ic_state],
838 ieee80211_state_name[cmd->state]);
839 ic->ic_state = cmd->state;
840 splx(s);
841 return;
842 case IEEE80211_S_AUTH:
843 ic->ic_bss->ni_rsn_supp_state = RSNA_SUPP_INITIALIZE;
844 error = rsu_join_bss(sc, ic->ic_bss);
845 if (error != 0) {
846 printf("%s: could not send join command\n",
847 sc->sc_dev.dv_xname);
848 ieee80211_begin_scan(&ic->ic_if);
849 splx(s);
850 return;
851 }
852 if (ifp->if_flags & IFF_DEBUG)
853 printf("%s: %s -> %s\n", ifp->if_xname,
854 ieee80211_state_name[ic->ic_state],
855 ieee80211_state_name[cmd->state]);
856 ic->ic_state = cmd->state;
857 if (ic->ic_flags & IEEE80211_F_RSNON)
858 ic->ic_bss->ni_rsn_supp_state = RSNA_SUPP_PTKSTART;
859 splx(s);
860 return;
861 case IEEE80211_S_ASSOC:
862 /* No-op for this driver. See rsu_event_join_bss(). */
863 if (ifp->if_flags & IFF_DEBUG)
864 printf("%s: %s -> %s\n", ifp->if_xname,
865 ieee80211_state_name[ic->ic_state],
866 ieee80211_state_name[cmd->state]);
867 ic->ic_state = cmd->state;
868 splx(s);
869 return;
870 case IEEE80211_S_RUN:
871 /* Indicate highest supported rate. */
872 ic->ic_bss->ni_txrate = ic->ic_bss->ni_rates.rs_nrates - 1;
873
874 /* Start periodic calibration. */
875 if (!usbd_is_dying(sc->sc_udev))
876 timeout_add_sec(&sc->calib_to, 2);
877 break;
878 }
879 (void)sc->sc_newstate(ic, cmd->state, cmd->arg);
880 splx(s);
881 }
882
883 int
rsu_set_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)884 rsu_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
885 struct ieee80211_key *k)
886 {
887 struct rsu_softc *sc = ic->ic_softc;
888 struct rsu_cmd_key cmd;
889
890 /* Defer setting of WEP keys until interface is brought up. */
891 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
892 (IFF_UP | IFF_RUNNING))
893 return (0);
894
895 /* Do it in a process context. */
896 cmd.key = *k;
897 cmd.ni = ni;
898 rsu_do_async(sc, rsu_set_key_cb, &cmd, sizeof(cmd));
899 sc->sc_key_tasks++;
900 return EBUSY;
901 }
902
903 void
rsu_set_key_cb(struct rsu_softc * sc,void * arg)904 rsu_set_key_cb(struct rsu_softc *sc, void *arg)
905 {
906 struct rsu_cmd_key *cmd = arg;
907 struct ieee80211com *ic = &sc->sc_ic;
908 struct ieee80211_key *k = &cmd->key;
909 struct r92s_fw_cmd_set_key key;
910
911 sc->sc_key_tasks--;
912
913 memset(&key, 0, sizeof(key));
914 /* Map net80211 cipher to HW crypto algorithm. */
915 switch (k->k_cipher) {
916 case IEEE80211_CIPHER_WEP40:
917 key.algo = R92S_KEY_ALGO_WEP40;
918 break;
919 case IEEE80211_CIPHER_WEP104:
920 key.algo = R92S_KEY_ALGO_WEP104;
921 break;
922 case IEEE80211_CIPHER_TKIP:
923 key.algo = R92S_KEY_ALGO_TKIP;
924 break;
925 case IEEE80211_CIPHER_CCMP:
926 key.algo = R92S_KEY_ALGO_AES;
927 break;
928 default:
929 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH,
930 IEEE80211_REASON_AUTH_LEAVE);
931 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
932 return;
933 }
934 key.id = k->k_id;
935 key.grpkey = (k->k_flags & IEEE80211_KEY_GROUP) != 0;
936 memcpy(key.key, k->k_key, MIN(k->k_len, sizeof(key.key)));
937 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key));
938
939 if (sc->sc_key_tasks == 0) {
940 DPRINTF(("marking port %s valid\n",
941 ether_sprintf(cmd->ni->ni_macaddr)));
942 cmd->ni->ni_port_valid = 1;
943 ieee80211_set_link_state(ic, LINK_STATE_UP);
944 }
945 }
946
947 void
rsu_delete_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)948 rsu_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
949 struct ieee80211_key *k)
950 {
951 struct rsu_softc *sc = ic->ic_softc;
952 struct rsu_cmd_key cmd;
953
954 if (!(ic->ic_if.if_flags & IFF_RUNNING) ||
955 ic->ic_state != IEEE80211_S_RUN)
956 return; /* Nothing to do. */
957
958 /* Do it in a process context. */
959 cmd.key = *k;
960 rsu_do_async(sc, rsu_delete_key_cb, &cmd, sizeof(cmd));
961 }
962
963 void
rsu_delete_key_cb(struct rsu_softc * sc,void * arg)964 rsu_delete_key_cb(struct rsu_softc *sc, void *arg)
965 {
966 struct rsu_cmd_key *cmd = arg;
967 struct ieee80211_key *k = &cmd->key;
968 struct r92s_fw_cmd_set_key key;
969
970 memset(&key, 0, sizeof(key));
971 key.id = k->k_id;
972 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key));
973 }
974
975 int
rsu_site_survey(struct rsu_softc * sc)976 rsu_site_survey(struct rsu_softc *sc)
977 {
978 struct ieee80211com *ic = &sc->sc_ic;
979 struct r92s_fw_cmd_sitesurvey cmd;
980
981 memset(&cmd, 0, sizeof(cmd));
982 if ((ic->ic_flags & IEEE80211_F_ASCAN) || sc->scan_pass == 1)
983 cmd.active = htole32(1);
984 cmd.limit = htole32(48);
985 if (sc->scan_pass == 1) {
986 /* Do a directed scan for second pass. */
987 cmd.ssidlen = htole32(ic->ic_des_esslen);
988 memcpy(cmd.ssid, ic->ic_des_essid, ic->ic_des_esslen);
989 }
990 DPRINTF(("sending site survey command, pass=%d\n", sc->scan_pass));
991 return (rsu_fw_cmd(sc, R92S_CMD_SITE_SURVEY, &cmd, sizeof(cmd)));
992 }
993
994 int
rsu_join_bss(struct rsu_softc * sc,struct ieee80211_node * ni)995 rsu_join_bss(struct rsu_softc *sc, struct ieee80211_node *ni)
996 {
997 struct ieee80211com *ic = &sc->sc_ic;
998 struct ndis_wlan_bssid_ex *bss;
999 struct ndis_802_11_fixed_ies *fixed;
1000 struct r92s_fw_cmd_auth auth;
1001 uint8_t buf[sizeof(*bss) + 128], *frm;
1002 uint8_t opmode;
1003 int error;
1004
1005 /* Let the FW decide the opmode based on the capinfo field. */
1006 opmode = NDIS802_11AUTOUNKNOWN;
1007 DPRINTF(("setting operating mode to %d\n", opmode));
1008 error = rsu_fw_cmd(sc, R92S_CMD_SET_OPMODE, &opmode, sizeof(opmode));
1009 if (error != 0)
1010 return (error);
1011
1012 memset(&auth, 0, sizeof(auth));
1013 if (ic->ic_flags & IEEE80211_F_RSNON) {
1014 auth.mode = R92S_AUTHMODE_WPA;
1015 auth.dot1x = ieee80211_is_8021x_akm(ni->ni_rsnakms);
1016 } else
1017 auth.mode = R92S_AUTHMODE_OPEN;
1018 DPRINTF(("setting auth mode to %d\n", auth.mode));
1019 error = rsu_fw_cmd(sc, R92S_CMD_SET_AUTH, &auth, sizeof(auth));
1020 if (error != 0)
1021 return (error);
1022
1023 memset(buf, 0, sizeof(buf));
1024 bss = (struct ndis_wlan_bssid_ex *)buf;
1025 IEEE80211_ADDR_COPY(bss->macaddr, ni->ni_bssid);
1026 bss->ssid.ssidlen = htole32(ni->ni_esslen);
1027 memcpy(bss->ssid.ssid, ni->ni_essid, ni->ni_esslen);
1028 if (ic->ic_flags & (IEEE80211_F_WEPON | IEEE80211_F_RSNON))
1029 bss->privacy = htole32(1);
1030 bss->rssi = htole32(ni->ni_rssi);
1031 if (ic->ic_curmode == IEEE80211_MODE_11B)
1032 bss->networktype = htole32(NDIS802_11DS);
1033 else
1034 bss->networktype = htole32(NDIS802_11OFDM24);
1035 bss->config.len = htole32(sizeof(bss->config));
1036 bss->config.bintval = htole32(ni->ni_intval);
1037 bss->config.dsconfig = htole32(ieee80211_chan2ieee(ic, ni->ni_chan));
1038 bss->inframode = htole32(NDIS802_11INFRASTRUCTURE);
1039 memcpy(bss->supprates, ni->ni_rates.rs_rates,
1040 ni->ni_rates.rs_nrates);
1041 /* Write the fixed fields of the beacon frame. */
1042 fixed = (struct ndis_802_11_fixed_ies *)&bss[1];
1043 memcpy(&fixed->tstamp, ni->ni_tstamp, 8);
1044 fixed->bintval = htole16(ni->ni_intval);
1045 fixed->capabilities = htole16(ni->ni_capinfo);
1046 /* Write IEs to be included in the association request. */
1047 frm = (uint8_t *)&fixed[1];
1048 if ((ic->ic_flags & IEEE80211_F_RSNON) &&
1049 (ni->ni_rsnprotos & IEEE80211_PROTO_RSN))
1050 frm = ieee80211_add_rsn(frm, ic, ni);
1051 if (ni->ni_flags & IEEE80211_NODE_QOS)
1052 frm = ieee80211_add_qos_capability(frm, ic);
1053 if (ni->ni_flags & IEEE80211_NODE_HT)
1054 frm = ieee80211_add_htcaps(frm, ic);
1055 if ((ic->ic_flags & IEEE80211_F_RSNON) &&
1056 (ni->ni_rsnprotos & IEEE80211_PROTO_WPA))
1057 frm = ieee80211_add_wpa(frm, ic, ni);
1058 bss->ieslen = htole32(frm - (uint8_t *)fixed);
1059 bss->len = htole32(((frm - buf) + 3) & ~3);
1060 DPRINTF(("sending join bss command to %s chan %d\n",
1061 ether_sprintf(bss->macaddr), letoh32(bss->config.dsconfig)));
1062 return (rsu_fw_cmd(sc, R92S_CMD_JOIN_BSS, buf, sizeof(buf)));
1063 }
1064
1065 int
rsu_disconnect(struct rsu_softc * sc)1066 rsu_disconnect(struct rsu_softc *sc)
1067 {
1068 uint32_t zero = 0; /* :-) */
1069
1070 /* Disassociate from our current BSS. */
1071 DPRINTF(("sending disconnect command\n"));
1072 return (rsu_fw_cmd(sc, R92S_CMD_DISCONNECT, &zero, sizeof(zero)));
1073 }
1074
1075 void
rsu_event_survey(struct rsu_softc * sc,uint8_t * buf,int len)1076 rsu_event_survey(struct rsu_softc *sc, uint8_t *buf, int len)
1077 {
1078 struct ieee80211com *ic = &sc->sc_ic;
1079 struct ifnet *ifp = &ic->ic_if;
1080 struct ieee80211_rxinfo rxi;
1081 struct ieee80211_node *ni;
1082 struct ieee80211_frame *wh;
1083 struct ndis_wlan_bssid_ex *bss;
1084 struct mbuf *m;
1085 uint32_t pktlen, ieslen;
1086
1087 if (__predict_false(len < sizeof(*bss)))
1088 return;
1089 bss = (struct ndis_wlan_bssid_ex *)buf;
1090 ieslen = letoh32(bss->ieslen);
1091 if (ieslen > len - sizeof(*bss))
1092 return;
1093
1094 DPRINTFN(2, ("found BSS %s: len=%d chan=%d inframode=%d "
1095 "networktype=%d privacy=%d\n",
1096 ether_sprintf(bss->macaddr), letoh32(bss->len),
1097 letoh32(bss->config.dsconfig), letoh32(bss->inframode),
1098 letoh32(bss->networktype), letoh32(bss->privacy)));
1099
1100 /* Build a fake beacon frame to let net80211 do all the parsing. */
1101 pktlen = sizeof(*wh) + ieslen;
1102 if (__predict_false(pktlen > MCLBYTES))
1103 return;
1104 MGETHDR(m, M_DONTWAIT, MT_DATA);
1105 if (__predict_false(m == NULL))
1106 return;
1107 if (pktlen > MHLEN) {
1108 MCLGET(m, M_DONTWAIT);
1109 if (!(m->m_flags & M_EXT)) {
1110 m_free(m);
1111 return;
1112 }
1113 }
1114 wh = mtod(m, struct ieee80211_frame *);
1115 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
1116 IEEE80211_FC0_SUBTYPE_BEACON;
1117 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
1118 *(uint16_t *)wh->i_dur = 0;
1119 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr);
1120 IEEE80211_ADDR_COPY(wh->i_addr2, bss->macaddr);
1121 IEEE80211_ADDR_COPY(wh->i_addr3, bss->macaddr);
1122 *(uint16_t *)wh->i_seq = 0;
1123 memcpy(&wh[1], (uint8_t *)&bss[1], ieslen);
1124
1125 /* Finalize mbuf. */
1126 m->m_pkthdr.len = m->m_len = pktlen;
1127
1128 ni = ieee80211_find_rxnode(ic, wh);
1129 memset(&rxi, 0, sizeof(rxi));
1130 rxi.rxi_rssi = letoh32(bss->rssi);
1131 ieee80211_input(ifp, m, ni, &rxi);
1132 /* Node is no longer needed. */
1133 ieee80211_release_node(ic, ni);
1134 }
1135
1136 void
rsu_event_join_bss(struct rsu_softc * sc,uint8_t * buf,int len)1137 rsu_event_join_bss(struct rsu_softc *sc, uint8_t *buf, int len)
1138 {
1139 struct ieee80211com *ic = &sc->sc_ic;
1140 struct ieee80211_node *ni = ic->ic_bss;
1141 struct r92s_event_join_bss *rsp;
1142 int res;
1143
1144 if (__predict_false(len < sizeof(*rsp)))
1145 return;
1146 rsp = (struct r92s_event_join_bss *)buf;
1147 res = (int)letoh32(rsp->join_res);
1148
1149 DPRINTF(("Rx join BSS event len=%d res=%d\n", len, res));
1150 if (res <= 0) {
1151 ic->ic_stats.is_rx_auth_fail++;
1152 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1153 return;
1154 }
1155 DPRINTF(("associated with %s associd=%d\n",
1156 ether_sprintf(rsp->bss.macaddr), letoh32(rsp->associd)));
1157
1158 ni->ni_associd = letoh32(rsp->associd) | 0xc000;
1159 if (ic->ic_flags & IEEE80211_F_WEPON)
1160 ni->ni_flags |= IEEE80211_NODE_TXRXPROT;
1161
1162 /* Force an ASSOC->RUN transition. AUTH->RUN is invalid. */
1163 ic->ic_state = IEEE80211_S_ASSOC;
1164 ieee80211_new_state(ic, IEEE80211_S_RUN,
1165 IEEE80211_FC0_SUBTYPE_ASSOC_RESP);
1166 }
1167
1168 void
rsu_rx_event(struct rsu_softc * sc,uint8_t code,uint8_t * buf,int len)1169 rsu_rx_event(struct rsu_softc *sc, uint8_t code, uint8_t *buf, int len)
1170 {
1171 struct ieee80211com *ic = &sc->sc_ic;
1172 struct ifnet *ifp = &ic->ic_if;
1173
1174 DPRINTFN(4, ("Rx event code=%d len=%d\n", code, len));
1175 switch (code) {
1176 case R92S_EVT_SURVEY:
1177 if (ic->ic_state == IEEE80211_S_SCAN)
1178 rsu_event_survey(sc, buf, len);
1179 break;
1180 case R92S_EVT_SURVEY_DONE:
1181 DPRINTF(("site survey pass %d done, found %d BSS\n",
1182 sc->scan_pass, letoh32(*(uint32_t *)buf)));
1183 if (ic->ic_state != IEEE80211_S_SCAN)
1184 break; /* Ignore if not scanning. */
1185 if (sc->scan_pass == 0 && ic->ic_des_esslen != 0) {
1186 /* Schedule a directed scan for hidden APs. */
1187 sc->scan_pass = 1;
1188 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1189 break;
1190 }
1191 ieee80211_end_scan(ifp);
1192 sc->scan_pass = 0;
1193 break;
1194 case R92S_EVT_JOIN_BSS:
1195 if (ic->ic_state == IEEE80211_S_AUTH)
1196 rsu_event_join_bss(sc, buf, len);
1197 break;
1198 case R92S_EVT_DEL_STA:
1199 DPRINTF(("disassociated from %s\n", ether_sprintf(buf)));
1200 if (ic->ic_state == IEEE80211_S_RUN &&
1201 IEEE80211_ADDR_EQ(ic->ic_bss->ni_bssid, buf))
1202 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1203 break;
1204 case R92S_EVT_WPS_PBC:
1205 DPRINTF(("WPS PBC pushed.\n"));
1206 break;
1207 case R92S_EVT_FWDBG:
1208 if (ifp->if_flags & IFF_DEBUG) {
1209 buf[60] = '\0';
1210 printf("FWDBG: %s\n", (char *)buf);
1211 }
1212 break;
1213 }
1214 }
1215
1216 void
rsu_rx_multi_event(struct rsu_softc * sc,uint8_t * buf,int len)1217 rsu_rx_multi_event(struct rsu_softc *sc, uint8_t *buf, int len)
1218 {
1219 struct r92s_fw_cmd_hdr *cmd;
1220 int cmdsz;
1221
1222 DPRINTFN(6, ("Rx events len=%d\n", len));
1223
1224 /* Skip Rx status. */
1225 buf += sizeof(struct r92s_rx_stat);
1226 len -= sizeof(struct r92s_rx_stat);
1227
1228 /* Process all events. */
1229 for (;;) {
1230 /* Check that command header fits. */
1231 if (__predict_false(len < sizeof(*cmd)))
1232 break;
1233 cmd = (struct r92s_fw_cmd_hdr *)buf;
1234 /* Check that command payload fits. */
1235 cmdsz = letoh16(cmd->len);
1236 if (__predict_false(len < sizeof(*cmd) + cmdsz))
1237 break;
1238 if (cmdsz > len)
1239 break;
1240
1241 /* Process firmware event. */
1242 rsu_rx_event(sc, cmd->code, (uint8_t *)&cmd[1], cmdsz);
1243
1244 if (!(cmd->seq & R92S_FW_CMD_MORE))
1245 break;
1246 buf += sizeof(*cmd) + cmdsz;
1247 len -= sizeof(*cmd) + cmdsz;
1248 }
1249 }
1250
1251 int8_t
rsu_get_rssi(struct rsu_softc * sc,int rate,void * physt)1252 rsu_get_rssi(struct rsu_softc *sc, int rate, void *physt)
1253 {
1254 static const int8_t cckoff[] = { 14, -2, -20, -40 };
1255 struct r92s_rx_phystat *phy;
1256 struct r92s_rx_cck *cck;
1257 uint8_t rpt;
1258 int8_t rssi;
1259
1260 if (rate <= 3) {
1261 cck = (struct r92s_rx_cck *)physt;
1262 rpt = (cck->agc_rpt >> 6) & 0x3;
1263 rssi = cck->agc_rpt & 0x3e;
1264 rssi = cckoff[rpt] - rssi;
1265 } else { /* OFDM/HT. */
1266 phy = (struct r92s_rx_phystat *)physt;
1267 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 106;
1268 }
1269 return (rssi);
1270 }
1271
1272 void
rsu_rx_frame(struct rsu_softc * sc,uint8_t * buf,int pktlen,struct mbuf_list * ml)1273 rsu_rx_frame(struct rsu_softc *sc, uint8_t *buf, int pktlen,
1274 struct mbuf_list *ml)
1275 {
1276 struct ieee80211com *ic = &sc->sc_ic;
1277 struct ifnet *ifp = &ic->ic_if;
1278 struct ieee80211_rxinfo rxi;
1279 struct ieee80211_frame *wh;
1280 struct ieee80211_node *ni;
1281 struct r92s_rx_stat *stat;
1282 uint32_t rxdw0, rxdw3;
1283 struct mbuf *m;
1284 uint8_t rate;
1285 int8_t rssi = 0;
1286 int s, infosz;
1287
1288 stat = (struct r92s_rx_stat *)buf;
1289 rxdw0 = letoh32(stat->rxdw0);
1290 rxdw3 = letoh32(stat->rxdw3);
1291
1292 if (__predict_false(rxdw0 & R92S_RXDW0_CRCERR)) {
1293 ifp->if_ierrors++;
1294 return;
1295 }
1296 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) {
1297 ifp->if_ierrors++;
1298 return;
1299 }
1300
1301 rate = MS(rxdw3, R92S_RXDW3_RATE);
1302 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8;
1303
1304 /* Get RSSI from PHY status descriptor if present. */
1305 if (infosz != 0)
1306 rssi = rsu_get_rssi(sc, rate, &stat[1]);
1307
1308 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n",
1309 pktlen, rate, infosz, rssi));
1310
1311 MGETHDR(m, M_DONTWAIT, MT_DATA);
1312 if (__predict_false(m == NULL)) {
1313 ifp->if_ierrors++;
1314 return;
1315 }
1316 if (pktlen > MHLEN) {
1317 MCLGET(m, M_DONTWAIT);
1318 if (__predict_false(!(m->m_flags & M_EXT))) {
1319 ifp->if_ierrors++;
1320 m_freem(m);
1321 return;
1322 }
1323 }
1324 /* Finalize mbuf. */
1325 /* Hardware does Rx TCP checksum offload. */
1326 if (rxdw3 & R92S_RXDW3_TCPCHKVALID) {
1327 if (__predict_true(rxdw3 & R92S_RXDW3_TCPCHKRPT))
1328 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK;
1329 else
1330 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_BAD;
1331 }
1332 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz);
1333 memcpy(mtod(m, uint8_t *), wh, pktlen);
1334 m->m_pkthdr.len = m->m_len = pktlen;
1335
1336 s = splnet();
1337 #if NBPFILTER > 0
1338 if (__predict_false(sc->sc_drvbpf != NULL)) {
1339 struct rsu_rx_radiotap_header *tap = &sc->sc_rxtap;
1340 struct mbuf mb;
1341
1342 tap->wr_flags = 0;
1343 /* Map HW rate index to 802.11 rate. */
1344 tap->wr_flags = 2;
1345 if (!(rxdw3 & R92S_RXDW3_HTC)) {
1346 switch (rate) {
1347 /* CCK. */
1348 case 0: tap->wr_rate = 2; break;
1349 case 1: tap->wr_rate = 4; break;
1350 case 2: tap->wr_rate = 11; break;
1351 case 3: tap->wr_rate = 22; break;
1352 /* OFDM. */
1353 case 4: tap->wr_rate = 12; break;
1354 case 5: tap->wr_rate = 18; break;
1355 case 6: tap->wr_rate = 24; break;
1356 case 7: tap->wr_rate = 36; break;
1357 case 8: tap->wr_rate = 48; break;
1358 case 9: tap->wr_rate = 72; break;
1359 case 10: tap->wr_rate = 96; break;
1360 case 11: tap->wr_rate = 108; break;
1361 }
1362 } else if (rate >= 12) { /* MCS0~15. */
1363 /* Bit 7 set means HT MCS instead of rate. */
1364 tap->wr_rate = 0x80 | (rate - 12);
1365 }
1366 tap->wr_dbm_antsignal = rssi;
1367 tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
1368 tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
1369
1370 mb.m_data = (caddr_t)tap;
1371 mb.m_len = sc->sc_rxtap_len;
1372 mb.m_next = m;
1373 mb.m_nextpkt = NULL;
1374 mb.m_type = 0;
1375 mb.m_flags = 0;
1376 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN);
1377 }
1378 #endif
1379
1380 ni = ieee80211_find_rxnode(ic, wh);
1381 memset(&rxi, 0, sizeof(rxi));
1382 rxi.rxi_rssi = rssi;
1383 ieee80211_inputm(ifp, m, ni, &rxi, ml);
1384 /* Node is no longer needed. */
1385 ieee80211_release_node(ic, ni);
1386 splx(s);
1387 }
1388
1389 void
rsu_rx_multi_frame(struct rsu_softc * sc,uint8_t * buf,int len)1390 rsu_rx_multi_frame(struct rsu_softc *sc, uint8_t *buf, int len)
1391 {
1392 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
1393 struct r92s_rx_stat *stat;
1394 uint32_t rxdw0;
1395 int totlen, pktlen, infosz, npkts;
1396
1397 /* Get the number of encapsulated frames. */
1398 stat = (struct r92s_rx_stat *)buf;
1399 npkts = MS(letoh32(stat->rxdw2), R92S_RXDW2_PKTCNT);
1400 DPRINTFN(6, ("Rx %d frames in one chunk\n", npkts));
1401
1402 /* Process all of them. */
1403 while (npkts-- > 0) {
1404 if (__predict_false(len < sizeof(*stat)))
1405 break;
1406 stat = (struct r92s_rx_stat *)buf;
1407 rxdw0 = letoh32(stat->rxdw0);
1408
1409 pktlen = MS(rxdw0, R92S_RXDW0_PKTLEN);
1410 if (__predict_false(pktlen == 0))
1411 break;
1412
1413 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8;
1414
1415 /* Make sure everything fits in xfer. */
1416 totlen = sizeof(*stat) + infosz + pktlen;
1417 if (__predict_false(totlen > len))
1418 break;
1419
1420 /* Process 802.11 frame. */
1421 rsu_rx_frame(sc, buf, pktlen, &ml);
1422
1423 /* Next chunk is 128-byte aligned. */
1424 totlen = (totlen + 127) & ~127;
1425 buf += totlen;
1426 len -= totlen;
1427 }
1428 if_input(&sc->sc_ic.ic_if, &ml);
1429 }
1430
1431 void
rsu_rxeof(struct usbd_xfer * xfer,void * priv,usbd_status status)1432 rsu_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1433 {
1434 struct rsu_rx_data *data = priv;
1435 struct rsu_softc *sc = data->sc;
1436 struct r92s_rx_stat *stat;
1437 struct ifnet *ifp = &sc->sc_ic.ic_if;
1438 int len;
1439
1440 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1441 DPRINTF(("RX status=%d\n", status));
1442 if (status == USBD_STALLED)
1443 usbd_clear_endpoint_stall_async(data->pipe);
1444 if (status != USBD_CANCELLED)
1445 goto resubmit;
1446 return;
1447 }
1448 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL);
1449
1450 if (__predict_false(len < sizeof(*stat))) {
1451 DPRINTF(("xfer too short %d\n", len));
1452 ifp->if_ierrors++;
1453 goto resubmit;
1454 }
1455 if (len > RSU_RXBUFSZ) {
1456 DPRINTF(("xfer too large %d\n", len));
1457 ifp->if_ierrors++;
1458 goto resubmit;
1459 }
1460
1461 /* Determine if it is a firmware C2H event or an 802.11 frame. */
1462 stat = (struct r92s_rx_stat *)data->buf;
1463 if ((letoh32(stat->rxdw1) & 0x1ff) == 0x1ff)
1464 rsu_rx_multi_event(sc, data->buf, len);
1465 else
1466 rsu_rx_multi_frame(sc, data->buf, len);
1467
1468 resubmit:
1469 /* Setup a new transfer. */
1470 usbd_setup_xfer(xfer, data->pipe, data, data->buf, RSU_RXBUFSZ,
1471 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, rsu_rxeof);
1472 (void)usbd_transfer(xfer);
1473 }
1474
1475 void
rsu_txeof(struct usbd_xfer * xfer,void * priv,usbd_status status)1476 rsu_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1477 {
1478 struct rsu_tx_data *data = priv;
1479 struct rsu_softc *sc = data->sc;
1480 struct ifnet *ifp = &sc->sc_ic.ic_if;
1481 int s;
1482
1483 s = splnet();
1484 /* Put this Tx buffer back to our free list. */
1485 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next);
1486
1487 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1488 DPRINTF(("TX status=%d\n", status));
1489 if (status == USBD_STALLED)
1490 usbd_clear_endpoint_stall_async(data->pipe);
1491 ifp->if_oerrors++;
1492 splx(s);
1493 return;
1494 }
1495 sc->sc_tx_timer = 0;
1496
1497 /* We just released a Tx buffer, notify Tx. */
1498 if (ifq_is_oactive(&ifp->if_snd)) {
1499 ifq_clr_oactive(&ifp->if_snd);
1500 rsu_start(ifp);
1501 }
1502 splx(s);
1503 }
1504
1505 int
rsu_tx(struct rsu_softc * sc,struct mbuf * m,struct ieee80211_node * ni)1506 rsu_tx(struct rsu_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1507 {
1508 struct ieee80211com *ic = &sc->sc_ic;
1509 struct ieee80211_frame *wh;
1510 struct ieee80211_key *k = NULL;
1511 struct rsu_tx_data *data;
1512 struct r92s_tx_desc *txd;
1513 struct usbd_pipe *pipe;
1514 uint16_t qos;
1515 uint8_t type, qid, tid = 0;
1516 int hasqos, xferlen, error;
1517
1518 wh = mtod(m, struct ieee80211_frame *);
1519 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1520
1521 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1522 k = ieee80211_get_txkey(ic, wh, ni);
1523 if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
1524 return (ENOBUFS);
1525 wh = mtod(m, struct ieee80211_frame *);
1526 }
1527 if ((hasqos = ieee80211_has_qos(wh))) {
1528 qos = ieee80211_get_qos(wh);
1529 tid = qos & IEEE80211_QOS_TID;
1530 qid = rsu_ac2qid[ieee80211_up_to_ac(ic, tid)];
1531 } else
1532 qid = RSU_QID_BE;
1533
1534 /* Get the USB pipe to use for this queue id. */
1535 pipe = sc->pipe[sc->qid2idx[qid]];
1536
1537 /* Grab a Tx buffer from our free list. */
1538 data = TAILQ_FIRST(&sc->tx_free_list);
1539 TAILQ_REMOVE(&sc->tx_free_list, data, next);
1540
1541 /* Fill Tx descriptor. */
1542 txd = (struct r92s_tx_desc *)data->buf;
1543 memset(txd, 0, sizeof(*txd));
1544
1545 txd->txdw0 |= htole32(
1546 SM(R92S_TXDW0_PKTLEN, m->m_pkthdr.len) |
1547 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) |
1548 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG);
1549
1550 txd->txdw1 |= htole32(
1551 SM(R92S_TXDW1_MACID, R92S_MACID_BSS) |
1552 SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_BE));
1553 if (!hasqos)
1554 txd->txdw1 |= htole32(R92S_TXDW1_NONQOS);
1555 #ifdef notyet
1556 if (k != NULL) {
1557 switch (k->k_cipher) {
1558 case IEEE80211_CIPHER_WEP40:
1559 case IEEE80211_CIPHER_WEP104:
1560 cipher = R92S_TXDW1_CIPHER_WEP;
1561 break;
1562 case IEEE80211_CIPHER_TKIP:
1563 cipher = R92S_TXDW1_CIPHER_TKIP;
1564 break;
1565 case IEEE80211_CIPHER_CCMP:
1566 cipher = R92S_TXDW1_CIPHER_AES;
1567 break;
1568 default:
1569 cipher = R92S_TXDW1_CIPHER_NONE;
1570 }
1571 txd->txdw1 |= htole32(
1572 SM(R92S_TXDW1_CIPHER, cipher) |
1573 SM(R92S_TXDW1_KEYIDX, k->k_id));
1574 }
1575 #endif
1576 txd->txdw2 |= htole32(R92S_TXDW2_BK);
1577 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1578 txd->txdw2 |= htole32(R92S_TXDW2_BMCAST);
1579 /*
1580 * Firmware will use and increment the sequence number for the
1581 * specified TID.
1582 */
1583 txd->txdw3 |= htole32(SM(R92S_TXDW3_SEQ, tid));
1584
1585 #if NBPFILTER > 0
1586 if (__predict_false(sc->sc_drvbpf != NULL)) {
1587 struct rsu_tx_radiotap_header *tap = &sc->sc_txtap;
1588 struct mbuf mb;
1589
1590 tap->wt_flags = 0;
1591 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
1592 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
1593
1594 mb.m_data = (caddr_t)tap;
1595 mb.m_len = sc->sc_txtap_len;
1596 mb.m_next = m;
1597 mb.m_nextpkt = NULL;
1598 mb.m_type = 0;
1599 mb.m_flags = 0;
1600 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT);
1601 }
1602 #endif
1603
1604 xferlen = sizeof(*txd) + m->m_pkthdr.len;
1605 m_copydata(m, 0, m->m_pkthdr.len, &txd[1]);
1606 m_freem(m);
1607
1608 data->pipe = pipe;
1609 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen,
1610 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RSU_TX_TIMEOUT,
1611 rsu_txeof);
1612 error = usbd_transfer(data->xfer);
1613 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) {
1614 /* Put this Tx buffer back to our free list. */
1615 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next);
1616 return (error);
1617 }
1618 ieee80211_release_node(ic, ni);
1619 return (0);
1620 }
1621
1622 int
rsu_send_mgmt(struct ieee80211com * ic,struct ieee80211_node * ni,int type,int arg1,int arg2)1623 rsu_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni, int type,
1624 int arg1, int arg2)
1625 {
1626 return (EOPNOTSUPP);
1627 }
1628
1629 void
rsu_start(struct ifnet * ifp)1630 rsu_start(struct ifnet *ifp)
1631 {
1632 struct rsu_softc *sc = ifp->if_softc;
1633 struct ieee80211com *ic = &sc->sc_ic;
1634 struct ieee80211_node *ni;
1635 struct mbuf *m;
1636
1637 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
1638 return;
1639
1640 for (;;) {
1641 if (TAILQ_EMPTY(&sc->tx_free_list)) {
1642 ifq_set_oactive(&ifp->if_snd);
1643 break;
1644 }
1645 if (ic->ic_state != IEEE80211_S_RUN)
1646 break;
1647
1648 /* Encapsulate and send data frames. */
1649 m = ifq_dequeue(&ifp->if_snd);
1650 if (m == NULL)
1651 break;
1652 #if NBPFILTER > 0
1653 if (ifp->if_bpf != NULL)
1654 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
1655 #endif
1656 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL)
1657 continue;
1658
1659 #if NBPFILTER > 0
1660 if (ic->ic_rawbpf != NULL)
1661 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT);
1662 #endif
1663 if (rsu_tx(sc, m, ni) != 0) {
1664 ieee80211_release_node(ic, ni);
1665 ifp->if_oerrors++;
1666 continue;
1667 }
1668
1669 sc->sc_tx_timer = 5;
1670 ifp->if_timer = 1;
1671 }
1672 }
1673
1674 void
rsu_watchdog(struct ifnet * ifp)1675 rsu_watchdog(struct ifnet *ifp)
1676 {
1677 struct rsu_softc *sc = ifp->if_softc;
1678
1679 ifp->if_timer = 0;
1680
1681 if (sc->sc_tx_timer > 0) {
1682 if (--sc->sc_tx_timer == 0) {
1683 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
1684 /* rsu_init(ifp); XXX needs a process context! */
1685 ifp->if_oerrors++;
1686 return;
1687 }
1688 ifp->if_timer = 1;
1689 }
1690 ieee80211_watchdog(ifp);
1691 }
1692
1693 int
rsu_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1694 rsu_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1695 {
1696 struct rsu_softc *sc = ifp->if_softc;
1697 int s, error = 0;
1698
1699 if (usbd_is_dying(sc->sc_udev))
1700 return ENXIO;
1701
1702 usbd_ref_incr(sc->sc_udev);
1703
1704 s = splnet();
1705
1706 switch (cmd) {
1707 case SIOCSIFADDR:
1708 ifp->if_flags |= IFF_UP;
1709 /* FALLTHROUGH */
1710 case SIOCSIFFLAGS:
1711 if (ifp->if_flags & IFF_UP) {
1712 if (!(ifp->if_flags & IFF_RUNNING))
1713 rsu_init(ifp);
1714 } else {
1715 if (ifp->if_flags & IFF_RUNNING)
1716 rsu_stop(ifp);
1717 }
1718 break;
1719 default:
1720 error = ieee80211_ioctl(ifp, cmd, data);
1721 }
1722
1723 if (error == ENETRESET) {
1724 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1725 (IFF_UP | IFF_RUNNING)) {
1726 rsu_stop(ifp);
1727 rsu_init(ifp);
1728 }
1729 error = 0;
1730 }
1731 splx(s);
1732
1733 usbd_ref_decr(sc->sc_udev);
1734
1735 return (error);
1736 }
1737
1738 /*
1739 * Power on sequence for A-cut adapters.
1740 */
1741 void
rsu_power_on_acut(struct rsu_softc * sc)1742 rsu_power_on_acut(struct rsu_softc *sc)
1743 {
1744 uint32_t reg;
1745
1746 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53);
1747 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57);
1748
1749 /* Enable AFE macro block's bandgap and Mbias. */
1750 rsu_write_1(sc, R92S_AFE_MISC,
1751 rsu_read_1(sc, R92S_AFE_MISC) |
1752 R92S_AFE_MISC_BGEN | R92S_AFE_MISC_MBEN);
1753 /* Enable LDOA15 block. */
1754 rsu_write_1(sc, R92S_LDOA15_CTRL,
1755 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN);
1756
1757 rsu_write_1(sc, R92S_SPS1_CTRL,
1758 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_LDEN);
1759 usbd_delay_ms(sc->sc_udev, 2);
1760 /* Enable switch regulator block. */
1761 rsu_write_1(sc, R92S_SPS1_CTRL,
1762 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_SWEN);
1763
1764 rsu_write_4(sc, R92S_SPS1_CTRL, 0x00a7b267);
1765
1766 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1,
1767 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08);
1768
1769 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1770 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20);
1771
1772 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1,
1773 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x90);
1774
1775 /* Enable AFE clock. */
1776 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1,
1777 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04);
1778 /* Enable AFE PLL macro block. */
1779 rsu_write_1(sc, R92S_AFE_PLL_CTRL,
1780 rsu_read_1(sc, R92S_AFE_PLL_CTRL) | 0x11);
1781 /* Attach AFE PLL to MACTOP/BB. */
1782 rsu_write_1(sc, R92S_SYS_ISO_CTRL,
1783 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11);
1784
1785 /* Switch to 40MHz clock instead of 80MHz. */
1786 rsu_write_2(sc, R92S_SYS_CLKR,
1787 rsu_read_2(sc, R92S_SYS_CLKR) & ~R92S_SYS_CLKSEL);
1788
1789 /* Enable MAC clock. */
1790 rsu_write_2(sc, R92S_SYS_CLKR,
1791 rsu_read_2(sc, R92S_SYS_CLKR) |
1792 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN);
1793
1794 rsu_write_1(sc, R92S_PMC_FSM, 0x02);
1795
1796 /* Enable digital core and IOREG R/W. */
1797 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1798 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08);
1799
1800 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1801 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80);
1802
1803 /* Switch the control path to firmware. */
1804 reg = rsu_read_2(sc, R92S_SYS_CLKR);
1805 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL;
1806 rsu_write_2(sc, R92S_SYS_CLKR, reg);
1807
1808 rsu_write_2(sc, R92S_CR, 0x37fc);
1809
1810 /* Fix USB RX FIFO issue. */
1811 rsu_write_1(sc, 0xfe5c,
1812 rsu_read_1(sc, 0xfe5c) | 0x80);
1813 rsu_write_1(sc, 0x00ab,
1814 rsu_read_1(sc, 0x00ab) | 0xc0);
1815
1816 rsu_write_1(sc, R92S_SYS_CLKR,
1817 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL);
1818 }
1819
1820 /*
1821 * Power on sequence for B-cut and C-cut adapters.
1822 */
1823 void
rsu_power_on_bcut(struct rsu_softc * sc)1824 rsu_power_on_bcut(struct rsu_softc *sc)
1825 {
1826 uint32_t reg;
1827 int ntries;
1828
1829 /* Prevent eFuse leakage. */
1830 rsu_write_1(sc, 0x37, 0xb0);
1831 usbd_delay_ms(sc->sc_udev, 10);
1832 rsu_write_1(sc, 0x37, 0x30);
1833
1834 /* Switch the control path to hardware. */
1835 reg = rsu_read_2(sc, R92S_SYS_CLKR);
1836 if (reg & R92S_FWHW_SEL) {
1837 rsu_write_2(sc, R92S_SYS_CLKR,
1838 reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL));
1839 }
1840 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1841 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) & ~0x8c);
1842 DELAY(1000);
1843
1844 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53);
1845 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57);
1846
1847 reg = rsu_read_1(sc, R92S_AFE_MISC);
1848 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN);
1849 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN |
1850 R92S_AFE_MISC_MBEN | R92S_AFE_MISC_I32_EN);
1851
1852 /* Enable PLL. */
1853 rsu_write_1(sc, R92S_LDOA15_CTRL,
1854 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN);
1855
1856 rsu_write_1(sc, R92S_LDOV12D_CTRL,
1857 rsu_read_1(sc, R92S_LDOV12D_CTRL) | R92S_LDV12_EN);
1858
1859 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1,
1860 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08);
1861
1862 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1863 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20);
1864
1865 /* Support 64KB IMEM. */
1866 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1,
1867 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x97);
1868
1869 /* Enable AFE clock. */
1870 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1,
1871 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04);
1872 /* Enable AFE PLL macro block. */
1873 reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL);
1874 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11);
1875 DELAY(500);
1876 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51);
1877 DELAY(500);
1878 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11);
1879 DELAY(500);
1880
1881 /* Attach AFE PLL to MACTOP/BB. */
1882 rsu_write_1(sc, R92S_SYS_ISO_CTRL,
1883 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11);
1884
1885 /* Switch to 40MHz clock. */
1886 rsu_write_1(sc, R92S_SYS_CLKR, 0x00);
1887 /* Disable CPU clock and 80MHz SSC. */
1888 rsu_write_1(sc, R92S_SYS_CLKR,
1889 rsu_read_1(sc, R92S_SYS_CLKR) | 0xa0);
1890 /* Enable MAC clock. */
1891 rsu_write_2(sc, R92S_SYS_CLKR,
1892 rsu_read_2(sc, R92S_SYS_CLKR) |
1893 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN);
1894
1895 rsu_write_1(sc, R92S_PMC_FSM, 0x02);
1896
1897 /* Enable digital core and IOREG R/W. */
1898 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1899 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08);
1900
1901 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1,
1902 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80);
1903
1904 /* Switch the control path to firmware. */
1905 reg = rsu_read_2(sc, R92S_SYS_CLKR);
1906 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL;
1907 rsu_write_2(sc, R92S_SYS_CLKR, reg);
1908
1909 rsu_write_2(sc, R92S_CR, 0x37fc);
1910
1911 /* Fix USB RX FIFO issue. */
1912 rsu_write_1(sc, 0xfe5c,
1913 rsu_read_1(sc, 0xfe5c) | 0x80);
1914
1915 rsu_write_1(sc, R92S_SYS_CLKR,
1916 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL);
1917
1918 rsu_write_1(sc, 0xfe1c, 0x80);
1919
1920 /* Make sure TxDMA is ready to download firmware. */
1921 for (ntries = 0; ntries < 20; ntries++) {
1922 reg = rsu_read_1(sc, R92S_TCR);
1923 if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) ==
1924 (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT))
1925 break;
1926 DELAY(5);
1927 }
1928 if (ntries == 20) {
1929 /* Reset TxDMA. */
1930 reg = rsu_read_1(sc, R92S_CR);
1931 rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN);
1932 DELAY(2);
1933 rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN);
1934 }
1935 }
1936
1937 void
rsu_power_off(struct rsu_softc * sc)1938 rsu_power_off(struct rsu_softc *sc)
1939 {
1940 /* Turn RF off. */
1941 rsu_write_1(sc, R92S_RF_CTRL, 0x00);
1942 usbd_delay_ms(sc->sc_udev, 5);
1943
1944 /* Turn MAC off. */
1945 /* Switch control path. */
1946 rsu_write_1(sc, R92S_SYS_CLKR + 1, 0x38);
1947 /* Reset MACTOP. */
1948 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x70);
1949 rsu_write_1(sc, R92S_PMC_FSM, 0x06);
1950 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 0, 0xf9);
1951 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 0xe8);
1952
1953 /* Disable AFE PLL. */
1954 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 0x00);
1955 /* Disable A15V. */
1956 rsu_write_1(sc, R92S_LDOA15_CTRL, 0x54);
1957 /* Disable eFuse 1.2V. */
1958 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x50);
1959 rsu_write_1(sc, R92S_LDOV12D_CTRL, 0x24);
1960 /* Enable AFE macro block's bandgap and Mbias. */
1961 rsu_write_1(sc, R92S_AFE_MISC, 0x30);
1962 /* Disable 1.6V LDO. */
1963 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x56);
1964 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x43);
1965 }
1966
1967 int
rsu_fw_loadsection(struct rsu_softc * sc,uint8_t * buf,int len)1968 rsu_fw_loadsection(struct rsu_softc *sc, uint8_t *buf, int len)
1969 {
1970 struct rsu_tx_data *data;
1971 struct r92s_tx_desc *txd;
1972 struct usbd_pipe *pipe;
1973 int mlen, error;
1974
1975 data = sc->fwcmd_data;
1976 pipe = sc->pipe[sc->qid2idx[RSU_QID_VO]];
1977 txd = (struct r92s_tx_desc *)data->buf;
1978 while (len > 0) {
1979 memset(txd, 0, sizeof(*txd));
1980 if (len <= RSU_TXBUFSZ - sizeof(*txd)) {
1981 /* Last chunk. */
1982 txd->txdw0 |= htole32(R92S_TXDW0_LINIP);
1983 mlen = len;
1984 } else
1985 mlen = RSU_TXBUFSZ - sizeof(*txd);
1986 txd->txdw0 |= htole32(SM(R92S_TXDW0_PKTLEN, mlen));
1987 memcpy(&txd[1], buf, mlen);
1988
1989 usbd_setup_xfer(data->xfer, pipe, NULL, data->buf,
1990 sizeof(*txd) + mlen,
1991 USBD_SHORT_XFER_OK | USBD_NO_COPY | USBD_SYNCHRONOUS,
1992 RSU_TX_TIMEOUT, NULL);
1993 error = usbd_transfer(data->xfer);
1994 if (error != 0)
1995 return (error);
1996 buf += mlen;
1997 len -= mlen;
1998 }
1999 return (0);
2000 }
2001
2002 int
rsu_load_firmware(struct rsu_softc * sc)2003 rsu_load_firmware(struct rsu_softc *sc)
2004 {
2005 struct ieee80211com *ic = &sc->sc_ic;
2006 struct r92s_fw_hdr *hdr;
2007 struct r92s_fw_priv *dmem;
2008 uint8_t *imem, *emem;
2009 int imemsz, ememsz;
2010 u_char *fw;
2011 size_t size;
2012 uint32_t reg;
2013 int ntries, error;
2014
2015 /* Read firmware image from the filesystem. */
2016 if ((error = loadfirmware("rsu-rtl8712", &fw, &size)) != 0) {
2017 printf("%s: failed loadfirmware of file %s (error %d)\n",
2018 sc->sc_dev.dv_xname, "rsu-rtl8712", error);
2019 return (error);
2020 }
2021 if (size < sizeof(*hdr)) {
2022 printf("%s: firmware too short\n", sc->sc_dev.dv_xname);
2023 error = EINVAL;
2024 goto fail;
2025 }
2026 hdr = (struct r92s_fw_hdr *)fw;
2027 if (hdr->signature != htole16(0x8712) &&
2028 hdr->signature != htole16(0x8192)) {
2029 printf("%s: invalid firmware signature 0x%x\n",
2030 sc->sc_dev.dv_xname, letoh16(hdr->signature));
2031 error = EINVAL;
2032 goto fail;
2033 }
2034 DPRINTF(("FW V%d %02x-%02x %02x:%02x\n", letoh16(hdr->version),
2035 hdr->month, hdr->day, hdr->hour, hdr->minute));
2036
2037 /* Make sure that driver and firmware are in sync. */
2038 if (hdr->privsz != htole32(sizeof(*dmem))) {
2039 printf("%s: unsupported firmware image\n",
2040 sc->sc_dev.dv_xname);
2041 error = EINVAL;
2042 goto fail;
2043 }
2044 /* Get FW sections sizes. */
2045 imemsz = letoh32(hdr->imemsz);
2046 ememsz = letoh32(hdr->sramsz);
2047 /* Check that all FW sections fit in image. */
2048 if (size < sizeof(*hdr) + imemsz + ememsz) {
2049 printf("%s: firmware too short\n", sc->sc_dev.dv_xname);
2050 error = EINVAL;
2051 goto fail;
2052 }
2053 imem = (uint8_t *)&hdr[1];
2054 emem = imem + imemsz;
2055
2056 /* Load IMEM section. */
2057 error = rsu_fw_loadsection(sc, imem, imemsz);
2058 if (error != 0) {
2059 printf("%s: could not load firmware section %s\n",
2060 sc->sc_dev.dv_xname, "IMEM");
2061 goto fail;
2062 }
2063 /* Wait for load to complete. */
2064 for (ntries = 0; ntries < 10; ntries++) {
2065 reg = rsu_read_2(sc, R92S_TCR);
2066 if (reg & R92S_TCR_IMEM_CODE_DONE)
2067 break;
2068 DELAY(10);
2069 }
2070 if (ntries == 10 || !(reg & R92S_TCR_IMEM_CHK_RPT)) {
2071 printf("%s: timeout waiting for %s transfer\n",
2072 sc->sc_dev.dv_xname, "IMEM");
2073 error = ETIMEDOUT;
2074 goto fail;
2075 }
2076
2077 /* Load EMEM section. */
2078 error = rsu_fw_loadsection(sc, emem, ememsz);
2079 if (error != 0) {
2080 printf("%s: could not load firmware section %s\n",
2081 sc->sc_dev.dv_xname, "EMEM");
2082 goto fail;
2083 }
2084 /* Wait for load to complete. */
2085 for (ntries = 0; ntries < 10; ntries++) {
2086 reg = rsu_read_2(sc, R92S_TCR);
2087 if (reg & R92S_TCR_EMEM_CODE_DONE)
2088 break;
2089 DELAY(10);
2090 }
2091 if (ntries == 10 || !(reg & R92S_TCR_EMEM_CHK_RPT)) {
2092 printf("%s: timeout waiting for %s transfer\n",
2093 sc->sc_dev.dv_xname, "EMEM");
2094 error = ETIMEDOUT;
2095 goto fail;
2096 }
2097
2098 /* Enable CPU. */
2099 rsu_write_1(sc, R92S_SYS_CLKR,
2100 rsu_read_1(sc, R92S_SYS_CLKR) | R92S_SYS_CPU_CLKSEL);
2101 if (!(rsu_read_1(sc, R92S_SYS_CLKR) & R92S_SYS_CPU_CLKSEL)) {
2102 printf("%s: could not enable system clock\n",
2103 sc->sc_dev.dv_xname);
2104 error = EIO;
2105 goto fail;
2106 }
2107 rsu_write_2(sc, R92S_SYS_FUNC_EN,
2108 rsu_read_2(sc, R92S_SYS_FUNC_EN) | R92S_FEN_CPUEN);
2109 if (!(rsu_read_2(sc, R92S_SYS_FUNC_EN) & R92S_FEN_CPUEN)) {
2110 printf("%s: could not enable microcontroller\n",
2111 sc->sc_dev.dv_xname);
2112 error = EIO;
2113 goto fail;
2114 }
2115 /* Wait for CPU to initialize. */
2116 for (ntries = 0; ntries < 100; ntries++) {
2117 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_IMEM_RDY)
2118 break;
2119 DELAY(1000);
2120 }
2121 if (ntries == 100) {
2122 printf("%s: timeout waiting for microcontroller\n",
2123 sc->sc_dev.dv_xname);
2124 error = ETIMEDOUT;
2125 goto fail;
2126 }
2127
2128 /* Update DMEM section before loading. */
2129 dmem = &hdr->priv;
2130 memset(dmem, 0, sizeof(*dmem));
2131 dmem->hci_sel = R92S_HCI_SEL_USB | R92S_HCI_SEL_8172;
2132 dmem->nendpoints = sc->npipes;
2133 dmem->rf_config = 0x12; /* 1T2R */
2134 dmem->vcs_type = R92S_VCS_TYPE_AUTO;
2135 dmem->vcs_mode = R92S_VCS_MODE_RTS_CTS;
2136 dmem->bw40_en = (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) != 0;
2137 dmem->turbo_mode = 1;
2138 /* Load DMEM section. */
2139 error = rsu_fw_loadsection(sc, (uint8_t *)dmem, sizeof(*dmem));
2140 if (error != 0) {
2141 printf("%s: could not load firmware section %s\n",
2142 sc->sc_dev.dv_xname, "DMEM");
2143 goto fail;
2144 }
2145 /* Wait for load to complete. */
2146 for (ntries = 0; ntries < 100; ntries++) {
2147 if (rsu_read_2(sc, R92S_TCR) & R92S_TCR_DMEM_CODE_DONE)
2148 break;
2149 DELAY(1000);
2150 }
2151 if (ntries == 100) {
2152 printf("%s: timeout waiting for %s transfer\n",
2153 sc->sc_dev.dv_xname, "DMEM");
2154 error = ETIMEDOUT;
2155 goto fail;
2156 }
2157 /* Wait for firmware readiness. */
2158 for (ntries = 0; ntries < 60; ntries++) {
2159 if (!(rsu_read_2(sc, R92S_TCR) & R92S_TCR_FWRDY))
2160 break;
2161 DELAY(1000);
2162 }
2163 if (ntries == 60) {
2164 printf("%s: timeout waiting for firmware readiness\n",
2165 sc->sc_dev.dv_xname);
2166 error = ETIMEDOUT;
2167 goto fail;
2168 }
2169 fail:
2170 free(fw, M_DEVBUF, size);
2171 return (error);
2172 }
2173
2174 int
rsu_init(struct ifnet * ifp)2175 rsu_init(struct ifnet *ifp)
2176 {
2177 struct rsu_softc *sc = ifp->if_softc;
2178 struct ieee80211com *ic = &sc->sc_ic;
2179 struct r92s_set_pwr_mode cmd;
2180 struct rsu_rx_data *data;
2181 int i, error;
2182
2183 /* Init host async commands ring. */
2184 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0;
2185
2186 /* Allocate Tx/Rx buffers. */
2187 error = rsu_alloc_rx_list(sc);
2188 if (error != 0) {
2189 printf("%s: could not allocate Rx buffers\n",
2190 sc->sc_dev.dv_xname);
2191 goto fail;
2192 }
2193 error = rsu_alloc_tx_list(sc);
2194 if (error != 0) {
2195 printf("%s: could not allocate Tx buffers\n",
2196 sc->sc_dev.dv_xname);
2197 goto fail;
2198 }
2199 /* Reserve one Tx buffer for firmware commands. */
2200 sc->fwcmd_data = TAILQ_FIRST(&sc->tx_free_list);
2201 TAILQ_REMOVE(&sc->tx_free_list, sc->fwcmd_data, next);
2202
2203 /* Power on adapter. */
2204 if (sc->cut == 1)
2205 rsu_power_on_acut(sc);
2206 else
2207 rsu_power_on_bcut(sc);
2208 /* Load firmware. */
2209 error = rsu_load_firmware(sc);
2210 if (error != 0)
2211 goto fail;
2212
2213 /* Enable Rx TCP checksum offload. */
2214 rsu_write_4(sc, R92S_RCR,
2215 rsu_read_4(sc, R92S_RCR) | 0x04000000);
2216 /* Append PHY status. */
2217 rsu_write_4(sc, R92S_RCR,
2218 rsu_read_4(sc, R92S_RCR) | 0x02000000);
2219
2220 rsu_write_4(sc, R92S_CR,
2221 rsu_read_4(sc, R92S_CR) & ~0xff000000);
2222
2223 /* Use 128 bytes pages. */
2224 rsu_write_1(sc, 0x00b5,
2225 rsu_read_1(sc, 0x00b5) | 0x01);
2226 /* Enable USB Rx aggregation. */
2227 rsu_write_1(sc, 0x00bd,
2228 rsu_read_1(sc, 0x00bd) | 0x80);
2229 /* Set USB Rx aggregation threshold. */
2230 rsu_write_1(sc, 0x00d9, 0x01);
2231 /* Set USB Rx aggregation timeout (1.7ms/4). */
2232 rsu_write_1(sc, 0xfe5b, 0x04);
2233 /* Fix USB Rx FIFO issue. */
2234 rsu_write_1(sc, 0xfe5c,
2235 rsu_read_1(sc, 0xfe5c) | 0x80);
2236
2237 /* Set MAC address. */
2238 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl));
2239 rsu_write_region_1(sc, R92S_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN);
2240
2241 /* Queue Rx xfers (XXX C2H pipe for 11-pipe configurations?) */
2242 for (i = 0; i < RSU_RX_LIST_COUNT; i++) {
2243 data = &sc->rx_data[i];
2244
2245 data->pipe = sc->pipe[sc->qid2idx[RSU_QID_RXOFF]];
2246 usbd_setup_xfer(data->xfer, data->pipe, data, data->buf,
2247 RSU_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY,
2248 USBD_NO_TIMEOUT, rsu_rxeof);
2249 error = usbd_transfer(data->xfer);
2250 if (error != 0 && error != USBD_IN_PROGRESS)
2251 goto fail;
2252 }
2253
2254 /* NB: it really takes that long for firmware to boot. */
2255 usbd_delay_ms(sc->sc_udev, 1500);
2256
2257 DPRINTF(("setting MAC address to %s\n", ether_sprintf(ic->ic_myaddr)));
2258 error = rsu_fw_cmd(sc, R92S_CMD_SET_MAC_ADDRESS, ic->ic_myaddr,
2259 IEEE80211_ADDR_LEN);
2260 if (error != 0) {
2261 printf("%s: could not set MAC address\n", sc->sc_dev.dv_xname);
2262 goto fail;
2263 }
2264
2265 rsu_write_1(sc, R92S_USB_HRPWM,
2266 R92S_USB_HRPWM_PS_ST_ACTIVE | R92S_USB_HRPWM_PS_ALL_ON);
2267
2268 memset(&cmd, 0, sizeof(cmd));
2269 cmd.mode = R92S_PS_MODE_ACTIVE;
2270 DPRINTF(("setting ps mode to %d\n", cmd.mode));
2271 error = rsu_fw_cmd(sc, R92S_CMD_SET_PWR_MODE, &cmd, sizeof(cmd));
2272 if (error != 0) {
2273 printf("%s: could not set PS mode\n", sc->sc_dev.dv_xname);
2274 goto fail;
2275 }
2276
2277 if (ic->ic_htcaps & IEEE80211_HTCAP_CBW20_40) {
2278 /* Enable 40MHz mode. */
2279 error = rsu_fw_iocmd(sc,
2280 SM(R92S_IOCMD_CLASS, 0xf4) |
2281 SM(R92S_IOCMD_INDEX, 0x00) |
2282 SM(R92S_IOCMD_VALUE, 0x0007));
2283 if (error != 0) {
2284 printf("%s: could not enable 40MHz mode\n",
2285 sc->sc_dev.dv_xname);
2286 goto fail;
2287 }
2288 }
2289
2290 /* Set default channel. */
2291 ic->ic_bss->ni_chan = ic->ic_ibss_chan;
2292
2293 /* We're ready to go. */
2294 ifp->if_flags |= IFF_RUNNING;
2295 ifq_clr_oactive(&ifp->if_snd);
2296
2297 #ifdef notyet
2298 if (ic->ic_flags & IEEE80211_F_WEPON) {
2299 /* Install WEP keys. */
2300 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2301 rsu_set_key(ic, NULL, &ic->ic_nw_keys[i]);
2302 rsu_wait_async(sc);
2303 }
2304 #endif
2305
2306 sc->scan_pass = 0;
2307 ieee80211_begin_scan(ifp);
2308 return (0);
2309 fail:
2310 rsu_stop(ifp);
2311 return (error);
2312 }
2313
2314 void
rsu_stop(struct ifnet * ifp)2315 rsu_stop(struct ifnet *ifp)
2316 {
2317 struct rsu_softc *sc = ifp->if_softc;
2318 struct ieee80211com *ic = &sc->sc_ic;
2319 int i, s;
2320
2321 sc->sc_tx_timer = 0;
2322 ifp->if_timer = 0;
2323 ifp->if_flags &= ~IFF_RUNNING;
2324 ifq_clr_oactive(&ifp->if_snd);
2325
2326 s = splusb();
2327 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2328 /* Wait for all async commands to complete. */
2329 rsu_wait_async(sc);
2330 splx(s);
2331
2332 timeout_del(&sc->calib_to);
2333
2334 /* Power off adapter. */
2335 rsu_power_off(sc);
2336
2337 /* Abort Tx/Rx. */
2338 for (i = 0; i < sc->npipes; i++)
2339 usbd_abort_pipe(sc->pipe[i]);
2340
2341 /* Free Tx/Rx buffers. */
2342 rsu_free_tx_list(sc);
2343 rsu_free_rx_list(sc);
2344 }
2345