1 /* $OpenBSD: if_rtw_cardbus.c,v 1.28 2024/05/24 06:26:47 jsg Exp $ */
2 /* $NetBSD: if_rtw_cardbus.c,v 1.4 2004/12/20 21:05:34 dyoung Exp $ */
3
4 /*-
5 * Copyright (c) 2004, 2005 David Young. All rights reserved.
6 *
7 * Adapted for the RTL8180 by David Young.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of David Young may not be used to endorse or promote
18 * products derived from this software without specific prior
19 * written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
23 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
24 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
25 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
26 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
27 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 * OF SUCH DAMAGE.
33 */
34 /*-
35 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to The NetBSD Foundation
39 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
40 * NASA Ames Research Center.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
44 * are met:
45 * 1. Redistributions of source code must retain the above copyright
46 * notice, this list of conditions and the following disclaimer.
47 * 2. Redistributions in binary form must reproduce the above copyright
48 * notice, this list of conditions and the following disclaimer in the
49 * documentation and/or other materials provided with the distribution.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
52 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
53 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
54 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
55 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
56 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
57 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
58 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
59 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
60 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61 * POSSIBILITY OF SUCH DAMAGE.
62 */
63
64 /*
65 * Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver.
66 *
67 * TBD factor with atw, tlp Cardbus front-ends?
68 */
69
70 #include "bpfilter.h"
71
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/device.h>
75
76 #include <net/if.h>
77 #include <net/if_media.h>
78
79 #include <netinet/in.h>
80 #include <netinet/if_ether.h>
81
82 #include <net80211/ieee80211_radiotap.h>
83 #include <net80211/ieee80211_var.h>
84
85 #include <machine/bus.h>
86
87 #include <dev/ic/rtwreg.h>
88 #include <dev/ic/rtwvar.h>
89
90 #include <dev/pci/pcivar.h>
91 #include <dev/pci/pcireg.h>
92 #include <dev/pci/pcidevs.h>
93
94 #include <dev/cardbus/cardbusvar.h>
95
96 /*
97 * PCI configuration space registers used by the RTL8180.
98 */
99 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */
100 #define RTW_PCI_MMBA 0x14 /* memory mapped base */
101
102 struct rtw_cardbus_softc {
103 struct rtw_softc sc_rtw; /* real RTL8180 softc */
104
105 /* CardBus-specific goo. */
106 void *sc_ih; /* interrupt handle */
107 cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
108 pcitag_t sc_tag; /* our CardBus tag */
109 pci_chipset_tag_t sc_pc; /* PCI chipset */
110 int sc_csr; /* CSR bits */
111 bus_size_t sc_mapsize; /* size of the mapped bus space
112 * region
113 */
114
115 int sc_cben; /* CardBus enables */
116 int sc_bar_reg; /* which BAR to use */
117 pcireg_t sc_bar_val; /* value of the BAR */
118
119 int sc_intrline; /* interrupt line */
120 };
121
122 int rtw_cardbus_match(struct device *, void *, void *);
123 void rtw_cardbus_attach(struct device *, struct device *, void *);
124 int rtw_cardbus_detach(struct device *, int);
125 void rtw_cardbus_intr_ack(struct rtw_regs *);
126 void rtw_cardbus_funcregen(struct rtw_regs *, int);
127
128 const struct cfattach rtw_cardbus_ca = {
129 sizeof(struct rtw_cardbus_softc), rtw_cardbus_match, rtw_cardbus_attach,
130 rtw_cardbus_detach
131 };
132
133 void rtw_cardbus_setup(struct rtw_cardbus_softc *);
134
135 int rtw_cardbus_enable(struct rtw_softc *);
136 void rtw_cardbus_disable(struct rtw_softc *);
137 void rtw_cardbus_power(struct rtw_softc *, int);
138
139 const struct pci_matchid rtw_cardbus_devices[] = {
140 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180 },
141 #ifdef RTW_DEBUG
142 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8185 },
143 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D7010 },
144 #endif
145 { PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6020V3 },
146 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610 }
147 };
148
149 int
rtw_cardbus_match(struct device * parent,void * match,void * aux)150 rtw_cardbus_match(struct device *parent, void *match, void *aux)
151 {
152 return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
153 rtw_cardbus_devices, nitems(rtw_cardbus_devices)));
154 }
155
156 void
rtw_cardbus_intr_ack(struct rtw_regs * regs)157 rtw_cardbus_intr_ack(struct rtw_regs *regs)
158 {
159 RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
160 }
161
162 void
rtw_cardbus_funcregen(struct rtw_regs * regs,int enable)163 rtw_cardbus_funcregen(struct rtw_regs *regs, int enable)
164 {
165 u_int32_t reg;
166 rtw_config0123_enable(regs, 1);
167 reg = RTW_READ(regs, RTW_CONFIG3);
168 if (enable) {
169 RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);
170 } else {
171 RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);
172 }
173 rtw_config0123_enable(regs, 0);
174 }
175
176 void
rtw_cardbus_attach(struct device * parent,struct device * self,void * aux)177 rtw_cardbus_attach(struct device *parent, struct device *self, void *aux)
178 {
179 struct rtw_cardbus_softc *csc = (void *)self;
180 struct rtw_softc *sc = &csc->sc_rtw;
181 struct rtw_regs *regs = &sc->sc_regs;
182 struct cardbus_attach_args *ca = aux;
183 cardbus_devfunc_t ct = ca->ca_ct;
184 bus_addr_t adr;
185 int rev;
186
187 sc->sc_dmat = ca->ca_dmat;
188 csc->sc_ct = ct;
189 csc->sc_tag = ca->ca_tag;
190 csc->sc_pc = ca->ca_pc;
191
192 /*
193 * Power management hooks.
194 */
195 sc->sc_enable = rtw_cardbus_enable;
196 sc->sc_disable = rtw_cardbus_disable;
197 sc->sc_power = rtw_cardbus_power;
198
199 sc->sc_intr_ack = rtw_cardbus_intr_ack;
200
201 /* Get revision info. */
202 rev = PCI_REVISION(ca->ca_class);
203
204 RTW_DPRINTF(RTW_DEBUG_ATTACH,
205 ("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
206 (rev >> 4) & 0xf, rev & 0xf,
207 pci_conf_read(ca->ca_pc, csc->sc_tag, 0x80)));
208
209 /*
210 * Map the device.
211 */
212 csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
213 if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA,
214 PCI_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr,
215 &csc->sc_mapsize) == 0) {
216 RTW_DPRINTF(RTW_DEBUG_ATTACH,
217 ("%s: %s mapped %lu bytes mem space\n",
218 sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
219 csc->sc_cben = CARDBUS_MEM_ENABLE;
220 csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
221 csc->sc_bar_reg = RTW_PCI_MMBA;
222 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
223 } else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA,
224 PCI_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr,
225 &csc->sc_mapsize) == 0) {
226 RTW_DPRINTF(RTW_DEBUG_ATTACH,
227 ("%s: %s mapped %lu bytes I/O space\n",
228 sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
229 csc->sc_cben = CARDBUS_IO_ENABLE;
230 csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
231 csc->sc_bar_reg = RTW_PCI_IOBA;
232 csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
233 } else {
234 printf("%s: unable to map device registers\n",
235 sc->sc_dev.dv_xname);
236 return;
237 }
238
239 /*
240 * Bring the chip out of powersave mode and initialize the
241 * configuration registers.
242 */
243 rtw_cardbus_setup(csc);
244
245 /* Remember which interrupt line. */
246 csc->sc_intrline = ca->ca_intrline;
247
248 printf(": irq %d\n", csc->sc_intrline);
249
250 /*
251 * Finish off the attach.
252 */
253 rtw_attach(sc);
254
255 rtw_cardbus_funcregen(regs, 1);
256
257 RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR);
258 RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
259
260 /*
261 * Power down the socket.
262 */
263 Cardbus_function_disable(csc->sc_ct);
264 }
265
266 int
rtw_cardbus_detach(struct device * self,int flags)267 rtw_cardbus_detach(struct device *self, int flags)
268 {
269 struct rtw_cardbus_softc *csc = (void *)self;
270 struct rtw_softc *sc = &csc->sc_rtw;
271 struct rtw_regs *regs = &sc->sc_regs;
272 struct cardbus_devfunc *ct = csc->sc_ct;
273 int rv;
274
275 #if defined(DIAGNOSTIC)
276 if (ct == NULL)
277 panic("%s: data structure lacks", sc->sc_dev.dv_xname);
278 #endif
279
280 rv = rtw_detach(sc);
281 if (rv)
282 return (rv);
283
284 rtw_cardbus_funcregen(regs, 0);
285
286 /*
287 * Unhook the interrupt handler.
288 */
289 if (csc->sc_ih != NULL)
290 cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
291
292 /*
293 * Release bus space and close window.
294 */
295 if (csc->sc_bar_reg != 0)
296 Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
297 regs->r_bt, regs->r_bh, csc->sc_mapsize);
298
299 return (0);
300 }
301
302 int
rtw_cardbus_enable(struct rtw_softc * sc)303 rtw_cardbus_enable(struct rtw_softc *sc)
304 {
305 struct rtw_cardbus_softc *csc = (void *) sc;
306 cardbus_devfunc_t ct = csc->sc_ct;
307 cardbus_chipset_tag_t cc = ct->ct_cc;
308 cardbus_function_tag_t cf = ct->ct_cf;
309
310 /*
311 * Power on the socket.
312 */
313 Cardbus_function_enable(ct);
314
315 /*
316 * Set up the PCI configuration registers.
317 */
318 rtw_cardbus_setup(csc);
319
320 /*
321 * Map and establish the interrupt.
322 */
323 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
324 rtw_intr, sc, sc->sc_dev.dv_xname);
325 if (csc->sc_ih == NULL) {
326 printf("%s: unable to establish interrupt at %d\n",
327 sc->sc_dev.dv_xname, csc->sc_intrline);
328 Cardbus_function_disable(csc->sc_ct);
329 return (1);
330 }
331
332 rtw_cardbus_funcregen(&sc->sc_regs, 1);
333
334 RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR);
335 RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR);
336
337 return (0);
338 }
339
340 void
rtw_cardbus_disable(struct rtw_softc * sc)341 rtw_cardbus_disable(struct rtw_softc *sc)
342 {
343 struct rtw_cardbus_softc *csc = (void *) sc;
344 cardbus_devfunc_t ct = csc->sc_ct;
345 cardbus_chipset_tag_t cc = ct->ct_cc;
346 cardbus_function_tag_t cf = ct->ct_cf;
347
348 RTW_WRITE(&sc->sc_regs, RTW_FEMR,
349 RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR);
350
351 rtw_cardbus_funcregen(&sc->sc_regs, 0);
352
353 /* Unhook the interrupt handler. */
354 cardbus_intr_disestablish(cc, cf, csc->sc_ih);
355 csc->sc_ih = NULL;
356
357 /* Power down the socket. */
358 Cardbus_function_disable(ct);
359 }
360
361 void
rtw_cardbus_power(struct rtw_softc * sc,int why)362 rtw_cardbus_power(struct rtw_softc *sc, int why)
363 {
364 RTW_DPRINTF(RTW_DEBUG_ATTACH,
365 ("%s: rtw_cardbus_power\n", sc->sc_dev.dv_xname));
366
367 if (why == DVACT_RESUME)
368 rtw_enable(sc);
369 }
370
371 void
rtw_cardbus_setup(struct rtw_cardbus_softc * csc)372 rtw_cardbus_setup(struct rtw_cardbus_softc *csc)
373 {
374 struct rtw_softc *sc = &csc->sc_rtw;
375 cardbus_devfunc_t ct = csc->sc_ct;
376 cardbus_chipset_tag_t cc = ct->ct_cc;
377 pci_chipset_tag_t pc = csc->sc_pc;
378 pcireg_t reg;
379 int pmreg;
380
381 if (pci_get_capability(pc, csc->sc_tag,
382 PCI_CAP_PWRMGMT, &pmreg, 0)) {
383 reg = pci_conf_read(pc, csc->sc_tag, pmreg + 4) & 0x03;
384 #if 1 /* XXX Probably not right for CardBus. */
385 if (reg == 3) {
386 /*
387 * The card has lost all configuration data in
388 * this state, so punt.
389 */
390 printf("%s: unable to wake up from power state D3\n",
391 sc->sc_dev.dv_xname);
392 return;
393 }
394 #endif
395 if (reg != 0) {
396 printf("%s: waking up from power state D%d\n",
397 sc->sc_dev.dv_xname, reg);
398 pci_conf_write(pc, csc->sc_tag,
399 pmreg + 4, 0);
400 }
401 }
402
403 /* Program the BAR. */
404 pci_conf_write(pc, csc->sc_tag, csc->sc_bar_reg,
405 csc->sc_bar_val);
406
407 /* Make sure the right access type is on the CardBus bridge. */
408 (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
409 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
410
411 /* Enable the appropriate bits in the PCI CSR. */
412 reg = pci_conf_read(pc, csc->sc_tag,
413 PCI_COMMAND_STATUS_REG);
414 reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
415 reg |= csc->sc_csr;
416 pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
417 reg);
418
419 /*
420 * Make sure the latency timer is set to some reasonable
421 * value.
422 */
423 reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
424 if (PCI_LATTIMER(reg) < 0x20) {
425 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
426 reg |= (0x20 << PCI_LATTIMER_SHIFT);
427 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
428 }
429 }
430