1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Computer Consoles Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_acereg.h 7.2 (Berkeley) 05/08/91 11 */ 12 13 /* 14 * VERSAbus ACC ethernet controller definitions 15 */ 16 17 /* 18 * Register definitions 19 */ 20 struct acedevice { 21 short station[6]; /* station address */ 22 short bcastena[2]; /* broadcast enable */ 23 short hash[8]; /* multicast hash codes */ 24 short csr; /* control and status register */ 25 short tseg; /* current transmit segment # */ 26 short rseg; /* current receive segment # */ 27 short segb; /* segment boundary register */ 28 short lrf; /* lost receive frame counter */ 29 short ivct; /* interrupt vector register */ 30 short resv; /* reserved for future use */ 31 short fcoll; /* force collision register */ 32 }; 33 34 /* 35 * Transmit segment in dual ported ram. 36 */ 37 struct tx_segment { 38 short tx_csr; /* packet status */ 39 char tx_data[2014]; 40 short tx_backoff[16]; /* random backoff counters */ 41 }; 42 43 /* 44 * Receive segment in dual ported ram. 45 */ 46 struct rx_segment { 47 short rx_csr; /* packet status */ 48 char rx_data[2046]; 49 }; 50 51 /* 52 * ACC statistics block. 53 */ 54 struct ace_stats { 55 int rx_datagrams; /* valid packets received */ 56 int rx_crc_errors; /* CRC errors */ 57 int rx_overruns; /* packets too large */ 58 int rx_underruns; /* packets too small */ 59 int rx_align_errors; /* packets w/ odd byte count */ 60 int rx_reserved; 61 int rx_busy; /* recv segment filled */ 62 int rx_mbuf; /* out of mbufs */ 63 int rx_oddoff; /* odd offset in mbuf */ 64 int rx_rintcnt; /* recvr interrupt */ 65 66 int tx_datagrams; /* packets xmit'd */ 67 int tx_retries; /* collision retries */ 68 int tx_discarded; /* packets w/ max retries */ 69 int tx_busy; /* xmit segment filled in acestart */ 70 int tx_cbusy; /* xmit segment filled in acecint */ 71 int tx_mbuf; /* total mbufs */ 72 int tx_oddoff; /* odd offset in mbuf */ 73 int tx_outcnt; /* calls to aceoutput */ 74 int tx_startcnt; /* calls to acestart */ 75 int tx_cintcnt; /* xmit's completed */ 76 }; 77 78 /* 79 * Control status definitions. 80 */ 81 #define CSR_OBCENA 0x0200 /* enable xmit of odd byte count */ 82 #define CSR_ACTIVE 0x0080 /* board active */ 83 #define CSR_RESET 0x0040 /* reset board */ 84 #define CSR_PROMISC 0x0020 /* enable promiscous mode */ 85 #define CSR_CRCDIS 0x0010 /* disable CRC generation */ 86 #define CSR_LOOP3 0x0008 /* enable loopback mode 3 */ 87 #define CSR_LOOP2 0x0004 /* enable loopback mode 2 */ 88 #define CSR_IENA 0x0002 /* interrupt enable */ 89 #define CSR_GO 0x0001 /* enable micro-engine */ 90 91 #define ACE_CSRBITS \ 92 "\20\12OBCENA\10ACTIVE\7RESET\6PROMISC\5CRCDIS\4LOOP3\3LOOP2\2IENA\1GO" 93 /* 94 * Transmit packet status definitions. 95 */ 96 #define TCS_TBFULL (short)0x8000 /* buffer filled, send it */ 97 #define TCS_TBC (short)0x07FF /* byte count */ 98 #define TCS_TBMT (short)0x8000 /* buffer empty */ 99 #define TCS_RTFAIL (short)0x4000 /* retries failed */ 100 #define TCS_RTC (short)0x000F /* collision retry mask */ 101 102 /* 103 * Receive packet status definitions. 104 */ 105 #define RCS_RBMT 0x8000 /* buffer ready for recv */ 106 #define RCS_RBFULL 0x8000 /* buffer full, take data */ 107 #define RCS_ROVRN 0x4000 /* overrun error */ 108 #define RCS_RCRC 0x2000 /* CRC error */ 109 #define RCS_RODD 0x1000 /* odd byte count error */ 110 #define RCS_RBC 0x07FF /* byte count mask */ 111 112 #define ACE_RCSBITS "\20\20RBFULL\17ROVRN\16RCSR\15RODD" 113 114 #define CRC_SIZE 4 /* number of bytes in a rx seg's CRC */ 115 #define RCW_SIZE 2 /* number of bytes in a rx seg's csr */ 116 #define SEG_MAX 15 /* largest valid segment number */ 117 #define ET_MINLEN 64 /* min frame size */ 118 #define ET_MAXLEN 1514 /* max frame size w/o CRC & RCW */ 119