1 /*
2 * S/390 virtual CPU header
3 *
4 * For details on the s390x architecture and used definitions (e.g.,
5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
7 *
8 * Copyright (c) 2009 Ulrich Hecht
9 * Copyright IBM Corp. 2012, 2018
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #ifndef S390X_CPU_H
26 #define S390X_CPU_H
27
28 #include "cpu-qom.h"
29 #include "cpu_models.h"
30 #include "exec/cpu-defs.h"
31 #include "qemu/cpu-float.h"
32 #include "qapi/qapi-types-machine-common.h"
33
34 #define ELF_MACHINE_UNAME "S390X"
35
36 #define TARGET_HAS_PRECISE_SMC
37
38 #define TARGET_INSN_START_EXTRA_WORDS 2
39
40 #define MMU_USER_IDX 0
41
42 #define S390_MAX_CPUS 248
43
44 #ifndef CONFIG_KVM
45 #define S390_ADAPTER_SUPPRESSIBLE 0x01
46 #else
47 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
48 #endif
49
50 typedef struct PSW {
51 uint64_t mask;
52 uint64_t addr;
53 } PSW;
54
55 typedef struct CPUArchState {
56 uint64_t regs[16]; /* GP registers */
57 /*
58 * The floating point registers are part of the vector registers.
59 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
60 */
61 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
62 uint32_t aregs[16]; /* access registers */
63 uint64_t gscb[4]; /* guarded storage control */
64 uint64_t etoken; /* etoken */
65 uint64_t etoken_extension; /* etoken extension */
66
67 uint64_t diag318_info;
68
69 /* Fields up to this point are not cleared by initial CPU reset */
70 struct {} start_initial_reset_fields;
71
72 uint32_t fpc; /* floating-point control register */
73 uint32_t cc_op;
74 bool bpbc; /* branch prediction blocking */
75
76 float_status fpu_status; /* passed to softfloat lib */
77
78 PSW psw;
79
80 S390CrashReason crash_reason;
81
82 uint64_t cc_src;
83 uint64_t cc_dst;
84 uint64_t cc_vr;
85
86 uint64_t ex_value;
87 uint64_t ex_target;
88
89 uint64_t __excp_addr;
90 uint64_t psa;
91
92 uint32_t int_pgm_code;
93 uint32_t int_pgm_ilen;
94
95 uint32_t int_svc_code;
96 uint32_t int_svc_ilen;
97
98 uint64_t per_address;
99 uint16_t per_perc_atmid;
100
101 uint64_t cregs[16]; /* control registers */
102
103 uint64_t ckc;
104 uint64_t cputm;
105 uint32_t todpr;
106
107 uint64_t pfault_token;
108 uint64_t pfault_compare;
109 uint64_t pfault_select;
110
111 uint64_t gbea;
112 uint64_t pp;
113
114 /* Fields up to this point are not cleared by normal CPU reset */
115 struct {} start_normal_reset_fields;
116 uint8_t riccb[64]; /* runtime instrumentation control */
117
118 int pending_int;
119 uint16_t external_call_addr;
120 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
121
122 #if !defined(CONFIG_USER_ONLY)
123 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */
124 int tlb_fill_exc; /* exception number seen during tlb_fill */
125 #endif
126
127 /* Fields up to this point are cleared by a CPU reset */
128 struct {} end_reset_fields;
129
130 #if !defined(CONFIG_USER_ONLY)
131 uint32_t core_id; /* PoP "CPU address", same as cpu_index */
132 int32_t socket_id;
133 int32_t book_id;
134 int32_t drawer_id;
135 bool dedicated;
136 S390CpuEntitlement entitlement; /* Used only for vertical polarization */
137 uint64_t cpuid;
138 #endif
139
140 QEMUTimer *tod_timer;
141
142 QEMUTimer *cpu_timer;
143
144 /*
145 * The cpu state represents the logical state of a cpu. In contrast to other
146 * architectures, there is a difference between a halt and a stop on s390.
147 * If all cpus are either stopped (including check stop) or in the disabled
148 * wait state, the vm can be shut down.
149 * The acceptable cpu_state values are defined in the CpuInfoS390State
150 * enum.
151 */
152 uint8_t cpu_state;
153
154 /* currently processed sigp order */
155 uint8_t sigp_order;
156
157 } CPUS390XState;
158
get_freg(CPUS390XState * cs,int nr)159 static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
160 {
161 return &cs->vregs[nr][0];
162 }
163
164 /**
165 * S390CPU:
166 * @env: #CPUS390XState.
167 *
168 * An S/390 CPU.
169 */
170 struct ArchCPU {
171 CPUState parent_obj;
172
173 CPUS390XState env;
174 S390CPUModel *model;
175 /* needed for live migration */
176 void *irqstate;
177 uint32_t irqstate_saved_size;
178 };
179
180 /**
181 * S390CPUClass:
182 * @parent_realize: The parent class' realize handler.
183 * @parent_phases: The parent class' reset phase handlers.
184 * @load_normal: Performs a load normal.
185 *
186 * An S/390 CPU model.
187 */
188 struct S390CPUClass {
189 CPUClass parent_class;
190
191 const S390CPUDef *cpu_def;
192 bool kvm_required;
193 bool is_static;
194 bool is_migration_safe;
195 const char *desc;
196
197 DeviceRealize parent_realize;
198 ResettablePhases parent_phases;
199 void (*load_normal)(CPUState *cpu);
200 };
201
202 #ifndef CONFIG_USER_ONLY
203 extern const VMStateDescription vmstate_s390_cpu;
204 #endif
205
206 /* distinguish between 24 bit and 31 bit addressing */
207 #define HIGH_ORDER_BIT 0x80000000
208
209 /* Interrupt Codes */
210 /* Program Interrupts */
211 #define PGM_OPERATION 0x0001
212 #define PGM_PRIVILEGED 0x0002
213 #define PGM_EXECUTE 0x0003
214 #define PGM_PROTECTION 0x0004
215 #define PGM_ADDRESSING 0x0005
216 #define PGM_SPECIFICATION 0x0006
217 #define PGM_DATA 0x0007
218 #define PGM_FIXPT_OVERFLOW 0x0008
219 #define PGM_FIXPT_DIVIDE 0x0009
220 #define PGM_DEC_OVERFLOW 0x000a
221 #define PGM_DEC_DIVIDE 0x000b
222 #define PGM_HFP_EXP_OVERFLOW 0x000c
223 #define PGM_HFP_EXP_UNDERFLOW 0x000d
224 #define PGM_HFP_SIGNIFICANCE 0x000e
225 #define PGM_HFP_DIVIDE 0x000f
226 #define PGM_SEGMENT_TRANS 0x0010
227 #define PGM_PAGE_TRANS 0x0011
228 #define PGM_TRANS_SPEC 0x0012
229 #define PGM_SPECIAL_OP 0x0013
230 #define PGM_OPERAND 0x0015
231 #define PGM_TRACE_TABLE 0x0016
232 #define PGM_VECTOR_PROCESSING 0x001b
233 #define PGM_SPACE_SWITCH 0x001c
234 #define PGM_HFP_SQRT 0x001d
235 #define PGM_PC_TRANS_SPEC 0x001f
236 #define PGM_AFX_TRANS 0x0020
237 #define PGM_ASX_TRANS 0x0021
238 #define PGM_LX_TRANS 0x0022
239 #define PGM_EX_TRANS 0x0023
240 #define PGM_PRIM_AUTH 0x0024
241 #define PGM_SEC_AUTH 0x0025
242 #define PGM_ALET_SPEC 0x0028
243 #define PGM_ALEN_SPEC 0x0029
244 #define PGM_ALE_SEQ 0x002a
245 #define PGM_ASTE_VALID 0x002b
246 #define PGM_ASTE_SEQ 0x002c
247 #define PGM_EXT_AUTH 0x002d
248 #define PGM_STACK_FULL 0x0030
249 #define PGM_STACK_EMPTY 0x0031
250 #define PGM_STACK_SPEC 0x0032
251 #define PGM_STACK_TYPE 0x0033
252 #define PGM_STACK_OP 0x0034
253 #define PGM_ASCE_TYPE 0x0038
254 #define PGM_REG_FIRST_TRANS 0x0039
255 #define PGM_REG_SEC_TRANS 0x003a
256 #define PGM_REG_THIRD_TRANS 0x003b
257 #define PGM_MONITOR 0x0040
258 #define PGM_PER 0x0080
259 #define PGM_CRYPTO 0x0119
260
261 /* External Interrupts */
262 #define EXT_INTERRUPT_KEY 0x0040
263 #define EXT_CLOCK_COMP 0x1004
264 #define EXT_CPU_TIMER 0x1005
265 #define EXT_MALFUNCTION 0x1200
266 #define EXT_EMERGENCY 0x1201
267 #define EXT_EXTERNAL_CALL 0x1202
268 #define EXT_ETR 0x1406
269 #define EXT_SERVICE 0x2401
270 #define EXT_VIRTIO 0x2603
271
272 /* PSW defines */
273 #undef PSW_MASK_PER
274 #undef PSW_MASK_UNUSED_2
275 #undef PSW_MASK_UNUSED_3
276 #undef PSW_MASK_DAT
277 #undef PSW_MASK_IO
278 #undef PSW_MASK_EXT
279 #undef PSW_MASK_KEY
280 #undef PSW_SHIFT_KEY
281 #undef PSW_MASK_MCHECK
282 #undef PSW_MASK_WAIT
283 #undef PSW_MASK_PSTATE
284 #undef PSW_MASK_ASC
285 #undef PSW_SHIFT_ASC
286 #undef PSW_MASK_CC
287 #undef PSW_MASK_PM
288 #undef PSW_MASK_RI
289 #undef PSW_SHIFT_MASK_PM
290 #undef PSW_MASK_64
291 #undef PSW_MASK_32
292 #undef PSW_MASK_ESA_ADDR
293
294 #define PSW_MASK_PER 0x4000000000000000ULL
295 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
296 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL
297 #define PSW_MASK_DAT 0x0400000000000000ULL
298 #define PSW_MASK_IO 0x0200000000000000ULL
299 #define PSW_MASK_EXT 0x0100000000000000ULL
300 #define PSW_MASK_KEY 0x00F0000000000000ULL
301 #define PSW_SHIFT_KEY 52
302 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
303 #define PSW_MASK_MCHECK 0x0004000000000000ULL
304 #define PSW_MASK_WAIT 0x0002000000000000ULL
305 #define PSW_MASK_PSTATE 0x0001000000000000ULL
306 #define PSW_MASK_ASC 0x0000C00000000000ULL
307 #define PSW_SHIFT_ASC 46
308 #define PSW_MASK_CC 0x0000300000000000ULL
309 #define PSW_MASK_PM 0x00000F0000000000ULL
310 #define PSW_SHIFT_MASK_PM 40
311 #define PSW_MASK_RI 0x0000008000000000ULL
312 #define PSW_MASK_64 0x0000000100000000ULL
313 #define PSW_MASK_32 0x0000000080000000ULL
314 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
315 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
316 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL
317
318 #undef PSW_ASC_PRIMARY
319 #undef PSW_ASC_ACCREG
320 #undef PSW_ASC_SECONDARY
321 #undef PSW_ASC_HOME
322
323 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
324 #define PSW_ASC_ACCREG 0x0000400000000000ULL
325 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
326 #define PSW_ASC_HOME 0x0000C00000000000ULL
327
328 /* the address space values shifted */
329 #define AS_PRIMARY 0
330 #define AS_ACCREG 1
331 #define AS_SECONDARY 2
332 #define AS_HOME 3
333
334 /* tb flags */
335
336 #define FLAG_MASK_PSW_SHIFT 31
337 #define FLAG_MASK_32 0x00000001u
338 #define FLAG_MASK_64 0x00000002u
339 #define FLAG_MASK_AFP 0x00000004u
340 #define FLAG_MASK_VECTOR 0x00000008u
341 #define FLAG_MASK_ASC 0x00018000u
342 #define FLAG_MASK_PSTATE 0x00020000u
343 #define FLAG_MASK_PER_IFETCH_NULLIFY 0x01000000u
344 #define FLAG_MASK_DAT 0x08000000u
345 #define FLAG_MASK_PER_STORE_REAL 0x20000000u
346 #define FLAG_MASK_PER_IFETCH 0x40000000u
347 #define FLAG_MASK_PER_BRANCH 0x80000000u
348
349 QEMU_BUILD_BUG_ON(FLAG_MASK_32 != PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT);
350 QEMU_BUILD_BUG_ON(FLAG_MASK_64 != PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT);
351 QEMU_BUILD_BUG_ON(FLAG_MASK_ASC != PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT);
352 QEMU_BUILD_BUG_ON(FLAG_MASK_PSTATE != PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT);
353 QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT);
354
355 #define FLAG_MASK_PSW (FLAG_MASK_DAT | FLAG_MASK_PSTATE | \
356 FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
357 #define FLAG_MASK_CR9 (FLAG_MASK_PER_BRANCH | FLAG_MASK_PER_IFETCH)
358 #define FLAG_MASK_PER (FLAG_MASK_PER_BRANCH | \
359 FLAG_MASK_PER_IFETCH | \
360 FLAG_MASK_PER_IFETCH_NULLIFY | \
361 FLAG_MASK_PER_STORE_REAL)
362
363 /* Control register 0 bits */
364 #define CR0_LOWPROT 0x0000000010000000ULL
365 #define CR0_SECONDARY 0x0000000004000000ULL
366 #define CR0_EDAT 0x0000000000800000ULL
367 #define CR0_AFP 0x0000000000040000ULL
368 #define CR0_VECTOR 0x0000000000020000ULL
369 #define CR0_IEP 0x0000000000100000ULL
370 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
371 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
372 #define CR0_CKC_SC 0x0000000000000800ULL
373 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
374 #define CR0_SERVICE_SC 0x0000000000000200ULL
375
376 /* Control register 14 bits */
377 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
378
379 /* MMU */
380 #define MMU_PRIMARY_IDX 0
381 #define MMU_SECONDARY_IDX 1
382 #define MMU_HOME_IDX 2
383 #define MMU_REAL_IDX 3
384
s390x_env_mmu_index(CPUS390XState * env,bool ifetch)385 static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
386 {
387 #ifdef CONFIG_USER_ONLY
388 return MMU_USER_IDX;
389 #else
390 if (!(env->psw.mask & PSW_MASK_DAT)) {
391 return MMU_REAL_IDX;
392 }
393
394 if (ifetch) {
395 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
396 return MMU_HOME_IDX;
397 }
398 return MMU_PRIMARY_IDX;
399 }
400
401 switch (env->psw.mask & PSW_MASK_ASC) {
402 case PSW_ASC_PRIMARY:
403 return MMU_PRIMARY_IDX;
404 case PSW_ASC_SECONDARY:
405 return MMU_SECONDARY_IDX;
406 case PSW_ASC_HOME:
407 return MMU_HOME_IDX;
408 case PSW_ASC_ACCREG:
409 /* Fallthrough: access register mode is not yet supported */
410 default:
411 abort();
412 }
413 #endif
414 }
415
416 #ifdef CONFIG_TCG
417
418 #include "tcg/tcg_s390x.h"
419
420 void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
421 uint64_t *cs_base, uint32_t *flags);
422
423 #endif /* CONFIG_TCG */
424
425 /* PER bits from control register 9 */
426 #define PER_CR9_EVENT_BRANCH 0x80000000
427 #define PER_CR9_EVENT_IFETCH 0x40000000
428 #define PER_CR9_EVENT_STORE 0x20000000
429 #define PER_CR9_EVENT_STORAGE_KEY_ALTERATION 0x10000000
430 #define PER_CR9_EVENT_STORE_REAL 0x08000000
431 #define PER_CR9_EVENT_ZERO_ADDRESS_DETECTION 0x04000000
432 #define PER_CR9_EVENT_TRANSACTION_END 0x02000000
433 #define PER_CR9_EVENT_IFETCH_NULLIFICATION 0x01000000
434 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
435 #define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000
436 #define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000
437
438 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_BRANCH != PER_CR9_EVENT_BRANCH);
439 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH != PER_CR9_EVENT_IFETCH);
440 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH_NULLIFY !=
441 PER_CR9_EVENT_IFETCH_NULLIFICATION);
442
443 /* PER bits from the PER CODE/ATMID/AI in lowcore */
444 #define PER_CODE_EVENT_BRANCH 0x8000
445 #define PER_CODE_EVENT_IFETCH 0x4000
446 #define PER_CODE_EVENT_STORE 0x2000
447 #define PER_CODE_EVENT_STORE_REAL 0x0800
448 #define PER_CODE_EVENT_NULLIFICATION 0x0100
449
450 #define EXCP_EXT 1 /* external interrupt */
451 #define EXCP_SVC 2 /* supervisor call (syscall) */
452 #define EXCP_PGM 3 /* program interruption */
453 #define EXCP_RESTART 4 /* restart interrupt */
454 #define EXCP_STOP 5 /* stop interrupt */
455 #define EXCP_IO 7 /* I/O interrupt */
456 #define EXCP_MCHK 8 /* machine check */
457
458 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
459 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
460 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
461 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
462 #define INTERRUPT_RESTART (1 << 7)
463 #define INTERRUPT_STOP (1 << 8)
464
465 /* Program Status Word. */
466 #define S390_PSWM_REGNUM 0
467 #define S390_PSWA_REGNUM 1
468 /* General Purpose Registers. */
469 #define S390_R0_REGNUM 2
470 #define S390_R1_REGNUM 3
471 #define S390_R2_REGNUM 4
472 #define S390_R3_REGNUM 5
473 #define S390_R4_REGNUM 6
474 #define S390_R5_REGNUM 7
475 #define S390_R6_REGNUM 8
476 #define S390_R7_REGNUM 9
477 #define S390_R8_REGNUM 10
478 #define S390_R9_REGNUM 11
479 #define S390_R10_REGNUM 12
480 #define S390_R11_REGNUM 13
481 #define S390_R12_REGNUM 14
482 #define S390_R13_REGNUM 15
483 #define S390_R14_REGNUM 16
484 #define S390_R15_REGNUM 17
485
setcc(S390CPU * cpu,uint64_t cc)486 static inline void setcc(S390CPU *cpu, uint64_t cc)
487 {
488 CPUS390XState *env = &cpu->env;
489
490 env->psw.mask &= ~(3ull << 44);
491 env->psw.mask |= (cc & 3) << 44;
492 env->cc_op = cc;
493 }
494
495 /* STSI */
496 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
497 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
498 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
499 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
500 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
501 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
502 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
503 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
504 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
505
506 /* Basic Machine Configuration */
507 typedef struct SysIB_111 {
508 uint8_t res1[32];
509 uint8_t manuf[16];
510 uint8_t type[4];
511 uint8_t res2[12];
512 uint8_t model[16];
513 uint8_t sequence[16];
514 uint8_t plant[4];
515 uint8_t res3[3996];
516 } SysIB_111;
517 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
518
519 /* Basic Machine CPU */
520 typedef struct SysIB_121 {
521 uint8_t res1[80];
522 uint8_t sequence[16];
523 uint8_t plant[4];
524 uint8_t res2[2];
525 uint16_t cpu_addr;
526 uint8_t res3[3992];
527 } SysIB_121;
528 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
529
530 /* Basic Machine CPUs */
531 typedef struct SysIB_122 {
532 uint8_t res1[32];
533 uint32_t capability;
534 uint16_t total_cpus;
535 uint16_t conf_cpus;
536 uint16_t standby_cpus;
537 uint16_t reserved_cpus;
538 uint16_t adjustments[2026];
539 } SysIB_122;
540 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
541
542 /* LPAR CPU */
543 typedef struct SysIB_221 {
544 uint8_t res1[80];
545 uint8_t sequence[16];
546 uint8_t plant[4];
547 uint16_t cpu_id;
548 uint16_t cpu_addr;
549 uint8_t res3[3992];
550 } SysIB_221;
551 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
552
553 /* LPAR CPUs */
554 typedef struct SysIB_222 {
555 uint8_t res1[32];
556 uint16_t lpar_num;
557 uint8_t res2;
558 uint8_t lcpuc;
559 uint16_t total_cpus;
560 uint16_t conf_cpus;
561 uint16_t standby_cpus;
562 uint16_t reserved_cpus;
563 uint8_t name[8];
564 uint32_t caf;
565 uint8_t res3[16];
566 uint16_t dedicated_cpus;
567 uint16_t shared_cpus;
568 uint8_t res4[4020];
569 } SysIB_222;
570 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
571
572 /* VM CPUs */
573 typedef struct SysIB_322 {
574 uint8_t res1[31];
575 uint8_t count;
576 struct {
577 uint8_t res2[4];
578 uint16_t total_cpus;
579 uint16_t conf_cpus;
580 uint16_t standby_cpus;
581 uint16_t reserved_cpus;
582 uint8_t name[8];
583 uint32_t caf;
584 uint8_t cpi[16];
585 uint8_t res5[3];
586 uint8_t ext_name_encoding;
587 uint32_t res3;
588 uint8_t uuid[16];
589 } vm[8];
590 uint8_t res4[1504];
591 uint8_t ext_names[8][256];
592 } SysIB_322;
593 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
594
595 /*
596 * Topology Magnitude fields (MAG) indicates the maximum number of
597 * topology list entries (TLE) at the corresponding nesting level.
598 */
599 #define S390_TOPOLOGY_MAG 6
600 #define S390_TOPOLOGY_MAG6 0
601 #define S390_TOPOLOGY_MAG5 1
602 #define S390_TOPOLOGY_MAG4 2
603 #define S390_TOPOLOGY_MAG3 3
604 #define S390_TOPOLOGY_MAG2 4
605 #define S390_TOPOLOGY_MAG1 5
606 /* Configuration topology */
607 typedef struct SysIB_151x {
608 uint8_t reserved0[2];
609 uint16_t length;
610 uint8_t mag[S390_TOPOLOGY_MAG];
611 uint8_t reserved1;
612 uint8_t mnest;
613 uint32_t reserved2;
614 char tle[];
615 } SysIB_151x;
616 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16);
617
618 typedef union SysIB {
619 SysIB_111 sysib_111;
620 SysIB_121 sysib_121;
621 SysIB_122 sysib_122;
622 SysIB_221 sysib_221;
623 SysIB_222 sysib_222;
624 SysIB_322 sysib_322;
625 SysIB_151x sysib_151x;
626 } SysIB;
627 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
628
629 /*
630 * CPU Topology List provided by STSI with fc=15 provides a list
631 * of two different Topology List Entries (TLE) types to specify
632 * the topology hierarchy.
633 *
634 * - Container Topology List Entry
635 * Defines a container to contain other Topology List Entries
636 * of any type, nested containers or CPU.
637 * - CPU Topology List Entry
638 * Specifies the CPUs position, type, entitlement and polarization
639 * of the CPUs contained in the last container TLE.
640 *
641 * There can be theoretically up to five levels of containers, QEMU
642 * uses only three levels, the drawer's, book's and socket's level.
643 *
644 * A container with a nesting level (NL) greater than 1 can only
645 * contain another container of nesting level NL-1.
646 *
647 * A container of nesting level 1 (socket), contains as many CPU TLE
648 * as needed to describe the position and qualities of all CPUs inside
649 * the container.
650 * The qualities of a CPU are polarization, entitlement and type.
651 *
652 * The CPU TLE defines the position of the CPUs of identical qualities
653 * using a 64bits mask which first bit has its offset defined by
654 * the CPU address origin field of the CPU TLE like in:
655 * CPU address = origin * 64 + bit position within the mask
656 */
657 /* Container type Topology List Entry */
658 typedef struct SYSIBContainerListEntry {
659 uint8_t nl;
660 uint8_t reserved[6];
661 uint8_t id;
662 } SYSIBContainerListEntry;
663 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry) != 8);
664
665 /* CPU type Topology List Entry */
666 typedef struct SysIBCPUListEntry {
667 uint8_t nl;
668 uint8_t reserved0[3];
669 #define SYSIB_TLE_POLARITY_MASK 0x03
670 #define SYSIB_TLE_DEDICATED 0x04
671 uint8_t flags;
672 uint8_t type;
673 uint16_t origin;
674 uint64_t mask;
675 } SysIBCPUListEntry;
676 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry) != 16);
677
678 void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra);
679 void s390_cpu_topology_set_changed(bool changed);
680
681 /* MMU defines */
682 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
683 #define ASCE_SUBSPACE 0x200 /* subspace group control */
684 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
685 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
686 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
687 #define ASCE_REAL_SPACE 0x20 /* real space control */
688 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
689 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
690 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
691 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
692 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
693 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
694
695 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
696 #define REGION_ENTRY_P 0x0000000000000200ULL
697 #define REGION_ENTRY_TF 0x00000000000000c0ULL
698 #define REGION_ENTRY_I 0x0000000000000020ULL
699 #define REGION_ENTRY_TT 0x000000000000000cULL
700 #define REGION_ENTRY_TL 0x0000000000000003ULL
701
702 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
703 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
704 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
705
706 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
707 #define REGION3_ENTRY_AV 0x0000000000010000ULL
708 #define REGION3_ENTRY_ACC 0x000000000000f000ULL
709 #define REGION3_ENTRY_F 0x0000000000000800ULL
710 #define REGION3_ENTRY_FC 0x0000000000000400ULL
711 #define REGION3_ENTRY_IEP 0x0000000000000100ULL
712 #define REGION3_ENTRY_CR 0x0000000000000010ULL
713
714 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
715 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
716 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL
717 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
718 #define SEGMENT_ENTRY_F 0x0000000000000800ULL
719 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL
720 #define SEGMENT_ENTRY_P 0x0000000000000200ULL
721 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
722 #define SEGMENT_ENTRY_I 0x0000000000000020ULL
723 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL
724 #define SEGMENT_ENTRY_TT 0x000000000000000cULL
725
726 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
727
728 #define PAGE_ENTRY_0 0x0000000000000800ULL
729 #define PAGE_ENTRY_I 0x0000000000000400ULL
730 #define PAGE_ENTRY_P 0x0000000000000200ULL
731 #define PAGE_ENTRY_IEP 0x0000000000000100ULL
732
733 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
734 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
735 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
736 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
737 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
738
739 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
740 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
741 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
742 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
743 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
744
745 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
746 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
747 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
748 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
749
750 #define SK_C (0x1 << 1)
751 #define SK_R (0x1 << 2)
752 #define SK_F (0x1 << 3)
753 #define SK_ACC_MASK (0xf << 4)
754
755 /* SIGP order codes */
756 #define SIGP_SENSE 0x01
757 #define SIGP_EXTERNAL_CALL 0x02
758 #define SIGP_EMERGENCY 0x03
759 #define SIGP_START 0x04
760 #define SIGP_STOP 0x05
761 #define SIGP_RESTART 0x06
762 #define SIGP_STOP_STORE_STATUS 0x09
763 #define SIGP_INITIAL_CPU_RESET 0x0b
764 #define SIGP_CPU_RESET 0x0c
765 #define SIGP_SET_PREFIX 0x0d
766 #define SIGP_STORE_STATUS_ADDR 0x0e
767 #define SIGP_SET_ARCH 0x12
768 #define SIGP_COND_EMERGENCY 0x13
769 #define SIGP_SENSE_RUNNING 0x15
770 #define SIGP_STORE_ADTL_STATUS 0x17
771
772 /* SIGP condition codes */
773 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
774 #define SIGP_CC_STATUS_STORED 1
775 #define SIGP_CC_BUSY 2
776 #define SIGP_CC_NOT_OPERATIONAL 3
777
778 /* SIGP status bits */
779 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
780 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
781 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
782 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
783 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
784 #define SIGP_STAT_STOPPED 0x00000040UL
785 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
786 #define SIGP_STAT_CHECK_STOP 0x00000010UL
787 #define SIGP_STAT_INOPERATIVE 0x00000004UL
788 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
789 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
790
791 /* SIGP order code mask corresponding to bit positions 56-63 */
792 #define SIGP_ORDER_MASK 0x000000ff
793
794 /* machine check interruption code */
795
796 /* subclasses */
797 #define MCIC_SC_SD 0x8000000000000000ULL
798 #define MCIC_SC_PD 0x4000000000000000ULL
799 #define MCIC_SC_SR 0x2000000000000000ULL
800 #define MCIC_SC_CD 0x0800000000000000ULL
801 #define MCIC_SC_ED 0x0400000000000000ULL
802 #define MCIC_SC_DG 0x0100000000000000ULL
803 #define MCIC_SC_W 0x0080000000000000ULL
804 #define MCIC_SC_CP 0x0040000000000000ULL
805 #define MCIC_SC_SP 0x0020000000000000ULL
806 #define MCIC_SC_CK 0x0010000000000000ULL
807
808 /* subclass modifiers */
809 #define MCIC_SCM_B 0x0002000000000000ULL
810 #define MCIC_SCM_DA 0x0000000020000000ULL
811 #define MCIC_SCM_AP 0x0000000000080000ULL
812
813 /* storage errors */
814 #define MCIC_SE_SE 0x0000800000000000ULL
815 #define MCIC_SE_SC 0x0000400000000000ULL
816 #define MCIC_SE_KE 0x0000200000000000ULL
817 #define MCIC_SE_DS 0x0000100000000000ULL
818 #define MCIC_SE_IE 0x0000000080000000ULL
819
820 /* validity bits */
821 #define MCIC_VB_WP 0x0000080000000000ULL
822 #define MCIC_VB_MS 0x0000040000000000ULL
823 #define MCIC_VB_PM 0x0000020000000000ULL
824 #define MCIC_VB_IA 0x0000010000000000ULL
825 #define MCIC_VB_FA 0x0000008000000000ULL
826 #define MCIC_VB_VR 0x0000004000000000ULL
827 #define MCIC_VB_EC 0x0000002000000000ULL
828 #define MCIC_VB_FP 0x0000001000000000ULL
829 #define MCIC_VB_GR 0x0000000800000000ULL
830 #define MCIC_VB_CR 0x0000000400000000ULL
831 #define MCIC_VB_ST 0x0000000100000000ULL
832 #define MCIC_VB_AR 0x0000000040000000ULL
833 #define MCIC_VB_GS 0x0000000008000000ULL
834 #define MCIC_VB_PR 0x0000000000200000ULL
835 #define MCIC_VB_FC 0x0000000000100000ULL
836 #define MCIC_VB_CT 0x0000000000020000ULL
837 #define MCIC_VB_CC 0x0000000000010000ULL
838
s390_build_validity_mcic(void)839 static inline uint64_t s390_build_validity_mcic(void)
840 {
841 uint64_t mcic;
842
843 /*
844 * Indicate all validity bits (no damage) only. Other bits have to be
845 * added by the caller. (storage errors, subclasses and subclass modifiers)
846 */
847 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
848 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
849 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
850 if (s390_has_feat(S390_FEAT_VECTOR)) {
851 mcic |= MCIC_VB_VR;
852 }
853 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
854 mcic |= MCIC_VB_GS;
855 }
856 return mcic;
857 }
858
s390_do_cpu_full_reset(CPUState * cs,run_on_cpu_data arg)859 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
860 {
861 cpu_reset(cs);
862 }
863
s390_do_cpu_reset(CPUState * cs,run_on_cpu_data arg)864 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
865 {
866 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_NORMAL);
867 }
868
s390_do_cpu_initial_reset(CPUState * cs,run_on_cpu_data arg)869 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
870 {
871 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_INITIAL);
872 }
873
s390_do_cpu_load_normal(CPUState * cs,run_on_cpu_data arg)874 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
875 {
876 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
877
878 scc->load_normal(cs);
879 }
880
881
882 /* cpu.c */
883 void s390_crypto_reset(void);
884 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
885 void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
886 void s390_cmma_reset(void);
887 void s390_enable_css_support(S390CPU *cpu);
888 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg);
889 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
890 int vq, bool assign);
891 #ifndef CONFIG_USER_ONLY
892 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
893 #else
s390_cpu_set_state(uint8_t cpu_state,S390CPU * cpu)894 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
895 {
896 return 0;
897 }
898 #endif /* CONFIG_USER_ONLY */
s390_cpu_get_state(S390CPU * cpu)899 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
900 {
901 return cpu->env.cpu_state;
902 }
903
904
905 /* cpu_models.c */
906 void s390_cpu_list(void);
907 #define cpu_list s390_cpu_list
908 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
909 const S390FeatInit feat_init);
910
911
912 /* helper.c */
913 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
914
915 /* interrupt.c */
916 #define RA_IGNORED 0
917 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
918 /* service interrupts are floating therefore we must not pass an cpustate */
919 void s390_sclp_extint(uint32_t parm);
920
921 /* mmu_helper.c */
922 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
923 int len, bool is_write);
924 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
925 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
926 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
927 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
928 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
929 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
930 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
931 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
932 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
933 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
934 int len, bool is_write);
935 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \
936 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
937 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \
938 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
939
940 /* sigp.c */
941 int s390_cpu_restart(S390CPU *cpu);
942 void s390_init_sigp(void);
943
944 /* helper.c */
945 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
946 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
947
948 /* outside of target/s390x/ */
949 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
950
951 #include "exec/cpu-all.h"
952
953 #endif
954