1 /* $OpenBSD: cache.c,v 1.5 2016/03/05 17:16:33 tobiasu Exp $ */
2 /* $NetBSD: cache.c,v 1.11 2006/01/02 23:37:34 uwe Exp $ */
3
4 /*-
5 * Copyright (c) 2002 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by UCHIYAMA Yasushi.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35
36 #include <sh/cache.h>
37 #include <sh/cache_sh3.h>
38 #include <sh/cache_sh4.h>
39
40 /*
41 * __cache_flush is used before sh_cache_config() is called.
42 */
43 static void __cache_flush(void);
44
45 struct sh_cache_ops sh_cache_ops = {
46 ._icache_sync_all = (void (*)(void))__cache_flush,
47 ._icache_sync_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
48 ._icache_sync_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
49 ._dcache_wbinv_all = (void (*)(void))__cache_flush,
50 ._dcache_wbinv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
51 ._dcache_wbinv_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
52 ._dcache_inv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
53 ._dcache_wb_range = (void (*)(vaddr_t, vsize_t))__cache_flush
54 };
55
56 int sh_cache_enable_icache;
57 int sh_cache_enable_dcache;
58 int sh_cache_write_through;
59 int sh_cache_write_through_p0_u0_p3;
60 int sh_cache_write_through_p1;
61 int sh_cache_unified;
62 int sh_cache_ways;
63 int sh_cache_size_icache;
64 int sh_cache_size_dcache;
65 int sh_cache_line_size;
66 int sh_cache_ram_mode;
67 int sh_cache_index_mode_icache;
68 int sh_cache_index_mode_dcache;
69 int sh_cache_prefer_mask;
70
71 void
sh_cache_init(void)72 sh_cache_init(void)
73 {
74 #ifdef CACHE_DEBUG
75 return;
76 #endif
77 #ifdef SH3
78 if (CPU_IS_SH3)
79 sh3_cache_config();
80 #endif
81 #ifdef SH4
82 if (CPU_IS_SH4)
83 sh4_cache_config();
84 #endif
85 }
86
87 void
sh_cache_information(void)88 sh_cache_information(void)
89 {
90 #ifdef CACHE_DEBUG
91 printf("*** USE CPU INDEPENDENT CACHE OPS. ***\n");
92 return;
93 #endif
94
95 /* I-cache or I/D-unified cache */
96 printf("cpu0: %dKB/%dB",
97 sh_cache_size_icache >> 10, sh_cache_line_size);
98 if (sh_cache_ways > 1)
99 printf(" %d-way associative", sh_cache_ways);
100 else
101 printf(" direct");
102 if (sh_cache_unified)
103 printf(" I/D-");
104 else
105 printf(" I-");
106 printf("cache");
107 if (!sh_cache_enable_icache)
108 printf(" DISABLED");
109 if (sh_cache_unified && sh_cache_ram_mode)
110 printf(" RAM-mode");
111 if (sh_cache_index_mode_icache)
112 printf(" INDEX-mode");
113
114 /* D-cache */
115 if (!sh_cache_unified) {
116 printf(", %dKB/%dB", sh_cache_size_dcache >> 10,
117 sh_cache_line_size);
118 if (sh_cache_ways > 1)
119 printf(" %d-way associative", sh_cache_ways);
120 else
121 printf(" direct");
122 printf(" D-cache");
123 if (!sh_cache_enable_dcache)
124 printf(" DISABLED");
125 if (sh_cache_ram_mode)
126 printf(" RAM-mode");
127 if (sh_cache_index_mode_dcache)
128 printf(" INDEX-mode");
129 }
130 printf("\n");
131
132 #ifdef CACHE_DEBUG
133 /* Write-through/back */
134 printf("cpu0: P0, U0, P3 write-%s; P1 write-%s\n",
135 sh_cache_write_through_p0_u0_p3 ? "through" : "back",
136 sh_cache_write_through_p1 ? "through" : "back");
137 #endif
138 }
139
140 /*
141 * CPU-independent cache flush.
142 */
143 void
__cache_flush(void)144 __cache_flush(void)
145 {
146 volatile int *p = (int *)SH3_PHYS_TO_P1SEG(IOM_RAM_BEGIN);
147 int i;
148 int d;
149
150 /* Flush D-Cache */
151 /*
152 * Access address range [13:4].
153 * max:
154 * 16KB line-size 16B 4-way ... [11:4] * 4
155 * 16KB line-size 32B 1-way ... [13:5]
156 */
157 for (i = 0; i < 256/*entry*/ * 4/*way*/; i++) {
158 d = *p;
159 p += 4; /* next line index (16B) */
160 }
161
162 /* Flush I-Cache */
163 /*
164 * this code flush I-cache. but can't compile..
165 * __asm volatile(".space 8192");
166 *
167 */
168 }
169