1 /* 2 * Copyright (c) 2007-2013 Michael Mondy 3 * Copyright (c) 2012-2016 Harry Reed 4 * Copyright (c) 2013-2016 Charles Anthony 5 * Copyright (c) 2021 The DPS8M Development Team 6 * 7 * All rights reserved. 8 * 9 * This software is made available under the terms of the ICU 10 * License, version 1.8.1 or later. For more details, see the 11 * LICENSE.md file at the top-level directory of this distribution. 12 */ 13 14 extern DEVICE scu_dev; 15 16 #ifdef SPEED 17 # define if_sim_debug(dbits, dptr) if ((0)) 18 #else 19 # define if_sim_debug(dbits, dptr) \ 20 if ( \ 21 sim_deb && \ 22 (((dptr)->dctrl & (dbits)) || (dbits) == 0) && \ 23 ((dptr != & cpu_dev) || ((1 << current_running_cpu_idx) & dbgCPUMask)) && \ 24 ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ 25 ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ 26 ((dptr != & cpu_dev) || (! sim_deb_bar) || (! TST_I_NBAR)) && \ 27 cpu.cycleCnt >= sim_deb_start && \ 28 (sim_deb_stop == 0 || cpu.cycleCnt < sim_deb_stop) && \ 29 (sim_deb_mme_cntdwn == 0) && \ 30 ((dptr != & cpu_dev) | (((dbits) & DBG_TRACE) ? (sim_deb_skip_cnt ++ >= sim_deb_skip_limit) : (sim_deb_skip_cnt >= sim_deb_skip_limit))) \ 31 ) 32 #endif 33 34 #if !defined(THREADZ) && !defined(LOCKLESS) 35 # define dps8_sim_debug _sim_debug 36 #endif 37 38 #undef sim_debug 39 #if defined(THREADZ) || defined(LOCKLESS) 40 # define sim_debug(dbits, dptr, ...) \ 41 if_sim_debug((dbits), dptr) \ 42 dps8_sim_debug ((dbits), dptr, DBG_CTR, __VA_ARGS__); \ 43 else \ 44 (void) 0 45 #else 46 # define sim_debug(dbits, dptr, ...) \ 47 if_sim_debug((dbits), dptr) \ 48 dps8_sim_debug ((dbits), dptr, __VA_ARGS__); \ 49 else \ 50 (void) 0 51 #endif 52 53 /* scp Debug flags */ 54 55 #define DBG_TRACE (1U << 0) ///< instruction trace 56 #define DBG_MSG (1U << 1) ///< misc output 57 58 #define DBG_REGDUMPAQI (1U << 2) ///< A/Q/IR register dump 59 #define DBG_REGDUMPIDX (1U << 3) ///< index register dump 60 #define DBG_REGDUMPPR (1U << 4) ///< pointer registers dump 61 //#define DBG_REGDUMPADR (1U << 5) ///< address registers dump 62 #define DBG_REGDUMPPPR (1U << 6) ///< PPR register dump 63 #define DBG_REGDUMPDSBR (1U << 7) ///< descritptor segment base register dump 64 #define DBG_REGDUMPFLT (1U << 8) ///< C(EAQ) floating-point register dump 65 66 //#define DBG_REGDUMP (DBG_REGDUMPAQI | DBG_REGDUMPIDX | DBG_REGDUMPPR | 67 // DBG_REGDUMPADR | DBG_REGDUMPPPR | DBG_REGDUMPDSBR | DBG_REGDUMPFLT) 68 #define DBG_REGDUMP (DBG_REGDUMPAQI | DBG_REGDUMPIDX | DBG_REGDUMPPR | \ 69 DBG_REGDUMPPPR | DBG_REGDUMPDSBR | DBG_REGDUMPFLT) 70 71 #define DBG_ADDRMOD (1U << 9) ///< follow address modifications 72 #define DBG_APPENDING (1U << 10) ///< follow appending unit operations 73 #define DBG_TRACEEXT (1U << 11) ///< extended instruction trace 74 #define DBG_WARN (1U << 12) 75 #define DBG_DEBUG (1U << 13) 76 #define DBG_INFO (1U << 14) 77 #define DBG_NOTIFY (1U << 15) 78 #define DBG_SIM_USES_16 (1U << 16) 79 #define DBG_SIM_USES_17 (1U << 17) 80 #define DBG_SIM_USES_18 (1U << 18) 81 #define DBG_ERR (1U << 19) 82 #define DBG_ALL (DBG_NOTIFY | DBG_INFO | DBG_ERR | DBG_DEBUG | DBG_WARN | \ 83 DBG_ERR | DBG_TRACE ) 84 #define DBG_FAULT (1U << 20) ///< follow fault handling 85 #define DBG_INTR (1U << 21) // follow interrupt handling 86 #define DBG_CORE (1U << 22) 87 #define DBG_CYCLE (1U << 23) 88 #define DBG_CAC (1U << 24) 89 #define DBG_FINAL (1U << 25) 90 #define DBG_AVC (1U << 26) 91 92 // Abort codes, used to sort out longjmp's back to the main loop. 93 // Codes > 0 are simulator stop codes 94 // Codes < 0 are internal aborts 95 // Code = 0 stops execution for an interrupt check (XXX Don't know if I like 96 // this or not) 97 // XXX above is not entirely correct (anymore). 98 99 100 //#define SCPE_OK 0 101 #define STOP_STOP 1 102 #define STOP_BKPT 2 103 104 105 // not really STOP codes, but get returned from instruction loops 106 #define CONT_TRA -1 // encountered a transfer instruction; don't bump PPR.IC 107 #define CONT_DIS -2 // instruction was a DIS 108 #define CONT_XEC -3 // instruction was a XEC or XED 109 #define CONT_RET -5 // encountered a return instruction; don't bump PPR.IC, 110 // do instruction fetch 111 112 // 113 // mask entry flags 114 // MTAB_XTD extended entry 115 // MTAB_VDV valid for devices 116 // MTAB_VUN valid for units 117 // MTAB_VALO takes a value (optional) 118 // MTAB_VALR takes a value (required) 119 // MTAB_NMO valid only in named SHOW 120 // MTAB_NC do not convert option value to upper case 121 // MTAB_SHP SHOW parameter takes optional value 122 123 // Requires a value, DEV and DEVn both work, not in "show" 124 #define MTAB_unit_value MTAB_XTD | MTAB_VUN | MTAB_VDV | MTAB_NMO | MTAB_VALR 125 // Requires a value, DEVn, not in "show" 126 #define MTAB_unitonly_value MTAB_XTD | MTAB_VUN | MTAB_NMO | MTAB_VALR 127 // Requires a value, DEV and DEVn both work, in "show" 128 #define MTAB_unit_value_show MTAB_XTD | MTAB_VUN | MTAB_VDV | MTAB_VALR 129 // Requires a value, DEV only, not in "show", uppercase value 130 #define MTAB_dev_valr_noshow MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_VALR 131 // Requires a value, DEV only, not in "show", don't uppercase value 132 #define MTAB_dev_valr_nouc MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_VALR | MTAB_NC 133 // Requires a value, DEV only, not in "show" 134 #define MTAB_dev_value MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_VALR 135 // No value, DEV only, in "show" 136 #define MTAB_dev_novalue MTAB_XTD | MTAB_VDV 137 // Requires a value, DEVn only, in "show", don't uppercase value 138 #define MTAB_unit_valr_nouc MTAB_XTD | MTAB_VUN | MTAB_VALR | MTAB_NC 139 // Value optional, DEVn only, do not uppercase value 140 #define MTAB_unit_nouc MTAB_XTD | MTAB_VUN | MTAB_NC 141 // Value optional, DEVn only, uppercase value 142 #define MTAB_unit_uc MTAB_XTD | MTAB_VUN 143 // Value required, DEV only 144 #define MTAB_dev_valr MTAB_XTD | MTAB_VDV | MTAB_VALR 145 // End of list marker 146 #define MTAB_eol { 0, 0, NULL, NULL, 0, 0, NULL, NULL } 147 148 extern uint32 sim_brk_summ, sim_brk_types, sim_brk_dflt; 149 extern FILE *sim_deb; 150 void sim_printf( const char * format, ... ) // not really simh, by my impl 151 #ifdef __GNUC__ 152 __attribute__ ((format (printf, 1, 2))) 153 #endif 154 ; 155 156 #if defined(THREADZ) || defined(LOCKLESS) 157 void dps8_sim_debug (uint32 dbits, DEVICE* dptr, unsigned long long cnt, const char* fmt, ...) 158 # ifdef __GNUC__ 159 __attribute__ ((format (printf, 4, 5))) 160 # endif 161 ; 162 #endif 163 #define sim_fatal(format, ...) { _sim_err (format, ##__VA_ARGS__); exit (1); } 164 #define sim_msg sim_printf 165 #define sim_warn sim_printf 166 #define sim_print sim_printf 167