1 /*
2 * Emulated CXL Switch Upstream Port
3 *
4 * Copyright (c) 2022 Huawei Technologies.
5 *
6 * Based on xio3130_upstream.c
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "qemu/log.h"
13 #include "hw/qdev-properties.h"
14 #include "hw/qdev-properties-system.h"
15 #include "hw/pci/msi.h"
16 #include "hw/pci/pcie.h"
17 #include "hw/pci/pcie_port.h"
18 #include "hw/pci-bridge/cxl_upstream_port.h"
19 /*
20 * Null value of all Fs suggested by IEEE RA guidelines for use of
21 * EU, OUI and CID
22 */
23 #define UI64_NULL (~0ULL)
24
25 #define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2
26
27 #define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70
28 #define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90
29 #define CXL_UPSTREAM_PORT_AER_OFFSET 0x100
30 #define CXL_UPSTREAM_PORT_SN_OFFSET \
31 (CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
32 #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
33 (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF)
34
cxl_usp_to_cstate(CXLUpstreamPort * usp)35 CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
36 {
37 return &usp->cxl_cstate;
38 }
39
cxl_usp_dvsec_write_config(PCIDevice * dev,uint32_t addr,uint32_t val,int len)40 static void cxl_usp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
41 uint32_t val, int len)
42 {
43 CXLUpstreamPort *usp = CXL_USP(dev);
44
45 if (range_contains(&usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
46 uint8_t *reg = &dev->config[addr];
47 addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;
48 if (addr == PORT_CONTROL_OFFSET) {
49 if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
50 /* unmask SBR */
51 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
52 }
53 if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
54 /* Alt Memory & ID Space Enable */
55 qemu_log_mask(LOG_UNIMP,
56 "Alt Memory & ID space is not supported\n");
57 }
58 }
59 }
60 }
61
cxl_usp_write_config(PCIDevice * d,uint32_t address,uint32_t val,int len)62 static void cxl_usp_write_config(PCIDevice *d, uint32_t address,
63 uint32_t val, int len)
64 {
65 CXLUpstreamPort *usp = CXL_USP(d);
66
67 pcie_doe_write_config(&usp->doe_cdat, address, val, len);
68 pci_bridge_write_config(d, address, val, len);
69 pcie_cap_flr_write_config(d, address, val, len);
70 pcie_aer_write_config(d, address, val, len);
71
72 cxl_usp_dvsec_write_config(d, address, val, len);
73 }
74
cxl_usp_read_config(PCIDevice * d,uint32_t address,int len)75 static uint32_t cxl_usp_read_config(PCIDevice *d, uint32_t address, int len)
76 {
77 CXLUpstreamPort *usp = CXL_USP(d);
78 uint32_t val;
79
80 if (pcie_doe_read_config(&usp->doe_cdat, address, len, &val)) {
81 return val;
82 }
83
84 return pci_default_read_config(d, address, len);
85 }
86
latch_registers(CXLUpstreamPort * usp)87 static void latch_registers(CXLUpstreamPort *usp)
88 {
89 uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers;
90 uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask;
91
92 cxl_component_register_init_common(reg_state, write_msk,
93 CXL2_UPSTREAM_PORT);
94 ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8);
95 }
96
cxl_usp_reset(DeviceState * qdev)97 static void cxl_usp_reset(DeviceState *qdev)
98 {
99 PCIDevice *d = PCI_DEVICE(qdev);
100 CXLUpstreamPort *usp = CXL_USP(qdev);
101
102 pci_bridge_reset(qdev);
103 pcie_cap_deverr_reset(d);
104 pcie_cap_fill_link_ep_usp(d, usp->width, usp->speed);
105 latch_registers(usp);
106 }
107
build_dvsecs(CXLComponentState * cxl)108 static void build_dvsecs(CXLComponentState *cxl)
109 {
110 uint8_t *dvsec;
111
112 dvsec = (uint8_t *)&(CXLDVSECPortExt){
113 .status = 0x1, /* Port Power Management Init Complete */
114 };
115 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
116 EXTENSIONS_PORT_DVSEC_LENGTH,
117 EXTENSIONS_PORT_DVSEC,
118 EXTENSIONS_PORT_DVSEC_REVID, dvsec);
119 dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
120 .cap = 0x27, /* Cache, IO, Mem, non-MLD */
121 .ctrl = 0x27, /* Cache, IO, Mem */
122 .status = 0x26, /* same */
123 .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */
124 };
125 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
126 PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH,
127 PCIE_FLEXBUS_PORT_DVSEC,
128 PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID, dvsec);
129
130 dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
131 .rsvd = 0,
132 .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
133 .reg0_base_hi = 0,
134 };
135 cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
136 REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
137 REG_LOC_DVSEC_REVID, dvsec);
138 }
139
cxl_doe_cdat_rsp(DOECap * doe_cap)140 static bool cxl_doe_cdat_rsp(DOECap *doe_cap)
141 {
142 CDATObject *cdat = &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat;
143 uint16_t ent;
144 void *base;
145 uint32_t len;
146 CDATReq *req = pcie_doe_get_write_mbox_ptr(doe_cap);
147 CDATRsp rsp;
148
149 cxl_doe_cdat_update(&CXL_USP(doe_cap->pdev)->cxl_cstate, &error_fatal);
150 assert(cdat->entry_len);
151
152 /* Discard if request length mismatched */
153 if (pcie_doe_get_obj_len(req) <
154 DIV_ROUND_UP(sizeof(CDATReq), sizeof(uint32_t))) {
155 return false;
156 }
157
158 ent = req->entry_handle;
159 base = cdat->entry[ent].base;
160 len = cdat->entry[ent].length;
161
162 rsp = (CDATRsp) {
163 .header = {
164 .vendor_id = CXL_VENDOR_ID,
165 .data_obj_type = CXL_DOE_TABLE_ACCESS,
166 .reserved = 0x0,
167 .length = DIV_ROUND_UP((sizeof(rsp) + len), sizeof(uint32_t)),
168 },
169 .rsp_code = CXL_DOE_TAB_RSP,
170 .table_type = CXL_DOE_TAB_TYPE_CDAT,
171 .entry_handle = (ent < cdat->entry_len - 1) ?
172 ent + 1 : CXL_DOE_TAB_ENT_MAX,
173 };
174
175 memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp));
176 memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), sizeof(uint32_t)),
177 base, len);
178
179 doe_cap->read_mbox_len += rsp.header.length;
180
181 return true;
182 }
183
184 static DOEProtocol doe_cdat_prot[] = {
185 { CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp },
186 { }
187 };
188
189 enum {
190 CXL_USP_CDAT_SSLBIS_LAT,
191 CXL_USP_CDAT_SSLBIS_BW,
192 CXL_USP_CDAT_NUM_ENTRIES
193 };
194
build_cdat_table(CDATSubHeader *** cdat_table,void * priv)195 static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
196 {
197 CDATSslbis *sslbis_latency;
198 CDATSslbis *sslbis_bandwidth;
199 CXLUpstreamPort *us = CXL_USP(priv);
200 PCIBus *bus = &PCI_BRIDGE(us)->sec_bus;
201 int devfn, sslbis_size, i;
202 int count = 0;
203 uint16_t port_ids[256];
204
205 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
206 PCIDevice *d = bus->devices[devfn];
207 PCIEPort *port;
208
209 if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
210 continue;
211 }
212
213 /*
214 * Whilst the PCI express spec doesn't allow anything other than
215 * downstream ports on this bus, let us be a little paranoid
216 */
217 if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
218 continue;
219 }
220
221 port = PCIE_PORT(d);
222 port_ids[count] = port->port;
223 count++;
224 }
225
226 /* May not yet have any ports - try again later */
227 if (count == 0) {
228 return 0;
229 }
230
231 sslbis_size = sizeof(CDATSslbis) + sizeof(*sslbis_latency->sslbe) * count;
232 sslbis_latency = g_malloc(sslbis_size);
233 *sslbis_latency = (CDATSslbis) {
234 .sslbis_header = {
235 .header = {
236 .type = CDAT_TYPE_SSLBIS,
237 .length = sslbis_size,
238 },
239 .data_type = HMAT_LB_DATA_TYPE_ACCESS_LATENCY,
240 .entry_base_unit = 10000,
241 },
242 };
243
244 for (i = 0; i < count; i++) {
245 sslbis_latency->sslbe[i] = (CDATSslbe) {
246 .port_x_id = CDAT_PORT_ID_USP,
247 .port_y_id = port_ids[i],
248 .latency_bandwidth = 15, /* 150ns */
249 };
250 }
251
252 sslbis_bandwidth = g_malloc(sslbis_size);
253 *sslbis_bandwidth = (CDATSslbis) {
254 .sslbis_header = {
255 .header = {
256 .type = CDAT_TYPE_SSLBIS,
257 .length = sslbis_size,
258 },
259 .data_type = HMAT_LB_DATA_TYPE_ACCESS_BANDWIDTH,
260 .entry_base_unit = 1024,
261 },
262 };
263
264 for (i = 0; i < count; i++) {
265 sslbis_bandwidth->sslbe[i] = (CDATSslbe) {
266 .port_x_id = CDAT_PORT_ID_USP,
267 .port_y_id = port_ids[i],
268 .latency_bandwidth = 16, /* 16 GB/s */
269 };
270 }
271
272 *cdat_table = g_new0(CDATSubHeader *, CXL_USP_CDAT_NUM_ENTRIES);
273
274 /* Header always at start of structure */
275 (*cdat_table)[CXL_USP_CDAT_SSLBIS_LAT] = (CDATSubHeader *)sslbis_latency;
276 (*cdat_table)[CXL_USP_CDAT_SSLBIS_BW] = (CDATSubHeader *)sslbis_bandwidth;
277
278 return CXL_USP_CDAT_NUM_ENTRIES;
279 }
280
free_default_cdat_table(CDATSubHeader ** cdat_table,int num,void * priv)281 static void free_default_cdat_table(CDATSubHeader **cdat_table, int num,
282 void *priv)
283 {
284 int i;
285
286 for (i = 0; i < num; i++) {
287 g_free(cdat_table[i]);
288 }
289 g_free(cdat_table);
290 }
291
cxl_usp_realize(PCIDevice * d,Error ** errp)292 static void cxl_usp_realize(PCIDevice *d, Error **errp)
293 {
294 ERRP_GUARD();
295 PCIEPort *p = PCIE_PORT(d);
296 CXLUpstreamPort *usp = CXL_USP(d);
297 CXLComponentState *cxl_cstate = &usp->cxl_cstate;
298 ComponentRegisters *cregs = &cxl_cstate->crb;
299 MemoryRegion *component_bar = &cregs->component_registers;
300 int rc;
301
302 pci_bridge_initfn(d, TYPE_PCIE_BUS);
303 pcie_port_init_reg(d);
304
305 rc = msi_init(d, CXL_UPSTREAM_PORT_MSI_OFFSET,
306 CXL_UPSTREAM_PORT_MSI_NR_VECTOR, true, true, errp);
307 if (rc) {
308 assert(rc == -ENOTSUP);
309 goto err_bridge;
310 }
311
312 rc = pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET,
313 PCI_EXP_TYPE_UPSTREAM, p->port, errp);
314 if (rc < 0) {
315 goto err_msi;
316 }
317
318 pcie_cap_flr_init(d);
319 pcie_cap_deverr_init(d);
320 rc = pcie_aer_init(d, PCI_ERR_VER, CXL_UPSTREAM_PORT_AER_OFFSET,
321 PCI_ERR_SIZEOF, errp);
322 if (rc) {
323 goto err_cap;
324 }
325 if (usp->sn != UI64_NULL) {
326 pcie_dev_ser_num_init(d, CXL_UPSTREAM_PORT_SN_OFFSET, usp->sn);
327 }
328 cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;
329 cxl_cstate->pdev = d;
330 build_dvsecs(cxl_cstate);
331 cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_USP);
332 pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX,
333 PCI_BASE_ADDRESS_SPACE_MEMORY |
334 PCI_BASE_ADDRESS_MEM_TYPE_64,
335 component_bar);
336
337 pcie_doe_init(d, &usp->doe_cdat, cxl_cstate->dvsec_offset, doe_cdat_prot,
338 true, 1);
339
340 cxl_cstate->cdat.build_cdat_table = build_cdat_table;
341 cxl_cstate->cdat.free_cdat_table = free_default_cdat_table;
342 cxl_cstate->cdat.private = d;
343 if (!cxl_doe_cdat_init(cxl_cstate, errp)) {
344 goto err_cap;
345 }
346
347 return;
348
349 err_cap:
350 pcie_cap_exit(d);
351 err_msi:
352 msi_uninit(d);
353 err_bridge:
354 pci_bridge_exitfn(d);
355 }
356
cxl_usp_exitfn(PCIDevice * d)357 static void cxl_usp_exitfn(PCIDevice *d)
358 {
359 pcie_aer_exit(d);
360 pcie_cap_exit(d);
361 msi_uninit(d);
362 pci_bridge_exitfn(d);
363 }
364
365 static Property cxl_upstream_props[] = {
366 DEFINE_PROP_UINT64("sn", CXLUpstreamPort, sn, UI64_NULL),
367 DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename),
368 DEFINE_PROP_PCIE_LINK_SPEED("x-speed", CXLUpstreamPort,
369 speed, PCIE_LINK_SPEED_32),
370 DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort,
371 width, PCIE_LINK_WIDTH_16),
372 DEFINE_PROP_END_OF_LIST()
373 };
374
cxl_upstream_class_init(ObjectClass * oc,void * data)375 static void cxl_upstream_class_init(ObjectClass *oc, void *data)
376 {
377 DeviceClass *dc = DEVICE_CLASS(oc);
378 PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
379
380 k->config_write = cxl_usp_write_config;
381 k->config_read = cxl_usp_read_config;
382 k->realize = cxl_usp_realize;
383 k->exit = cxl_usp_exitfn;
384 k->vendor_id = 0x19e5; /* Huawei */
385 k->device_id = 0xa128; /* Emulated CXL Switch Upstream Port */
386 k->revision = 0;
387 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
388 dc->desc = "CXL Switch Upstream Port";
389 device_class_set_legacy_reset(dc, cxl_usp_reset);
390 device_class_set_props(dc, cxl_upstream_props);
391 }
392
393 static const TypeInfo cxl_usp_info = {
394 .name = TYPE_CXL_USP,
395 .parent = TYPE_PCIE_PORT,
396 .instance_size = sizeof(CXLUpstreamPort),
397 .class_init = cxl_upstream_class_init,
398 .interfaces = (InterfaceInfo[]) {
399 { INTERFACE_PCIE_DEVICE },
400 { INTERFACE_CXL_DEVICE },
401 { }
402 },
403 };
404
cxl_usp_register_type(void)405 static void cxl_usp_register_type(void)
406 {
407 type_register_static(&cxl_usp_info);
408 }
409
410 type_init(cxl_usp_register_type);
411