1 /*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/conf.h>
31 #include <sys/ioccom.h>
32 #include <sys/kernel.h>
33 #include <sys/lock.h>
34 #include <sys/malloc.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/rman.h>
38 #include <sys/sysctl.h>
39 #include <dev/pci/pcireg.h>
40 #include <dev/pci/pcivar.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/stdarg.h>
44 #include <vm/vm.h>
45 #include <vm/vm_param.h>
46 #include <vm/pmap.h>
47
48 #include "ioat.h"
49 #include "ioat_hw.h"
50 #include "ioat_internal.h"
51 #include "ioat_test.h"
52
53 #ifndef time_after
54 #define time_after(a,b) ((long)(b) - (long)(a) < 0)
55 #endif
56
57 MALLOC_DEFINE(M_IOAT_TEST, "ioat_test", "ioat test allocations");
58
59 #define IOAT_MAX_BUFS 256
60
61 struct test_transaction {
62 void *buf[IOAT_MAX_BUFS];
63 uint32_t length;
64 uint32_t depth;
65 uint32_t crc[IOAT_MAX_BUFS];
66 struct ioat_test *test;
67 TAILQ_ENTRY(test_transaction) entry;
68 };
69
70 #define IT_LOCK() mtx_lock(&ioat_test_lk)
71 #define IT_UNLOCK() mtx_unlock(&ioat_test_lk)
72 #define IT_ASSERT() mtx_assert(&ioat_test_lk, MA_OWNED)
73 static struct mtx ioat_test_lk;
74 MTX_SYSINIT(ioat_test_lk, &ioat_test_lk, "test coordination mtx", MTX_DEF);
75
76 static int g_thread_index = 1;
77 static struct cdev *g_ioat_cdev = NULL;
78
79 #define ioat_test_log(v, ...) _ioat_test_log((v), "ioat_test: " __VA_ARGS__)
80 static void _ioat_test_log(int verbosity, const char *fmt, ...);
81
82 static void
ioat_test_transaction_destroy(struct test_transaction * tx)83 ioat_test_transaction_destroy(struct test_transaction *tx)
84 {
85 int i;
86
87 for (i = 0; i < IOAT_MAX_BUFS; i++) {
88 if (tx->buf[i] != NULL) {
89 free(tx->buf[i], M_IOAT_TEST);
90 tx->buf[i] = NULL;
91 }
92 }
93
94 free(tx, M_IOAT_TEST);
95 }
96
97 static struct
ioat_test_transaction_create(struct ioat_test * test,unsigned num_buffers)98 test_transaction *ioat_test_transaction_create(struct ioat_test *test,
99 unsigned num_buffers)
100 {
101 struct test_transaction *tx;
102 unsigned i;
103
104 tx = malloc(sizeof(*tx), M_IOAT_TEST, M_NOWAIT | M_ZERO);
105 if (tx == NULL)
106 return (NULL);
107
108 tx->length = test->buffer_size;
109
110 for (i = 0; i < num_buffers; i++) {
111 if (test->testkind == IOAT_TEST_DMA_8K)
112 tx->buf[i] = malloc(test->buffer_size, M_IOAT_TEST,
113 M_NOWAIT);
114 else
115 tx->buf[i] = contigmalloc(test->buffer_size,
116 M_IOAT_TEST, M_NOWAIT, 0, BUS_SPACE_MAXADDR,
117 PAGE_SIZE, 0);
118
119 if (tx->buf[i] == NULL) {
120 ioat_test_transaction_destroy(tx);
121 return (NULL);
122 }
123 }
124 return (tx);
125 }
126
127 static void
dump_hex(void * p,size_t chunks)128 dump_hex(void *p, size_t chunks)
129 {
130 size_t i, j;
131
132 for (i = 0; i < chunks; i++) {
133 for (j = 0; j < 8; j++)
134 printf("%08x ", ((uint32_t *)p)[i * 8 + j]);
135 printf("\n");
136 }
137 }
138
139 static bool
ioat_compare_ok(struct test_transaction * tx)140 ioat_compare_ok(struct test_transaction *tx)
141 {
142 struct ioat_test *test;
143 char *dst, *src;
144 uint32_t i, j;
145
146 test = tx->test;
147
148 for (i = 0; i < tx->depth; i++) {
149 dst = tx->buf[2 * i + 1];
150 src = tx->buf[2 * i];
151
152 if (test->testkind == IOAT_TEST_FILL) {
153 for (j = 0; j < tx->length; j += sizeof(uint64_t)) {
154 if (memcmp(src, &dst[j],
155 MIN(sizeof(uint64_t), tx->length - j))
156 != 0)
157 return (false);
158 }
159 } else if (test->testkind == IOAT_TEST_DMA) {
160 if (memcmp(src, dst, tx->length) != 0)
161 return (false);
162 } else if (test->testkind == IOAT_TEST_RAW_DMA) {
163 if (test->raw_write)
164 dst = test->raw_vtarget;
165 dump_hex(dst, tx->length / 32);
166 }
167 }
168 return (true);
169 }
170
171 static void
ioat_dma_test_callback(void * arg,int error)172 ioat_dma_test_callback(void *arg, int error)
173 {
174 struct test_transaction *tx;
175 struct ioat_test *test;
176
177 if (error != 0)
178 ioat_test_log(0, "%s: Got error: %d\n", __func__, error);
179
180 tx = arg;
181 test = tx->test;
182
183 if (test->verify && !ioat_compare_ok(tx)) {
184 ioat_test_log(0, "miscompare found\n");
185 atomic_add_32(&test->status[IOAT_TEST_MISCOMPARE], tx->depth);
186 } else if (!test->too_late)
187 atomic_add_32(&test->status[IOAT_TEST_OK], tx->depth);
188
189 IT_LOCK();
190 TAILQ_REMOVE(&test->pend_q, tx, entry);
191 TAILQ_INSERT_TAIL(&test->free_q, tx, entry);
192 wakeup(&test->free_q);
193 IT_UNLOCK();
194 }
195
196 static int
ioat_test_prealloc_memory(struct ioat_test * test,int index)197 ioat_test_prealloc_memory(struct ioat_test *test, int index)
198 {
199 uint32_t i, j, k;
200 struct test_transaction *tx;
201
202 for (i = 0; i < test->transactions; i++) {
203 tx = ioat_test_transaction_create(test, test->chain_depth * 2);
204 if (tx == NULL) {
205 ioat_test_log(0, "tx == NULL - memory exhausted\n");
206 test->status[IOAT_TEST_NO_MEMORY]++;
207 return (ENOMEM);
208 }
209
210 TAILQ_INSERT_HEAD(&test->free_q, tx, entry);
211
212 tx->test = test;
213 tx->depth = test->chain_depth;
214
215 /* fill in source buffers */
216 for (j = 0; j < (tx->length / sizeof(uint32_t)); j++) {
217 uint32_t val = j + (index << 28);
218
219 for (k = 0; k < test->chain_depth; k++) {
220 ((uint32_t *)tx->buf[2*k])[j] = ~val;
221 ((uint32_t *)tx->buf[2*k+1])[j] = val;
222 }
223 }
224 }
225 return (0);
226 }
227
228 static void
ioat_test_release_memory(struct ioat_test * test)229 ioat_test_release_memory(struct ioat_test *test)
230 {
231 struct test_transaction *tx, *s;
232
233 TAILQ_FOREACH_SAFE(tx, &test->free_q, entry, s)
234 ioat_test_transaction_destroy(tx);
235 TAILQ_INIT(&test->free_q);
236
237 TAILQ_FOREACH_SAFE(tx, &test->pend_q, entry, s)
238 ioat_test_transaction_destroy(tx);
239 TAILQ_INIT(&test->pend_q);
240 }
241
242 static void
ioat_test_submit_1_tx(struct ioat_test * test,bus_dmaengine_t dma)243 ioat_test_submit_1_tx(struct ioat_test *test, bus_dmaengine_t dma)
244 {
245 struct test_transaction *tx;
246 struct bus_dmadesc *desc;
247 bus_dmaengine_callback_t cb;
248 bus_addr_t src, dest;
249 uint64_t fillpattern;
250 uint32_t i, flags;
251
252 desc = NULL;
253
254 IT_LOCK();
255 while (TAILQ_EMPTY(&test->free_q))
256 msleep(&test->free_q, &ioat_test_lk, 0, "test_submit", 0);
257
258 tx = TAILQ_FIRST(&test->free_q);
259 TAILQ_REMOVE(&test->free_q, tx, entry);
260 TAILQ_INSERT_HEAD(&test->pend_q, tx, entry);
261 IT_UNLOCK();
262
263 if (test->testkind != IOAT_TEST_MEMCPY)
264 ioat_acquire(dma);
265 for (i = 0; i < tx->depth; i++) {
266 if (test->testkind == IOAT_TEST_MEMCPY) {
267 memcpy(tx->buf[2 * i + 1], tx->buf[2 * i], tx->length);
268 if (i == tx->depth - 1)
269 ioat_dma_test_callback(tx, 0);
270 continue;
271 }
272
273 src = vtophys((vm_offset_t)tx->buf[2*i]);
274 dest = vtophys((vm_offset_t)tx->buf[2*i+1]);
275
276 if (test->testkind == IOAT_TEST_RAW_DMA) {
277 if (test->raw_write)
278 dest = test->raw_target;
279 else
280 src = test->raw_target;
281 }
282
283 if (i == tx->depth - 1) {
284 cb = ioat_dma_test_callback;
285 flags = DMA_INT_EN;
286 } else {
287 cb = NULL;
288 flags = 0;
289 }
290
291 if (test->testkind == IOAT_TEST_DMA ||
292 test->testkind == IOAT_TEST_RAW_DMA)
293 desc = ioat_copy(dma, dest, src, tx->length, cb, tx,
294 flags);
295 else if (test->testkind == IOAT_TEST_FILL) {
296 fillpattern = *(uint64_t *)tx->buf[2*i];
297 desc = ioat_blockfill(dma, dest, fillpattern,
298 tx->length, cb, tx, flags);
299 } else if (test->testkind == IOAT_TEST_DMA_8K) {
300 bus_addr_t src2, dst2;
301
302 src2 = vtophys((vm_offset_t)tx->buf[2*i] + PAGE_SIZE);
303 dst2 = vtophys((vm_offset_t)tx->buf[2*i+1] + PAGE_SIZE);
304
305 desc = ioat_copy_8k_aligned(dma, dest, dst2, src, src2,
306 cb, tx, flags);
307 } else if (test->testkind == IOAT_TEST_DMA_8K_PB) {
308 bus_addr_t src2, dst2;
309
310 src2 = vtophys((vm_offset_t)tx->buf[2*i+1] + PAGE_SIZE);
311 dst2 = vtophys((vm_offset_t)tx->buf[2*i] + PAGE_SIZE);
312
313 desc = ioat_copy_8k_aligned(dma, dest, dst2, src, src2,
314 cb, tx, flags);
315 } else if (test->testkind == IOAT_TEST_DMA_CRC) {
316 bus_addr_t crc;
317
318 tx->crc[i] = 0;
319 crc = vtophys((vm_offset_t)&tx->crc[i]);
320 desc = ioat_crc(dma, src, tx->length,
321 NULL, crc, cb, tx, flags | DMA_CRC_STORE);
322 } else if (test->testkind == IOAT_TEST_DMA_CRC_COPY) {
323 bus_addr_t crc;
324
325 tx->crc[i] = 0;
326 crc = vtophys((vm_offset_t)&tx->crc[i]);
327 desc = ioat_copy_crc(dma, dest, src, tx->length,
328 NULL, crc, cb, tx, flags | DMA_CRC_STORE);
329 }
330 if (desc == NULL)
331 break;
332 }
333 if (test->testkind == IOAT_TEST_MEMCPY)
334 return;
335 ioat_release(dma);
336
337 /*
338 * We couldn't issue an IO -- either the device is being detached or
339 * the HW reset. Essentially spin until the device comes back up or
340 * our timer expires.
341 */
342 if (desc == NULL && tx->depth > 0) {
343 atomic_add_32(&test->status[IOAT_TEST_NO_DMA_ENGINE], tx->depth);
344 IT_LOCK();
345 TAILQ_REMOVE(&test->pend_q, tx, entry);
346 TAILQ_INSERT_HEAD(&test->free_q, tx, entry);
347 IT_UNLOCK();
348 }
349 }
350
351 static void
ioat_dma_test(void * arg)352 ioat_dma_test(void *arg)
353 {
354 struct ioat_softc *ioat;
355 struct ioat_test *test;
356 bus_dmaengine_t dmaengine;
357 uint32_t loops;
358 int index, rc, start, end, error;
359
360 test = arg;
361 memset(__DEVOLATILE(void *, test->status), 0, sizeof(test->status));
362
363 if ((test->testkind == IOAT_TEST_DMA_8K ||
364 test->testkind == IOAT_TEST_DMA_8K_PB) &&
365 test->buffer_size != 2 * PAGE_SIZE) {
366 ioat_test_log(0, "Asked for 8k test and buffer size isn't 8k\n");
367 test->status[IOAT_TEST_INVALID_INPUT]++;
368 return;
369 }
370
371 if (test->buffer_size > 1024 * 1024) {
372 ioat_test_log(0, "Buffer size too large >1MB\n");
373 test->status[IOAT_TEST_NO_MEMORY]++;
374 return;
375 }
376
377 if (test->chain_depth * 2 > IOAT_MAX_BUFS) {
378 ioat_test_log(0, "Depth too large (> %u)\n",
379 (unsigned)IOAT_MAX_BUFS / 2);
380 test->status[IOAT_TEST_NO_MEMORY]++;
381 return;
382 }
383
384 if (btoc((uint64_t)test->buffer_size * test->chain_depth *
385 test->transactions) > (physmem / 4)) {
386 ioat_test_log(0, "Sanity check failed -- test would "
387 "use more than 1/4 of phys mem.\n");
388 test->status[IOAT_TEST_NO_MEMORY]++;
389 return;
390 }
391
392 if ((uint64_t)test->transactions * test->chain_depth > (1<<16)) {
393 ioat_test_log(0, "Sanity check failed -- test would "
394 "use more than available IOAT ring space.\n");
395 test->status[IOAT_TEST_NO_MEMORY]++;
396 return;
397 }
398
399 if (test->testkind >= IOAT_NUM_TESTKINDS) {
400 ioat_test_log(0, "Invalid kind %u\n",
401 (unsigned)test->testkind);
402 test->status[IOAT_TEST_INVALID_INPUT]++;
403 return;
404 }
405
406 dmaengine = ioat_get_dmaengine(test->channel_index, M_NOWAIT);
407 if (dmaengine == NULL) {
408 ioat_test_log(0, "Couldn't acquire dmaengine\n");
409 test->status[IOAT_TEST_NO_DMA_ENGINE]++;
410 return;
411 }
412 ioat = to_ioat_softc(dmaengine);
413
414 if (test->testkind == IOAT_TEST_FILL &&
415 (ioat->capabilities & IOAT_DMACAP_BFILL) == 0)
416 {
417 ioat_test_log(0,
418 "Hardware doesn't support block fill, aborting test\n");
419 test->status[IOAT_TEST_INVALID_INPUT]++;
420 goto out;
421 }
422
423 if (test->coalesce_period > ioat->intrdelay_max) {
424 ioat_test_log(0,
425 "Hardware doesn't support intrdelay of %u us.\n",
426 (unsigned)test->coalesce_period);
427 test->status[IOAT_TEST_INVALID_INPUT]++;
428 goto out;
429 }
430 error = ioat_set_interrupt_coalesce(dmaengine, test->coalesce_period);
431 if (error == ENODEV && test->coalesce_period == 0)
432 error = 0;
433 if (error != 0) {
434 ioat_test_log(0, "ioat_set_interrupt_coalesce: %d\n", error);
435 test->status[IOAT_TEST_INVALID_INPUT]++;
436 goto out;
437 }
438
439 if (test->zero_stats)
440 memset(&ioat->stats, 0, sizeof(ioat->stats));
441
442 if (test->testkind == IOAT_TEST_RAW_DMA) {
443 if (test->raw_is_virtual) {
444 test->raw_vtarget = (void *)test->raw_target;
445 test->raw_target = vtophys(test->raw_vtarget);
446 } else {
447 test->raw_vtarget = pmap_mapdev(test->raw_target,
448 test->buffer_size);
449 }
450 }
451
452 index = g_thread_index++;
453 TAILQ_INIT(&test->free_q);
454 TAILQ_INIT(&test->pend_q);
455
456 if (test->duration == 0)
457 ioat_test_log(1, "Thread %d: num_loops remaining: 0x%08x\n",
458 index, test->transactions);
459 else
460 ioat_test_log(1, "Thread %d: starting\n", index);
461
462 rc = ioat_test_prealloc_memory(test, index);
463 if (rc != 0) {
464 ioat_test_log(0, "prealloc_memory: %d\n", rc);
465 goto out;
466 }
467 wmb();
468
469 test->too_late = false;
470 start = ticks;
471 end = start + (((sbintime_t)test->duration * hz) / 1000);
472
473 for (loops = 0;; loops++) {
474 if (test->duration == 0 && loops >= test->transactions)
475 break;
476 else if (test->duration != 0 && time_after(ticks, end)) {
477 test->too_late = true;
478 break;
479 }
480
481 ioat_test_submit_1_tx(test, dmaengine);
482 }
483
484 ioat_test_log(1, "Test Elapsed: %d ticks (overrun %d), %d sec.\n",
485 ticks - start, ticks - end, (ticks - start) / hz);
486
487 IT_LOCK();
488 while (!TAILQ_EMPTY(&test->pend_q))
489 msleep(&test->free_q, &ioat_test_lk, 0, "ioattestcompl", hz);
490 IT_UNLOCK();
491
492 ioat_test_log(1, "Test Elapsed2: %d ticks (overrun %d), %d sec.\n",
493 ticks - start, ticks - end, (ticks - start) / hz);
494
495 ioat_test_release_memory(test);
496 out:
497 if (test->testkind == IOAT_TEST_RAW_DMA && !test->raw_is_virtual)
498 pmap_unmapdev(test->raw_vtarget, test->buffer_size);
499 ioat_put_dmaengine(dmaengine);
500 }
501
502 static int
ioat_test_open(struct cdev * dev,int flags,int fmt,struct thread * td)503 ioat_test_open(struct cdev *dev, int flags, int fmt, struct thread *td)
504 {
505
506 return (0);
507 }
508
509 static int
ioat_test_close(struct cdev * dev,int flags,int fmt,struct thread * td)510 ioat_test_close(struct cdev *dev, int flags, int fmt, struct thread *td)
511 {
512
513 return (0);
514 }
515
516 static int
ioat_test_ioctl(struct cdev * dev,unsigned long cmd,caddr_t arg,int flag,struct thread * td)517 ioat_test_ioctl(struct cdev *dev, unsigned long cmd, caddr_t arg, int flag,
518 struct thread *td)
519 {
520
521 switch (cmd) {
522 case IOAT_DMATEST:
523 ioat_dma_test(arg);
524 break;
525 default:
526 return (EINVAL);
527 }
528 return (0);
529 }
530
531 static struct cdevsw ioat_cdevsw = {
532 .d_version = D_VERSION,
533 .d_flags = 0,
534 .d_open = ioat_test_open,
535 .d_close = ioat_test_close,
536 .d_ioctl = ioat_test_ioctl,
537 .d_name = "ioat_test",
538 };
539
540 static int
enable_ioat_test(bool enable)541 enable_ioat_test(bool enable)
542 {
543 struct make_dev_args devargs;
544 int error = 0;
545
546 if (enable && g_ioat_cdev == NULL) {
547 make_dev_args_init(&devargs);
548 devargs.mda_devsw = &ioat_cdevsw;
549 devargs.mda_uid = UID_ROOT;
550 devargs.mda_gid = GID_WHEEL;
551 devargs.mda_mode = 0600;
552 error = make_dev_s(&devargs, &g_ioat_cdev, "ioat_test");
553 } else if (!enable && g_ioat_cdev != NULL) {
554 destroy_dev(g_ioat_cdev);
555 g_ioat_cdev = NULL;
556 }
557 return (error);
558 }
559
560 static int
sysctl_enable_ioat_test(SYSCTL_HANDLER_ARGS)561 sysctl_enable_ioat_test(SYSCTL_HANDLER_ARGS)
562 {
563 int error, enabled;
564
565 enabled = (g_ioat_cdev != NULL);
566 error = sysctl_handle_int(oidp, &enabled, 0, req);
567 if (error != 0 || req->newptr == NULL)
568 return (error);
569
570 return (enable_ioat_test(enabled));
571 }
572 SYSCTL_PROC(_hw_ioat, OID_AUTO, enable_ioat_test,
573 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0,
574 sysctl_enable_ioat_test, "I",
575 "Non-zero: Enable the /dev/ioat_test device");
576
577 void
ioat_test_attach(void)578 ioat_test_attach(void)
579 {
580 char *val;
581
582 val = kern_getenv("hw.ioat.enable_ioat_test");
583 if (val != NULL && strcmp(val, "0") != 0)
584 enable_ioat_test(true);
585 freeenv(val);
586 }
587
588 void
ioat_test_detach(void)589 ioat_test_detach(void)
590 {
591
592 enable_ioat_test(false);
593 }
594
595 static void
_ioat_test_log(int verbosity,const char * fmt,...)596 _ioat_test_log(int verbosity, const char *fmt, ...)
597 {
598 va_list argp;
599
600 if (verbosity > g_ioat_debug_level)
601 return;
602
603 va_start(argp, fmt);
604 vprintf(fmt, argp);
605 va_end(argp);
606 }
607