1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifndef OPENOCD_TARGET_ARMV7M_H
26 #define OPENOCD_TARGET_ARMV7M_H
27
28 #include "arm_adi_v5.h"
29 #include "arm.h"
30 #include "armv7m_trace.h"
31
32 extern const int armv7m_psp_reg_map[];
33 extern const int armv7m_msp_reg_map[];
34
35 const char *armv7m_exception_string(int number);
36
37 /* Cortex-M DCRSR.REGSEL selectors */
38 enum {
39 ARMV7M_REGSEL_R0,
40 ARMV7M_REGSEL_R1,
41 ARMV7M_REGSEL_R2,
42 ARMV7M_REGSEL_R3,
43
44 ARMV7M_REGSEL_R4,
45 ARMV7M_REGSEL_R5,
46 ARMV7M_REGSEL_R6,
47 ARMV7M_REGSEL_R7,
48
49 ARMV7M_REGSEL_R8,
50 ARMV7M_REGSEL_R9,
51 ARMV7M_REGSEL_R10,
52 ARMV7M_REGSEL_R11,
53
54 ARMV7M_REGSEL_R12,
55 ARMV7M_REGSEL_R13,
56 ARMV7M_REGSEL_R14,
57 ARMV7M_REGSEL_PC = 15,
58
59 ARMV7M_REGSEL_xPSR = 16,
60 ARMV7M_REGSEL_MSP,
61 ARMV7M_REGSEL_PSP,
62
63 ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
64 ARMV7M_REGSEL_FPSCR = 0x21,
65
66 /* 32bit Floating-point registers */
67 ARMV7M_REGSEL_S0 = 0x40,
68 ARMV7M_REGSEL_S1,
69 ARMV7M_REGSEL_S2,
70 ARMV7M_REGSEL_S3,
71 ARMV7M_REGSEL_S4,
72 ARMV7M_REGSEL_S5,
73 ARMV7M_REGSEL_S6,
74 ARMV7M_REGSEL_S7,
75 ARMV7M_REGSEL_S8,
76 ARMV7M_REGSEL_S9,
77 ARMV7M_REGSEL_S10,
78 ARMV7M_REGSEL_S11,
79 ARMV7M_REGSEL_S12,
80 ARMV7M_REGSEL_S13,
81 ARMV7M_REGSEL_S14,
82 ARMV7M_REGSEL_S15,
83 ARMV7M_REGSEL_S16,
84 ARMV7M_REGSEL_S17,
85 ARMV7M_REGSEL_S18,
86 ARMV7M_REGSEL_S19,
87 ARMV7M_REGSEL_S20,
88 ARMV7M_REGSEL_S21,
89 ARMV7M_REGSEL_S22,
90 ARMV7M_REGSEL_S23,
91 ARMV7M_REGSEL_S24,
92 ARMV7M_REGSEL_S25,
93 ARMV7M_REGSEL_S26,
94 ARMV7M_REGSEL_S27,
95 ARMV7M_REGSEL_S28,
96 ARMV7M_REGSEL_S29,
97 ARMV7M_REGSEL_S30,
98 ARMV7M_REGSEL_S31,
99 };
100
101 /* offsets into armv7m core register cache */
102 enum {
103 /* for convenience, the first set of indices match
104 * the Cortex-M DCRSR.REGSEL selectors
105 */
106 ARMV7M_R0 = ARMV7M_REGSEL_R0,
107 ARMV7M_R1 = ARMV7M_REGSEL_R1,
108 ARMV7M_R2 = ARMV7M_REGSEL_R2,
109 ARMV7M_R3 = ARMV7M_REGSEL_R3,
110
111 ARMV7M_R4 = ARMV7M_REGSEL_R4,
112 ARMV7M_R5 = ARMV7M_REGSEL_R5,
113 ARMV7M_R6 = ARMV7M_REGSEL_R6,
114 ARMV7M_R7 = ARMV7M_REGSEL_R7,
115
116 ARMV7M_R8 = ARMV7M_REGSEL_R8,
117 ARMV7M_R9 = ARMV7M_REGSEL_R9,
118 ARMV7M_R10 = ARMV7M_REGSEL_R10,
119 ARMV7M_R11 = ARMV7M_REGSEL_R11,
120
121 ARMV7M_R12 = ARMV7M_REGSEL_R12,
122 ARMV7M_R13 = ARMV7M_REGSEL_R13,
123 ARMV7M_R14 = ARMV7M_REGSEL_R14,
124 ARMV7M_PC = ARMV7M_REGSEL_PC,
125
126 ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
127 ARMV7M_MSP = ARMV7M_REGSEL_MSP,
128 ARMV7M_PSP = ARMV7M_REGSEL_PSP,
129
130 /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
131
132 /* working register for packing/unpacking special regs, hidden from gdb */
133 ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
134
135 /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
136 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
137 * cache only and are not flushed to CPU HW register.
138 * To trigger write to CPU HW register, add
139 * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
140 */
141 ARMV7M_PRIMASK,
142 ARMV7M_BASEPRI,
143 ARMV7M_FAULTMASK,
144 ARMV7M_CONTROL,
145
146 /* 64bit Floating-point registers */
147 ARMV7M_D0,
148 ARMV7M_D1,
149 ARMV7M_D2,
150 ARMV7M_D3,
151 ARMV7M_D4,
152 ARMV7M_D5,
153 ARMV7M_D6,
154 ARMV7M_D7,
155 ARMV7M_D8,
156 ARMV7M_D9,
157 ARMV7M_D10,
158 ARMV7M_D11,
159 ARMV7M_D12,
160 ARMV7M_D13,
161 ARMV7M_D14,
162 ARMV7M_D15,
163
164 /* Floating-point status register */
165 ARMV7M_FPSCR,
166
167 ARMV7M_LAST_REG,
168 };
169
170 enum {
171 FP_NONE = 0,
172 FPv4_SP,
173 FPv5_SP,
174 FPv5_DP,
175 };
176
177 #define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)
178 #define ARMV7M_NUM_CORE_REGS_NOFP (ARMV7M_CONTROL + 1)
179
180 #define ARMV7M_COMMON_MAGIC 0x2A452A45
181
182 struct armv7m_common {
183 struct arm arm;
184
185 int common_magic;
186 int exception_number;
187
188 /* AP this processor is connected to in the DAP */
189 struct adiv5_ap *debug_ap;
190
191 int fp_feature;
192 uint32_t demcr;
193
194 /* stlink is a high level adapter, does not support all functions */
195 bool stlink;
196
197 struct armv7m_trace_config trace_config;
198
199 /* Direct processor core register read and writes */
200 int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value);
201 int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value);
202
203 int (*examine_debug_reason)(struct target *target);
204 int (*post_debug_entry)(struct target *target);
205
206 void (*pre_restore_context)(struct target *target);
207 };
208
209 static inline struct armv7m_common *
target_to_armv7m(struct target * target)210 target_to_armv7m(struct target *target)
211 {
212 return container_of(target->arch_info, struct armv7m_common, arm);
213 }
214
is_armv7m(const struct armv7m_common * armv7m)215 static inline bool is_armv7m(const struct armv7m_common *armv7m)
216 {
217 return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
218 }
219
220 struct armv7m_algorithm {
221 int common_magic;
222
223 enum arm_mode core_mode;
224
225 uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
226 };
227
228 struct reg_cache *armv7m_build_reg_cache(struct target *target);
229 void armv7m_free_reg_cache(struct target *target);
230
231 enum armv7m_mode armv7m_number_to_mode(int number);
232 int armv7m_mode_to_number(enum armv7m_mode mode);
233
234 int armv7m_arch_state(struct target *target);
235 int armv7m_get_gdb_reg_list(struct target *target,
236 struct reg **reg_list[], int *reg_list_size,
237 enum target_register_class reg_class);
238
239 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
240
241 int armv7m_run_algorithm(struct target *target,
242 int num_mem_params, struct mem_param *mem_params,
243 int num_reg_params, struct reg_param *reg_params,
244 target_addr_t entry_point, target_addr_t exit_point,
245 int timeout_ms, void *arch_info);
246
247 int armv7m_start_algorithm(struct target *target,
248 int num_mem_params, struct mem_param *mem_params,
249 int num_reg_params, struct reg_param *reg_params,
250 target_addr_t entry_point, target_addr_t exit_point,
251 void *arch_info);
252
253 int armv7m_wait_algorithm(struct target *target,
254 int num_mem_params, struct mem_param *mem_params,
255 int num_reg_params, struct reg_param *reg_params,
256 target_addr_t exit_point, int timeout_ms,
257 void *arch_info);
258
259 int armv7m_invalidate_core_regs(struct target *target);
260
261 int armv7m_restore_context(struct target *target);
262
263 int armv7m_checksum_memory(struct target *target,
264 target_addr_t address, uint32_t count, uint32_t *checksum);
265 int armv7m_blank_check_memory(struct target *target,
266 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
267
268 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
269
270 extern const struct command_registration armv7m_command_handlers[];
271
272 #endif /* OPENOCD_TARGET_ARMV7M_H */
273