xref: /dragonfly/sys/dev/netif/tl/if_tl.c (revision 05d02a38)
1 /*
2  * Copyright (c) 1997, 1998
3  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
33  */
34 
35 /*
36  * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
37  * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
38  * the National Semiconductor DP83840A physical interface and the
39  * Microchip Technology 24Cxx series serial EEPROM.
40  *
41  * Written using the following four documents:
42  *
43  * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
44  * National Semiconductor DP83840A data sheet (www.national.com)
45  * Microchip Technology 24C02C data sheet (www.microchip.com)
46  * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
47  *
48  * Written by Bill Paul <wpaul@ctr.columbia.edu>
49  * Electrical Engineering Department
50  * Columbia University, New York City
51  */
52 
53 /*
54  * Some notes about the ThunderLAN:
55  *
56  * The ThunderLAN controller is a single chip containing PCI controller
57  * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58  * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59  * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60  * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61  * to act as a complete ethernet interface.
62  *
63  * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64  * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65  * in full or half duplex. Some of the Compaq Deskpro machines use a
66  * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67  * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68  * concert with the ThunderLAN's internal PHY to provide full 10/100
69  * support. This is cheaper than using a standalone external PHY for both
70  * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71  * A serial EEPROM is also attached to the ThunderLAN chip to provide
72  * power-up default register settings and for storing the adapter's
73  * station address. Although not supported by this driver, the ThunderLAN
74  * chip can also be connected to token ring PHYs.
75  *
76  * The ThunderLAN has a set of registers which can be used to issue
77  * commands, acknowledge interrupts, and to manipulate other internal
78  * registers on its DIO bus. The primary registers can be accessed
79  * using either programmed I/O (inb/outb) or via PCI memory mapping,
80  * depending on how the card is configured during the PCI probing
81  * phase. It is even possible to have both PIO and memory mapped
82  * access turned on at the same time.
83  *
84  * Frame reception and transmission with the ThunderLAN chip is done
85  * using frame 'lists.' A list structure looks more or less like this:
86  *
87  * struct tl_frag {
88  *	u_int32_t		fragment_address;
89  *	u_int32_t		fragment_size;
90  * };
91  * struct tl_list {
92  *	u_int32_t		forward_pointer;
93  *	u_int16_t		cstat;
94  *	u_int16_t		frame_size;
95  *	struct tl_frag		fragments[10];
96  * };
97  *
98  * The forward pointer in the list header can be either a 0 or the address
99  * of another list, which allows several lists to be linked together. Each
100  * list contains up to 10 fragment descriptors. This means the chip allows
101  * ethernet frames to be broken up into up to 10 chunks for transfer to
102  * and from the SRAM. Note that the forward pointer and fragment buffer
103  * addresses are physical memory addresses, not virtual. Note also that
104  * a single ethernet frame can not span lists: if the host wants to
105  * transmit a frame and the frame data is split up over more than 10
106  * buffers, the frame has to collapsed before it can be transmitted.
107  *
108  * To receive frames, the driver sets up a number of lists and populates
109  * the fragment descriptors, then it sends an RX GO command to the chip.
110  * When a frame is received, the chip will DMA it into the memory regions
111  * specified by the fragment descriptors and then trigger an RX 'end of
112  * frame interrupt' when done. The driver may choose to use only one
113  * fragment per list; this may result is slighltly less efficient use
114  * of memory in exchange for improving performance.
115  *
116  * To transmit frames, the driver again sets up lists and fragment
117  * descriptors, only this time the buffers contain frame data that
118  * is to be DMA'ed into the chip instead of out of it. Once the chip
119  * has transfered the data into its on-board SRAM, it will trigger a
120  * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121  * interrupt when it reaches the end of the list.
122  */
123 
124 /*
125  * Some notes about this driver:
126  *
127  * The ThunderLAN chip provides a couple of different ways to organize
128  * reception, transmission and interrupt handling. The simplest approach
129  * is to use one list each for transmission and reception. In this mode,
130  * the ThunderLAN will generate two interrupts for every received frame
131  * (one RX EOF and one RX EOC) and two for each transmitted frame (one
132  * TX EOF and one TX EOC). This may make the driver simpler but it hurts
133  * performance to have to handle so many interrupts.
134  *
135  * Initially I wanted to create a circular list of receive buffers so
136  * that the ThunderLAN chip would think there was an infinitely long
137  * receive channel and never deliver an RXEOC interrupt. However this
138  * doesn't work correctly under heavy load: while the manual says the
139  * chip will trigger an RXEOF interrupt each time a frame is copied into
140  * memory, you can't count on the chip waiting around for you to acknowledge
141  * the interrupt before it starts trying to DMA the next frame. The result
142  * is that the chip might traverse the entire circular list and then wrap
143  * around before you have a chance to do anything about it. Consequently,
144  * the receive list is terminated (with a 0 in the forward pointer in the
145  * last element). Each time an RXEOF interrupt arrives, the used list
146  * is shifted to the end of the list. This gives the appearance of an
147  * infinitely large RX chain so long as the driver doesn't fall behind
148  * the chip and allow all of the lists to be filled up.
149  *
150  * If all the lists are filled, the adapter will deliver an RX 'end of
151  * channel' interrupt when it hits the 0 forward pointer at the end of
152  * the chain. The RXEOC handler then cleans out the RX chain and resets
153  * the list head pointer in the ch_parm register and restarts the receiver.
154  *
155  * For frame transmission, it is possible to program the ThunderLAN's
156  * transmit interrupt threshold so that the chip can acknowledge multiple
157  * lists with only a single TX EOF interrupt. This allows the driver to
158  * queue several frames in one shot, and only have to handle a total
159  * two interrupts (one TX EOF and one TX EOC) no matter how many frames
160  * are transmitted. Frame transmission is done directly out of the
161  * mbufs passed to the tl_start() routine via the interface send queue.
162  * The driver simply sets up the fragment descriptors in the transmit
163  * lists to point to the mbuf data regions and sends a TX GO command.
164  *
165  * Note that since the RX and TX lists themselves are always used
166  * only by the driver, the are malloc()ed once at driver initialization
167  * time and never free()ed.
168  *
169  * Also, in order to remain as platform independent as possible, this
170  * driver uses memory mapped register access to manipulate the card
171  * as opposed to programmed I/O. This avoids the use of the inb/outb
172  * (and related) instructions which are specific to the i386 platform.
173  *
174  * Using these techniques, this driver achieves very high performance
175  * by minimizing the amount of interrupts generated during large
176  * transfers and by completely avoiding buffer copies. Frame transfer
177  * to and from the ThunderLAN chip is performed entirely by the chip
178  * itself thereby reducing the load on the host CPU.
179  */
180 
181 #include <sys/param.h>
182 #include <sys/systm.h>
183 #include <sys/sockio.h>
184 #include <sys/mbuf.h>
185 #include <sys/malloc.h>
186 #include <sys/kernel.h>
187 #include <sys/socket.h>
188 #include <sys/serialize.h>
189 #include <sys/bus.h>
190 #include <sys/rman.h>
191 #include <sys/interrupt.h>
192 
193 #include <net/if.h>
194 #include <net/ifq_var.h>
195 #include <net/if_arp.h>
196 #include <net/ethernet.h>
197 #include <net/if_dl.h>
198 #include <net/if_media.h>
199 
200 #include <net/bpf.h>
201 
202 #include <vm/vm.h>              /* for vtophys */
203 #include <vm/pmap.h>            /* for vtophys */
204 
205 #include "../mii_layer/mii.h"
206 #include "../mii_layer/miivar.h"
207 
208 #include <bus/pci/pcireg.h>
209 #include <bus/pci/pcivar.h>
210 
211 /*
212  * Default to using PIO register access mode to pacify certain
213  * laptop docking stations with built-in ThunderLAN chips that
214  * don't seem to handle memory mapped mode properly.
215  */
216 #define TL_USEIOSPACE
217 
218 #include "if_tlreg.h"
219 
220 /* "controller miibus0" required.  See GENERIC if you get errors here. */
221 #include "miibus_if.h"
222 
223 /*
224  * Various supported device vendors/types and their names.
225  */
226 
227 static struct tl_type tl_devs[] = {
228 	{ TI_VENDORID,	TI_DEVICEID_THUNDERLAN,
229 		"Texas Instruments ThunderLAN" },
230 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
231 		"Compaq Netelligent 10" },
232 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
233 		"Compaq Netelligent 10/100" },
234 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
235 		"Compaq Netelligent 10/100 Proliant" },
236 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
237 		"Compaq Netelligent 10/100 Dual Port" },
238 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
239 		"Compaq NetFlex-3/P Integrated" },
240 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
241 		"Compaq NetFlex-3/P" },
242 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
243 		"Compaq NetFlex 3/P w/ BNC" },
244 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
245 		"Compaq Netelligent 10/100 TX Embedded UTP" },
246 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
247 		"Compaq Netelligent 10 T/2 PCI UTP/Coax" },
248 	{ COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
249 		"Compaq Netelligent 10/100 TX UTP" },
250 	{ OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
251 		"Olicom OC-2183/2185" },
252 	{ OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
253 		"Olicom OC-2325" },
254 	{ OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
255 		"Olicom OC-2326 10/100 TX UTP" },
256 	{ 0, 0, NULL }
257 };
258 
259 static int tl_probe		(device_t);
260 static int tl_attach		(device_t);
261 static int tl_detach		(device_t);
262 static int tl_intvec_rxeoc	(void *, u_int32_t);
263 static int tl_intvec_txeoc	(void *, u_int32_t);
264 static int tl_intvec_txeof	(void *, u_int32_t);
265 static int tl_intvec_rxeof	(void *, u_int32_t);
266 static int tl_intvec_adchk	(void *, u_int32_t);
267 static int tl_intvec_netsts	(void *, u_int32_t);
268 
269 static int tl_newbuf		(struct tl_softc *,
270 					struct tl_chain_onefrag *);
271 static void tl_stats_update	(void *);
272 static void tl_stats_update_serialized(void *);
273 static int tl_encap		(struct tl_softc *, struct tl_chain *,
274 						struct mbuf *);
275 
276 static void tl_intr		(void *);
277 static void tl_start		(struct ifnet *, struct ifaltq_subque *);
278 static int tl_ioctl		(struct ifnet *, u_long, caddr_t,
279 						struct ucred *);
280 static void tl_init		(void *);
281 static void tl_stop		(struct tl_softc *);
282 static void tl_watchdog		(struct ifnet *);
283 static void tl_shutdown		(device_t);
284 static int tl_ifmedia_upd	(struct ifnet *);
285 static void tl_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
286 
287 static u_int8_t tl_eeprom_putbyte	(struct tl_softc *, int);
288 static u_int8_t	tl_eeprom_getbyte	(struct tl_softc *,
289 						int, u_int8_t *);
290 static int tl_read_eeprom	(struct tl_softc *, caddr_t, int, int);
291 
292 static void tl_mii_sync		(struct tl_softc *);
293 static void tl_mii_send		(struct tl_softc *, u_int32_t, int);
294 static int tl_mii_readreg	(struct tl_softc *, struct tl_mii_frame *);
295 static int tl_mii_writereg	(struct tl_softc *, struct tl_mii_frame *);
296 static int tl_miibus_readreg	(device_t, int, int);
297 static int tl_miibus_writereg	(device_t, int, int, int);
298 static void tl_miibus_statchg	(device_t);
299 
300 static void tl_setmode		(struct tl_softc *, int);
301 static int tl_calchash		(caddr_t);
302 static void tl_setmulti		(struct tl_softc *);
303 static void tl_setfilt		(struct tl_softc *, caddr_t, int);
304 static void tl_softreset	(struct tl_softc *, int);
305 static void tl_hardreset	(device_t);
306 static int tl_list_rx_init	(struct tl_softc *);
307 static int tl_list_tx_init	(struct tl_softc *);
308 
309 static u_int8_t tl_dio_read8	(struct tl_softc *, int);
310 static u_int16_t tl_dio_read16	(struct tl_softc *, int);
311 static u_int32_t tl_dio_read32	(struct tl_softc *, int);
312 static void tl_dio_write8	(struct tl_softc *, int, int);
313 static void tl_dio_write16	(struct tl_softc *, int, int);
314 static void tl_dio_write32	(struct tl_softc *, int, int);
315 static void tl_dio_setbit	(struct tl_softc *, int, int);
316 static void tl_dio_clrbit	(struct tl_softc *, int, int);
317 static void tl_dio_setbit16	(struct tl_softc *, int, int);
318 static void tl_dio_clrbit16	(struct tl_softc *, int, int);
319 
320 #ifdef TL_USEIOSPACE
321 #define TL_RES		SYS_RES_IOPORT
322 #define TL_RID		TL_PCI_LOIO
323 #else
324 #define TL_RES		SYS_RES_MEMORY
325 #define TL_RID		TL_PCI_LOMEM
326 #endif
327 
328 static device_method_t tl_methods[] = {
329 	/* Device interface */
330 	DEVMETHOD(device_probe,		tl_probe),
331 	DEVMETHOD(device_attach,	tl_attach),
332 	DEVMETHOD(device_detach,	tl_detach),
333 	DEVMETHOD(device_shutdown,	tl_shutdown),
334 
335 	/* bus interface */
336 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
337 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
338 
339 	/* MII interface */
340 	DEVMETHOD(miibus_readreg,	tl_miibus_readreg),
341 	DEVMETHOD(miibus_writereg,	tl_miibus_writereg),
342 	DEVMETHOD(miibus_statchg,	tl_miibus_statchg),
343 
344 	DEVMETHOD_END
345 };
346 
347 static driver_t tl_driver = {
348 	"tl",
349 	tl_methods,
350 	sizeof(struct tl_softc)
351 };
352 
353 static devclass_t tl_devclass;
354 
355 DECLARE_DUMMY_MODULE(if_tl);
356 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, NULL, NULL);
357 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, NULL, NULL);
358 
359 static u_int8_t
tl_dio_read8(struct tl_softc * sc,int reg)360 tl_dio_read8(struct tl_softc *sc, int reg)
361 {
362 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
363 	return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
364 }
365 
366 static u_int16_t
tl_dio_read16(struct tl_softc * sc,int reg)367 tl_dio_read16(struct tl_softc *sc, int reg)
368 {
369 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
370 	return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
371 }
372 
373 static u_int32_t
tl_dio_read32(struct tl_softc * sc,int reg)374 tl_dio_read32(struct tl_softc *sc, int reg)
375 {
376 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
377 	return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
378 }
379 
380 static void
tl_dio_write8(struct tl_softc * sc,int reg,int val)381 tl_dio_write8(struct tl_softc *sc, int reg, int val)
382 {
383 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
384 	CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
385 	return;
386 }
387 
388 static void
tl_dio_write16(struct tl_softc * sc,int reg,int val)389 tl_dio_write16(struct tl_softc *sc, int reg, int val)
390 {
391 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
392 	CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
393 	return;
394 }
395 
396 static void
tl_dio_write32(struct tl_softc * sc,int reg,int val)397 tl_dio_write32(struct tl_softc *sc, int reg, int val)
398 {
399 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
400 	CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
401 	return;
402 }
403 
404 static void
tl_dio_setbit(struct tl_softc * sc,int reg,int bit)405 tl_dio_setbit(struct tl_softc *sc, int reg, int bit)
406 {
407 	u_int8_t			f;
408 
409 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
410 	f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
411 	f |= bit;
412 	CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
413 
414 	return;
415 }
416 
417 static void
tl_dio_clrbit(struct tl_softc * sc,int reg,int bit)418 tl_dio_clrbit(struct tl_softc *sc, int reg, int bit)
419 {
420 	u_int8_t			f;
421 
422 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
423 	f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
424 	f &= ~bit;
425 	CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
426 
427 	return;
428 }
429 
430 static void
tl_dio_setbit16(struct tl_softc * sc,int reg,int bit)431 tl_dio_setbit16(struct tl_softc *sc, int reg, int bit)
432 {
433 	u_int16_t			f;
434 
435 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
436 	f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
437 	f |= bit;
438 	CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
439 
440 	return;
441 }
442 
443 static void
tl_dio_clrbit16(struct tl_softc * sc,int reg,int bit)444 tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit)
445 {
446 	u_int16_t			f;
447 
448 	CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
449 	f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
450 	f &= ~bit;
451 	CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
452 
453 	return;
454 }
455 
456 /*
457  * Send an instruction or address to the EEPROM, check for ACK.
458  */
459 static u_int8_t
tl_eeprom_putbyte(struct tl_softc * sc,int byte)460 tl_eeprom_putbyte(struct tl_softc *sc, int byte)
461 {
462 	int		i, ack = 0;
463 
464 	/*
465 	 * Make sure we're in TX mode.
466 	 */
467 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
468 
469 	/*
470 	 * Feed in each bit and stobe the clock.
471 	 */
472 	for (i = 0x80; i; i >>= 1) {
473 		if (byte & i) {
474 			tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
475 		} else {
476 			tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
477 		}
478 		DELAY(1);
479 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
480 		DELAY(1);
481 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
482 	}
483 
484 	/*
485 	 * Turn off TX mode.
486 	 */
487 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
488 
489 	/*
490 	 * Check for ack.
491 	 */
492 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
493 	ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
494 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
495 
496 	return(ack);
497 }
498 
499 /*
500  * Read a byte of data stored in the EEPROM at address 'addr.'
501  */
502 static u_int8_t
tl_eeprom_getbyte(struct tl_softc * sc,int addr,u_int8_t * dest)503 tl_eeprom_getbyte(struct tl_softc *sc, int addr, u_int8_t *dest)
504 {
505 	int		i;
506 	u_int8_t		byte = 0;
507 
508 	tl_dio_write8(sc, TL_NETSIO, 0);
509 
510 	EEPROM_START;
511 
512 	/*
513 	 * Send write control code to EEPROM.
514 	 */
515 	if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
516 		if_printf(&sc->arpcom.ac_if, "failed to send write command, "
517 			  "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
518 		return(1);
519 	}
520 
521 	/*
522 	 * Send address of byte we want to read.
523 	 */
524 	if (tl_eeprom_putbyte(sc, addr)) {
525 		if_printf(&sc->arpcom.ac_if, "failed to send address, "
526 			  "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
527 		return(1);
528 	}
529 
530 	EEPROM_STOP;
531 	EEPROM_START;
532 	/*
533 	 * Send read control code to EEPROM.
534 	 */
535 	if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
536 		if_printf(&sc->arpcom.ac_if, "failed to send write command, "
537 			  "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
538 		return(1);
539 	}
540 
541 	/*
542 	 * Start reading bits from EEPROM.
543 	 */
544 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
545 	for (i = 0x80; i; i >>= 1) {
546 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
547 		DELAY(1);
548 		if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
549 			byte |= i;
550 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
551 		DELAY(1);
552 	}
553 
554 	EEPROM_STOP;
555 
556 	/*
557 	 * No ACK generated for read, so just return byte.
558 	 */
559 
560 	*dest = byte;
561 
562 	return(0);
563 }
564 
565 /*
566  * Read a sequence of bytes from the EEPROM.
567  */
568 static int
tl_read_eeprom(struct tl_softc * sc,caddr_t dest,int off,int cnt)569 tl_read_eeprom(struct tl_softc *sc, caddr_t dest, int off, int cnt)
570 {
571 	int			err = 0, i;
572 	u_int8_t		byte = 0;
573 
574 	for (i = 0; i < cnt; i++) {
575 		err = tl_eeprom_getbyte(sc, off + i, &byte);
576 		if (err)
577 			break;
578 		*(dest + i) = byte;
579 	}
580 
581 	return(err ? 1 : 0);
582 }
583 
584 static void
tl_mii_sync(struct tl_softc * sc)585 tl_mii_sync(struct tl_softc *sc)
586 {
587 	int		i;
588 
589 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
590 
591 	for (i = 0; i < 32; i++) {
592 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
593 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
594 	}
595 
596 	return;
597 }
598 
599 static void
tl_mii_send(struct tl_softc * sc,u_int32_t bits,int cnt)600 tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt)
601 {
602 	int			i;
603 
604 	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
605 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
606 		if (bits & i) {
607 			tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
608 		} else {
609 			tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
610 		}
611 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
612 	}
613 }
614 
615 static int
tl_mii_readreg(struct tl_softc * sc,struct tl_mii_frame * frame)616 tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame)
617 {
618 	int			i, ack;
619 	int			minten = 0;
620 
621 	tl_mii_sync(sc);
622 
623 	/*
624 	 * Set up frame for RX.
625 	 */
626 	frame->mii_stdelim = TL_MII_STARTDELIM;
627 	frame->mii_opcode = TL_MII_READOP;
628 	frame->mii_turnaround = 0;
629 	frame->mii_data = 0;
630 
631 	/*
632 	 * Turn off MII interrupt by forcing MINTEN low.
633 	 */
634 	minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
635 	if (minten) {
636 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
637 	}
638 
639 	/*
640  	 * Turn on data xmit.
641 	 */
642 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
643 
644 	/*
645 	 * Send command/address info.
646 	 */
647 	tl_mii_send(sc, frame->mii_stdelim, 2);
648 	tl_mii_send(sc, frame->mii_opcode, 2);
649 	tl_mii_send(sc, frame->mii_phyaddr, 5);
650 	tl_mii_send(sc, frame->mii_regaddr, 5);
651 
652 	/*
653 	 * Turn off xmit.
654 	 */
655 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
656 
657 	/* Idle bit */
658 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
659 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
660 
661 	/* Check for ack */
662 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
663 	ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
664 
665 	/* Complete the cycle */
666 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
667 
668 	/*
669 	 * Now try reading data bits. If the ack failed, we still
670 	 * need to clock through 16 cycles to keep the PHYs in sync.
671 	 */
672 	if (ack) {
673 		for(i = 0; i < 16; i++) {
674 			tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
675 			tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
676 		}
677 		goto fail;
678 	}
679 
680 	for (i = 0x8000; i; i >>= 1) {
681 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
682 		if (!ack) {
683 			if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
684 				frame->mii_data |= i;
685 		}
686 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
687 	}
688 
689 fail:
690 
691 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
692 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
693 
694 	/* Reenable interrupts */
695 	if (minten) {
696 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
697 	}
698 
699 	if (ack)
700 		return(1);
701 	return(0);
702 }
703 
704 static int
tl_mii_writereg(struct tl_softc * sc,struct tl_mii_frame * frame)705 tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame)
706 {
707 	int			minten;
708 
709 	tl_mii_sync(sc);
710 
711 	/*
712 	 * Set up frame for TX.
713 	 */
714 
715 	frame->mii_stdelim = TL_MII_STARTDELIM;
716 	frame->mii_opcode = TL_MII_WRITEOP;
717 	frame->mii_turnaround = TL_MII_TURNAROUND;
718 
719 	/*
720 	 * Turn off MII interrupt by forcing MINTEN low.
721 	 */
722 	minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
723 	if (minten) {
724 		tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
725 	}
726 
727 	/*
728  	 * Turn on data output.
729 	 */
730 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
731 
732 	tl_mii_send(sc, frame->mii_stdelim, 2);
733 	tl_mii_send(sc, frame->mii_opcode, 2);
734 	tl_mii_send(sc, frame->mii_phyaddr, 5);
735 	tl_mii_send(sc, frame->mii_regaddr, 5);
736 	tl_mii_send(sc, frame->mii_turnaround, 2);
737 	tl_mii_send(sc, frame->mii_data, 16);
738 
739 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
740 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
741 
742 	/*
743 	 * Turn off xmit.
744 	 */
745 	tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
746 
747 	/* Reenable interrupts */
748 	if (minten)
749 		tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
750 
751 	return(0);
752 }
753 
754 static int
tl_miibus_readreg(device_t dev,int phy,int reg)755 tl_miibus_readreg(device_t dev, int phy, int reg)
756 {
757 	struct tl_softc		*sc;
758 	struct tl_mii_frame	frame;
759 
760 	sc = device_get_softc(dev);
761 	bzero((char *)&frame, sizeof(frame));
762 
763 	frame.mii_phyaddr = phy;
764 	frame.mii_regaddr = reg;
765 	tl_mii_readreg(sc, &frame);
766 
767 	return(frame.mii_data);
768 }
769 
770 static int
tl_miibus_writereg(device_t dev,int phy,int reg,int data)771 tl_miibus_writereg(device_t dev, int phy, int reg, int data)
772 {
773 	struct tl_softc		*sc;
774 	struct tl_mii_frame	frame;
775 
776 	sc = device_get_softc(dev);
777 	bzero((char *)&frame, sizeof(frame));
778 
779 	frame.mii_phyaddr = phy;
780 	frame.mii_regaddr = reg;
781 	frame.mii_data = data;
782 
783 	tl_mii_writereg(sc, &frame);
784 
785 	return(0);
786 }
787 
788 static void
tl_miibus_statchg(device_t dev)789 tl_miibus_statchg(device_t dev)
790 {
791 	struct tl_softc		*sc;
792 	struct mii_data		*mii;
793 
794 	sc = device_get_softc(dev);
795 	mii = device_get_softc(sc->tl_miibus);
796 
797 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
798 		tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
799 	} else {
800 		tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
801 	}
802 
803 	return;
804 }
805 
806 /*
807  * Set modes for bitrate devices.
808  */
809 static void
tl_setmode(struct tl_softc * sc,int media)810 tl_setmode(struct tl_softc *sc, int media)
811 {
812 	if (IFM_SUBTYPE(media) == IFM_10_5)
813 		tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
814 	if (IFM_SUBTYPE(media) == IFM_10_T) {
815 		tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
816 		if ((media & IFM_GMASK) == IFM_FDX) {
817 			tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
818 			tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
819 		} else {
820 			tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
821 			tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
822 		}
823 	}
824 
825 	return;
826 }
827 
828 /*
829  * Calculate the hash of a MAC address for programming the multicast hash
830  * table.  This hash is simply the address split into 6-bit chunks
831  * XOR'd, e.g.
832  * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
833  * bit:  765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
834  * Bytes 0-2 and 3-5 are symmetrical, so are folded together.  Then
835  * the folded 24-bit value is split into 6-bit portions and XOR'd.
836  */
837 static int
tl_calchash(caddr_t addr)838 tl_calchash(caddr_t addr)
839 {
840 	int			t;
841 
842 	t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
843 		(addr[2] ^ addr[5]);
844 	return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
845 }
846 
847 /*
848  * The ThunderLAN has a perfect MAC address filter in addition to
849  * the multicast hash filter. The perfect filter can be programmed
850  * with up to four MAC addresses. The first one is always used to
851  * hold the station address, which leaves us free to use the other
852  * three for multicast addresses.
853  */
854 static void
tl_setfilt(struct tl_softc * sc,caddr_t addr,int slot)855 tl_setfilt(struct tl_softc *sc, caddr_t addr, int slot)
856 {
857 	int			i;
858 	u_int16_t		regaddr;
859 
860 	regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
861 
862 	for (i = 0; i < ETHER_ADDR_LEN; i++)
863 		tl_dio_write8(sc, regaddr + i, *(addr + i));
864 
865 	return;
866 }
867 
868 /*
869  * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
870  * linked list. This is fine, except addresses are added from the head
871  * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
872  * group to always be in the perfect filter, but as more groups are added,
873  * the 224.0.0.1 entry (which is always added first) gets pushed down
874  * the list and ends up at the tail. So after 3 or 4 multicast groups
875  * are added, the all-hosts entry gets pushed out of the perfect filter
876  * and into the hash table.
877  *
878  * Because the multicast list is a doubly-linked list as opposed to a
879  * circular queue, we don't have the ability to just grab the tail of
880  * the list and traverse it backwards. Instead, we have to traverse
881  * the list once to find the tail, then traverse it again backwards to
882  * update the multicast filter.
883  */
884 static void
tl_setmulti(struct tl_softc * sc)885 tl_setmulti(struct tl_softc *sc)
886 {
887 	struct ifnet		*ifp;
888 	u_int32_t		hashes[2] = { 0, 0 };
889 	int			h, i;
890 	struct ifmultiaddr	*ifma;
891 	u_int8_t		dummy[] = { 0, 0, 0, 0, 0 ,0 };
892 	ifp = &sc->arpcom.ac_if;
893 
894 	/* First, zot all the existing filters. */
895 	for (i = 1; i < 4; i++)
896 		tl_setfilt(sc, (caddr_t)&dummy, i);
897 	tl_dio_write32(sc, TL_HASH1, 0);
898 	tl_dio_write32(sc, TL_HASH2, 0);
899 
900 	/* Now program new ones. */
901 	if (ifp->if_flags & IFF_ALLMULTI) {
902 		hashes[0] = 0xFFFFFFFF;
903 		hashes[1] = 0xFFFFFFFF;
904 	} else {
905 		i = 1;
906 		TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
907 			if (ifma->ifma_addr->sa_family != AF_LINK)
908 				continue;
909 			/*
910 			 * Program the first three multicast groups
911 			 * into the perfect filter. For all others,
912 			 * use the hash table.
913 			 */
914 			if (i < 4) {
915 				tl_setfilt(sc,
916 			LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
917 				i++;
918 				continue;
919 			}
920 
921 			h = tl_calchash(
922 				LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
923 			if (h < 32)
924 				hashes[0] |= (1 << h);
925 			else
926 				hashes[1] |= (1 << (h - 32));
927 		}
928 	}
929 
930 	tl_dio_write32(sc, TL_HASH1, hashes[0]);
931 	tl_dio_write32(sc, TL_HASH2, hashes[1]);
932 
933 	return;
934 }
935 
936 /*
937  * This routine is recommended by the ThunderLAN manual to insure that
938  * the internal PHY is powered up correctly. It also recommends a one
939  * second pause at the end to 'wait for the clocks to start' but in my
940  * experience this isn't necessary.
941  */
942 static void
tl_hardreset(device_t dev)943 tl_hardreset(device_t dev)
944 {
945 	struct tl_softc		*sc;
946 	int			i;
947 	u_int16_t		flags;
948 
949 	sc = device_get_softc(dev);
950 
951 	tl_mii_sync(sc);
952 
953 	flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
954 
955 	for (i = 0; i < MII_NPHY; i++)
956 		tl_miibus_writereg(dev, i, MII_BMCR, flags);
957 
958 	tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
959 	DELAY(50000);
960 	tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
961 	tl_mii_sync(sc);
962 	while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
963 
964 	DELAY(50000);
965 	return;
966 }
967 
968 static void
tl_softreset(struct tl_softc * sc,int internal)969 tl_softreset(struct tl_softc *sc, int internal)
970 {
971         u_int32_t               cmd, i;
972 
973         /* Assert the adapter reset bit. */
974 	CMD_SET(sc, TL_CMD_ADRST);
975 
976         /* Turn off interrupts */
977 	CMD_SET(sc, TL_CMD_INTSOFF);
978 
979 	/* First, clear the stats registers. */
980 	for (i = 0; i < 5; i++)
981 		tl_dio_read32(sc, TL_TXGOODFRAMES);
982 
983         /* Clear Areg and Hash registers */
984 	for (i = 0; i < 8; i++)
985 		tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
986 
987         /*
988 	 * Set up Netconfig register. Enable one channel and
989 	 * one fragment mode.
990 	 */
991 	tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
992 	if (internal && !sc->tl_bitrate) {
993 		tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
994 	} else {
995 		tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
996 	}
997 
998 	/* Handle cards with bitrate devices. */
999 	if (sc->tl_bitrate)
1000 		tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1001 
1002 	/*
1003 	 * Load adapter irq pacing timer and tx threshold.
1004 	 * We make the transmit threshold 1 initially but we may
1005 	 * change that later.
1006 	 */
1007 	cmd = CSR_READ_4(sc, TL_HOSTCMD);
1008 	cmd |= TL_CMD_NES;
1009 	cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1010 	CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1011 	CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1012 
1013         /* Unreset the MII */
1014 	tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1015 
1016 	/* Take the adapter out of reset */
1017 	tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1018 
1019 	/* Wait for things to settle down a little. */
1020 	DELAY(500);
1021 
1022         return;
1023 }
1024 
1025 /*
1026  * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1027  * against our list and return its name if we find a match.
1028  */
1029 static int
tl_probe(device_t dev)1030 tl_probe(device_t dev)
1031 {
1032 	struct tl_type		*t;
1033 
1034 	t = tl_devs;
1035 
1036 	while(t->tl_name != NULL) {
1037 		if ((pci_get_vendor(dev) == t->tl_vid) &&
1038 		    (pci_get_device(dev) == t->tl_did)) {
1039 			device_set_desc(dev, t->tl_name);
1040 			return(0);
1041 		}
1042 		t++;
1043 	}
1044 
1045 	return(ENXIO);
1046 }
1047 
1048 static int
tl_attach(device_t dev)1049 tl_attach(device_t dev)
1050 {
1051 	int			i;
1052 	u_int16_t		did, vid;
1053 	struct tl_type		*t;
1054 	struct ifnet		*ifp;
1055 	struct tl_softc		*sc;
1056 	int			error = 0, rid;
1057 	uint8_t			eaddr[ETHER_ADDR_LEN];
1058 
1059 	vid = pci_get_vendor(dev);
1060 	did = pci_get_device(dev);
1061 	sc = device_get_softc(dev);
1062 
1063 	t = tl_devs;
1064 	while(t->tl_name != NULL) {
1065 		if (vid == t->tl_vid && did == t->tl_did)
1066 			break;
1067 		t++;
1068 	}
1069 
1070 	KKASSERT(t->tl_name != NULL);
1071 
1072 	pci_enable_busmaster(dev);
1073 
1074 #ifdef TL_USEIOSPACE
1075 	rid = TL_PCI_LOIO;
1076 	sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1077 		RF_ACTIVE);
1078 
1079 	/*
1080 	 * Some cards have the I/O and memory mapped address registers
1081 	 * reversed. Try both combinations before giving up.
1082 	 */
1083 	if (sc->tl_res == NULL) {
1084 		rid = TL_PCI_LOMEM;
1085 		sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1086 		    RF_ACTIVE);
1087 	}
1088 #else
1089 	rid = TL_PCI_LOMEM;
1090 	sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1091 	    RF_ACTIVE);
1092 	if (sc->tl_res == NULL) {
1093 		rid = TL_PCI_LOIO;
1094 		sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1095 		    RF_ACTIVE);
1096 	}
1097 #endif
1098 
1099 	if (sc->tl_res == NULL) {
1100 		device_printf(dev, "couldn't map ports/memory\n");
1101 		error = ENXIO;
1102 		return(error);
1103 	}
1104 
1105 	sc->tl_btag = rman_get_bustag(sc->tl_res);
1106 	sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1107 
1108 #ifdef notdef
1109 	/*
1110 	 * The ThunderLAN manual suggests jacking the PCI latency
1111 	 * timer all the way up to its maximum value. I'm not sure
1112 	 * if this is really necessary, but what the manual wants,
1113 	 * the manual gets.
1114 	 */
1115 	command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1116 	command |= 0x0000FF00;
1117 	pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1118 #endif
1119 
1120 	/* Allocate interrupt */
1121 	rid = 0;
1122 	sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1123 	    RF_SHAREABLE | RF_ACTIVE);
1124 
1125 	if (sc->tl_irq == NULL) {
1126 		device_printf(dev, "couldn't map interrupt\n");
1127 		error = ENXIO;
1128 		goto fail;
1129 	}
1130 
1131 	/*
1132 	 * Now allocate memory for the TX and RX lists.
1133 	 */
1134 	sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1135 	    M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
1136 
1137 	if (sc->tl_ldata == NULL) {
1138 		device_printf(dev, "no memory for list buffers!\n");
1139 		error = ENXIO;
1140 		goto fail;
1141 	}
1142 
1143 	sc->tl_dinfo = t;
1144 	if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1145 		sc->tl_eeaddr = TL_EEPROM_EADDR;
1146 	if (t->tl_vid == OLICOM_VENDORID)
1147 		sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1148 
1149 	/* Reset the adapter. */
1150 	tl_softreset(sc, 1);
1151 	tl_hardreset(dev);
1152 	tl_softreset(sc, 1);
1153 
1154 	ifp = &sc->arpcom.ac_if;
1155 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1156 
1157 	/*
1158 	 * Get station address from the EEPROM.
1159 	 */
1160 	if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1161 		device_printf(dev, "failed to read station address\n");
1162 		error = ENXIO;
1163 		goto fail;
1164 	}
1165 
1166         /*
1167          * XXX Olicom, in its desire to be different from the
1168          * rest of the world, has done strange things with the
1169          * encoding of the station address in the EEPROM. First
1170          * of all, they store the address at offset 0xF8 rather
1171          * than at 0x83 like the ThunderLAN manual suggests.
1172          * Second, they store the address in three 16-bit words in
1173          * network byte order, as opposed to storing it sequentially
1174          * like all the other ThunderLAN cards. In order to get
1175          * the station address in a form that matches what the Olicom
1176          * diagnostic utility specifies, we have to byte-swap each
1177          * word. To make things even more confusing, neither 00:00:28
1178          * nor 00:00:24 appear in the IEEE OUI database.
1179          */
1180         if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1181                 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1182                         u_int16_t               *p;
1183                         p = (u_int16_t *)&eaddr[i];
1184                         *p = ntohs(*p);
1185                 }
1186         }
1187 
1188 	ifp->if_softc = sc;
1189 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1190 	ifp->if_ioctl = tl_ioctl;
1191 	ifp->if_start = tl_start;
1192 	ifp->if_watchdog = tl_watchdog;
1193 	ifp->if_init = tl_init;
1194 	ifp->if_mtu = ETHERMTU;
1195 	ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1);
1196 	ifq_set_ready(&ifp->if_snd);
1197 	callout_init(&sc->tl_stat_timer);
1198 
1199 	/* Reset the adapter again. */
1200 	tl_softreset(sc, 1);
1201 	tl_hardreset(dev);
1202 	tl_softreset(sc, 1);
1203 
1204 	/*
1205 	 * Do MII setup. If no PHYs are found, then this is a
1206 	 * bitrate ThunderLAN chip that only supports 10baseT
1207 	 * and AUI/BNC.
1208 	 */
1209 	if (mii_phy_probe(dev, &sc->tl_miibus,
1210 	    tl_ifmedia_upd, tl_ifmedia_sts)) {
1211 		struct ifmedia		*ifm;
1212 		sc->tl_bitrate = 1;
1213 		ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1214 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1215 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1216 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1217 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1218 		ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1219 		/* Reset again, this time setting bitrate mode. */
1220 		tl_softreset(sc, 1);
1221 		ifm = &sc->ifmedia;
1222 		ifm->ifm_media = ifm->ifm_cur->ifm_media;
1223 		tl_ifmedia_upd(ifp);
1224 	}
1225 
1226 	/*
1227 	 * Call MI attach routine.
1228 	 */
1229 	ether_ifattach(ifp, eaddr, NULL);
1230 
1231 	ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->tl_irq));
1232 
1233 	error = bus_setup_intr(dev, sc->tl_irq, INTR_MPSAFE,
1234 			       tl_intr, sc, &sc->tl_intrhand,
1235 			       ifp->if_serializer);
1236 
1237 	if (error) {
1238 		ether_ifdetach(ifp);
1239 		device_printf(dev, "couldn't set up irq\n");
1240 		goto fail;
1241 	}
1242 
1243 	return(0);
1244 
1245 fail:
1246 	tl_detach(dev);
1247 	return(error);
1248 }
1249 
1250 static int
tl_detach(device_t dev)1251 tl_detach(device_t dev)
1252 {
1253 	struct tl_softc *sc = device_get_softc(dev);
1254 	struct ifnet *ifp = &sc->arpcom.ac_if;
1255 
1256 	if (device_is_attached(dev)) {
1257 		lwkt_serialize_enter(ifp->if_serializer);
1258 		tl_stop(sc);
1259 		bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1260 		lwkt_serialize_exit(ifp->if_serializer);
1261 
1262 		ether_ifdetach(ifp);
1263 	}
1264 
1265 	if (sc->tl_miibus)
1266 		device_delete_child(dev, sc->tl_miibus);
1267 	bus_generic_detach(dev);
1268 
1269 	if (sc->tl_ldata)
1270 		contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1271 	if (sc->tl_bitrate)
1272 		ifmedia_removeall(&sc->ifmedia);
1273 	if (sc->tl_irq)
1274 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1275 	if (sc->tl_res)
1276 		bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1277 
1278 	return(0);
1279 }
1280 
1281 /*
1282  * Initialize the transmit lists.
1283  */
1284 static int
tl_list_tx_init(struct tl_softc * sc)1285 tl_list_tx_init(struct tl_softc *sc)
1286 {
1287 	struct tl_chain_data	*cd;
1288 	struct tl_list_data	*ld;
1289 	int			i;
1290 
1291 	cd = &sc->tl_cdata;
1292 	ld = sc->tl_ldata;
1293 	for (i = 0; i < TL_TX_LIST_CNT; i++) {
1294 		cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1295 		if (i == (TL_TX_LIST_CNT - 1))
1296 			cd->tl_tx_chain[i].tl_next = NULL;
1297 		else
1298 			cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1299 	}
1300 
1301 	cd->tl_tx_free = &cd->tl_tx_chain[0];
1302 	cd->tl_tx_tail = cd->tl_tx_head = NULL;
1303 	sc->tl_txeoc = 1;
1304 
1305 	return(0);
1306 }
1307 
1308 /*
1309  * Initialize the RX lists and allocate mbufs for them.
1310  */
1311 static int
tl_list_rx_init(struct tl_softc * sc)1312 tl_list_rx_init(struct tl_softc *sc)
1313 {
1314 	struct tl_chain_data	*cd;
1315 	struct tl_list_data	*ld;
1316 	int			i;
1317 
1318 	cd = &sc->tl_cdata;
1319 	ld = sc->tl_ldata;
1320 
1321 	for (i = 0; i < TL_RX_LIST_CNT; i++) {
1322 		cd->tl_rx_chain[i].tl_ptr =
1323 			(struct tl_list_onefrag *)&ld->tl_rx_list[i];
1324 		if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1325 			return(ENOBUFS);
1326 		if (i == (TL_RX_LIST_CNT - 1)) {
1327 			cd->tl_rx_chain[i].tl_next = NULL;
1328 			ld->tl_rx_list[i].tlist_fptr = 0;
1329 		} else {
1330 			cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1331 			ld->tl_rx_list[i].tlist_fptr =
1332 					vtophys(&ld->tl_rx_list[i + 1]);
1333 		}
1334 	}
1335 
1336 	cd->tl_rx_head = &cd->tl_rx_chain[0];
1337 	cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1338 
1339 	return(0);
1340 }
1341 
1342 static int
tl_newbuf(struct tl_softc * sc,struct tl_chain_onefrag * c)1343 tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c)
1344 {
1345 	struct mbuf *m_new;
1346 
1347 	m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1348 	if (m_new == NULL)
1349 		return (ENOBUFS);
1350 
1351 	c->tl_mbuf = m_new;
1352 	c->tl_next = NULL;
1353 	c->tl_ptr->tlist_frsize = MCLBYTES;
1354 	c->tl_ptr->tlist_fptr = 0;
1355 	c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1356 	c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1357 	c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1358 
1359 	return(0);
1360 }
1361 
1362 /*
1363  * Interrupt handler for RX 'end of frame' condition (EOF). This
1364  * tells us that a full ethernet frame has been captured and we need
1365  * to handle it.
1366  *
1367  * Reception is done using 'lists' which consist of a header and a
1368  * series of 10 data count/data address pairs that point to buffers.
1369  * Initially you're supposed to create a list, populate it with pointers
1370  * to buffers, then load the physical address of the list into the
1371  * ch_parm register. The adapter is then supposed to DMA the received
1372  * frame into the buffers for you.
1373  *
1374  * To make things as fast as possible, we have the chip DMA directly
1375  * into mbufs. This saves us from having to do a buffer copy: we can
1376  * just hand the mbufs directly to ether_input(). Once the frame has
1377  * been sent on its way, the 'list' structure is assigned a new buffer
1378  * and moved to the end of the RX chain. As long we we stay ahead of
1379  * the chip, it will always think it has an endless receive channel.
1380  *
1381  * If we happen to fall behind and the chip manages to fill up all of
1382  * the buffers, it will generate an end of channel interrupt and wait
1383  * for us to empty the chain and restart the receiver.
1384  */
1385 static int
tl_intvec_rxeof(void * xsc,u_int32_t type)1386 tl_intvec_rxeof(void *xsc, u_int32_t type)
1387 {
1388 	struct tl_softc		*sc;
1389 	int			r = 0, total_len = 0;
1390 	struct ether_header	*eh;
1391 	struct mbuf		*m;
1392 	struct ifnet		*ifp;
1393 	struct tl_chain_onefrag	*cur_rx;
1394 
1395 	sc = xsc;
1396 	ifp = &sc->arpcom.ac_if;
1397 
1398 	while(sc->tl_cdata.tl_rx_head != NULL) {
1399 		cur_rx = sc->tl_cdata.tl_rx_head;
1400 		if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1401 			break;
1402 		r++;
1403 		sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1404 		m = cur_rx->tl_mbuf;
1405 		total_len = cur_rx->tl_ptr->tlist_frsize;
1406 
1407 		if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1408 			IFNET_STAT_INC(ifp, ierrors, 1);
1409 			cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1410 			cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1411 			cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1412 			continue;
1413 		}
1414 
1415 		sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1416 						vtophys(cur_rx->tl_ptr);
1417 		sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1418 		sc->tl_cdata.tl_rx_tail = cur_rx;
1419 
1420 		eh = mtod(m, struct ether_header *);
1421 		m->m_pkthdr.rcvif = ifp;
1422 		m->m_pkthdr.len = m->m_len = total_len;
1423 
1424 		/*
1425 		 * Note: when the ThunderLAN chip is in 'capture all
1426 		 * frames' mode, it will receive its own transmissions.
1427 		 * We drop don't need to process our own transmissions,
1428 		 * so we drop them here and continue.
1429 		 */
1430 		/*if (ifp->if_flags & IFF_PROMISC && */
1431 		if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1432 		 					ETHER_ADDR_LEN)) {
1433 				m_freem(m);
1434 				continue;
1435 		}
1436 
1437 		ifp->if_input(ifp, m, NULL, -1);
1438 	}
1439 
1440 	return(r);
1441 }
1442 
1443 /*
1444  * The RX-EOC condition hits when the ch_parm address hasn't been
1445  * initialized or the adapter reached a list with a forward pointer
1446  * of 0 (which indicates the end of the chain). In our case, this means
1447  * the card has hit the end of the receive buffer chain and we need to
1448  * empty out the buffers and shift the pointer back to the beginning again.
1449  */
1450 static int
tl_intvec_rxeoc(void * xsc,u_int32_t type)1451 tl_intvec_rxeoc(void *xsc, u_int32_t type)
1452 {
1453 	struct tl_softc		*sc;
1454 	int			r;
1455 	struct tl_chain_data	*cd;
1456 
1457 
1458 	sc = xsc;
1459 	cd = &sc->tl_cdata;
1460 
1461 	/* Flush out the receive queue and ack RXEOF interrupts. */
1462 	r = tl_intvec_rxeof(xsc, type);
1463 	CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1464 	r = 1;
1465 	cd->tl_rx_head = &cd->tl_rx_chain[0];
1466 	cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1467 	CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1468 	r |= (TL_CMD_GO|TL_CMD_RT);
1469 	return(r);
1470 }
1471 
1472 static int
tl_intvec_txeof(void * xsc,u_int32_t type)1473 tl_intvec_txeof(void *xsc, u_int32_t type)
1474 {
1475 	struct tl_softc		*sc;
1476 	int			r = 0;
1477 	struct tl_chain		*cur_tx;
1478 
1479 	sc = xsc;
1480 
1481 	/*
1482 	 * Go through our tx list and free mbufs for those
1483 	 * frames that have been sent.
1484 	 */
1485 	while (sc->tl_cdata.tl_tx_head != NULL) {
1486 		cur_tx = sc->tl_cdata.tl_tx_head;
1487 		if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1488 			break;
1489 		sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1490 
1491 		r++;
1492 		m_freem(cur_tx->tl_mbuf);
1493 		cur_tx->tl_mbuf = NULL;
1494 
1495 		cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1496 		sc->tl_cdata.tl_tx_free = cur_tx;
1497 		if (!cur_tx->tl_ptr->tlist_fptr)
1498 			break;
1499 	}
1500 
1501 	return(r);
1502 }
1503 
1504 /*
1505  * The transmit end of channel interrupt. The adapter triggers this
1506  * interrupt to tell us it hit the end of the current transmit list.
1507  *
1508  * A note about this: it's possible for a condition to arise where
1509  * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1510  * You have to avoid this since the chip expects things to go in a
1511  * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1512  * When the TXEOF handler is called, it will free all of the transmitted
1513  * frames and reset the tx_head pointer to NULL. However, a TXEOC
1514  * interrupt should be received and acknowledged before any more frames
1515  * are queued for transmission. If tl_statrt() is called after TXEOF
1516  * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1517  * it could attempt to issue a transmit command prematurely.
1518  *
1519  * To guard against this, tl_start() will only issue transmit commands
1520  * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1521  * can set this flag once tl_start() has cleared it.
1522  */
1523 static int
tl_intvec_txeoc(void * xsc,u_int32_t type)1524 tl_intvec_txeoc(void *xsc, u_int32_t type)
1525 {
1526 	struct tl_softc		*sc;
1527 	struct ifnet		*ifp;
1528 	u_int32_t		cmd;
1529 
1530 	sc = xsc;
1531 	ifp = &sc->arpcom.ac_if;
1532 
1533 	/* Clear the timeout timer. */
1534 	ifp->if_timer = 0;
1535 
1536 	if (sc->tl_cdata.tl_tx_head == NULL) {
1537 		ifq_clr_oactive(&ifp->if_snd);
1538 		sc->tl_cdata.tl_tx_tail = NULL;
1539 		sc->tl_txeoc = 1;
1540 	} else {
1541 		sc->tl_txeoc = 0;
1542 		/* First we have to ack the EOC interrupt. */
1543 		CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1544 		/* Then load the address of the next TX list. */
1545 		CSR_WRITE_4(sc, TL_CH_PARM,
1546 		    vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1547 		/* Restart TX channel. */
1548 		cmd = CSR_READ_4(sc, TL_HOSTCMD);
1549 		cmd &= ~TL_CMD_RT;
1550 		cmd |= TL_CMD_GO|TL_CMD_INTSON;
1551 		CMD_PUT(sc, cmd);
1552 		return(0);
1553 	}
1554 
1555 	return(1);
1556 }
1557 
1558 static int
tl_intvec_adchk(void * xsc,u_int32_t type)1559 tl_intvec_adchk(void *xsc, u_int32_t type)
1560 {
1561 	struct tl_softc		*sc;
1562 
1563 	sc = xsc;
1564 
1565 	if (type) {
1566 		if_printf(&sc->arpcom.ac_if, "adapter check: %x\n",
1567 			  (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1568 	}
1569 
1570 	tl_softreset(sc, 1);
1571 	tl_stop(sc);
1572 	tl_init(sc);
1573 	CMD_SET(sc, TL_CMD_INTSON);
1574 
1575 	return(0);
1576 }
1577 
1578 static int
tl_intvec_netsts(void * xsc,u_int32_t type)1579 tl_intvec_netsts(void *xsc, u_int32_t type)
1580 {
1581 	struct tl_softc		*sc;
1582 	u_int16_t		netsts;
1583 
1584 	sc = xsc;
1585 
1586 	netsts = tl_dio_read16(sc, TL_NETSTS);
1587 	tl_dio_write16(sc, TL_NETSTS, netsts);
1588 
1589 	if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts);
1590 
1591 	return(1);
1592 }
1593 
1594 static void
tl_intr(void * xsc)1595 tl_intr(void *xsc)
1596 {
1597 	struct tl_softc		*sc;
1598 	struct ifnet		*ifp;
1599 	int			r = 0;
1600 	u_int32_t		type = 0;
1601 	u_int16_t		ints = 0;
1602 	u_int8_t		ivec = 0;
1603 
1604 	sc = xsc;
1605 
1606 	/* Disable interrupts */
1607 	ints = CSR_READ_2(sc, TL_HOST_INT);
1608 	CSR_WRITE_2(sc, TL_HOST_INT, ints);
1609 	type = (ints << 16) & 0xFFFF0000;
1610 	ivec = (ints & TL_VEC_MASK) >> 5;
1611 	ints = (ints & TL_INT_MASK) >> 2;
1612 
1613 	ifp = &sc->arpcom.ac_if;
1614 
1615 	switch(ints) {
1616 	case (TL_INTR_INVALID):
1617 #ifdef DIAGNOSTIC
1618 		if_printf(ifp, "got an invalid interrupt!\n");
1619 #endif
1620 		/* Re-enable interrupts but don't ack this one. */
1621 		CMD_PUT(sc, type);
1622 		r = 0;
1623 		break;
1624 	case (TL_INTR_TXEOF):
1625 		r = tl_intvec_txeof(sc, type);
1626 		break;
1627 	case (TL_INTR_TXEOC):
1628 		r = tl_intvec_txeoc(sc, type);
1629 		break;
1630 	case (TL_INTR_STATOFLOW):
1631 		tl_stats_update_serialized(sc);
1632 		r = 1;
1633 		break;
1634 	case (TL_INTR_RXEOF):
1635 		r = tl_intvec_rxeof(sc, type);
1636 		break;
1637 	case (TL_INTR_DUMMY):
1638 		if_printf(ifp, "got a dummy interrupt\n");
1639 		r = 1;
1640 		break;
1641 	case (TL_INTR_ADCHK):
1642 		if (ivec)
1643 			r = tl_intvec_adchk(sc, type);
1644 		else
1645 			r = tl_intvec_netsts(sc, type);
1646 		break;
1647 	case (TL_INTR_RXEOC):
1648 		r = tl_intvec_rxeoc(sc, type);
1649 		break;
1650 	default:
1651 		if_printf(ifp, "bogus interrupt type\n");
1652 		break;
1653 	}
1654 
1655 	/* Re-enable interrupts */
1656 	if (r) {
1657 		CMD_PUT(sc, TL_CMD_ACK | r | type);
1658 	}
1659 
1660 	if (!ifq_is_empty(&ifp->if_snd))
1661 		if_devstart(ifp);
1662 }
1663 
1664 static
1665 void
tl_stats_update(void * xsc)1666 tl_stats_update(void *xsc)
1667 {
1668 	struct tl_softc *sc = xsc;
1669 	struct ifnet *ifp = &sc->arpcom.ac_if;
1670 
1671 	lwkt_serialize_enter(ifp->if_serializer);
1672 	tl_stats_update_serialized(xsc);
1673 	lwkt_serialize_exit(ifp->if_serializer);
1674 }
1675 
1676 static
1677 void
tl_stats_update_serialized(void * xsc)1678 tl_stats_update_serialized(void *xsc)
1679 {
1680 	struct tl_softc		*sc;
1681 	struct ifnet		*ifp;
1682 	struct tl_stats		tl_stats;
1683 	struct mii_data		*mii;
1684 	u_int32_t		*p;
1685 
1686 	bzero((char *)&tl_stats, sizeof(struct tl_stats));
1687 
1688 	sc = xsc;
1689 	ifp = &sc->arpcom.ac_if;
1690 
1691 	p = (u_int32_t *)&tl_stats;
1692 
1693 	CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1694 	*p++ = CSR_READ_4(sc, TL_DIO_DATA);
1695 	*p++ = CSR_READ_4(sc, TL_DIO_DATA);
1696 	*p++ = CSR_READ_4(sc, TL_DIO_DATA);
1697 	*p++ = CSR_READ_4(sc, TL_DIO_DATA);
1698 	*p++ = CSR_READ_4(sc, TL_DIO_DATA);
1699 
1700 	IFNET_STAT_INC(ifp, opackets, tl_tx_goodframes(tl_stats));
1701 	IFNET_STAT_INC(ifp, collisions, tl_stats.tl_tx_single_collision +
1702 	    tl_stats.tl_tx_multi_collision);
1703 	IFNET_STAT_INC(ifp, ipackets, tl_rx_goodframes(tl_stats));
1704 	IFNET_STAT_INC(ifp, ierrors, tl_stats.tl_crc_errors +
1705 	    tl_stats.tl_code_errors + tl_rx_overrun(tl_stats));
1706 	IFNET_STAT_INC(ifp, oerrors, tl_tx_underrun(tl_stats));
1707 
1708 	if (tl_tx_underrun(tl_stats)) {
1709 		u_int8_t		tx_thresh;
1710 		tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1711 		if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1712 			tx_thresh >>= 4;
1713 			tx_thresh++;
1714 			if_printf(ifp, "tx underrun -- increasing "
1715 				  "tx threshold to %d bytes\n",
1716 				  (64 * (tx_thresh * 4)));
1717 			tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1718 			tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1719 		}
1720 	}
1721 
1722 	callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1723 
1724 	if (!sc->tl_bitrate) {
1725 		mii = device_get_softc(sc->tl_miibus);
1726 		mii_tick(mii);
1727 	}
1728 }
1729 
1730 /*
1731  * Encapsulate an mbuf chain in a list by coupling the mbuf data
1732  * pointers to the fragment pointers.
1733  */
1734 static int
tl_encap(struct tl_softc * sc,struct tl_chain * c,struct mbuf * m_head)1735 tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head)
1736 {
1737 	int			frag = 0;
1738 	struct tl_frag		*f = NULL;
1739 	int			total_len;
1740 	struct mbuf		*m;
1741 
1742 	/*
1743  	 * Start packing the mbufs in this chain into
1744 	 * the fragment pointers. Stop when we run out
1745  	 * of fragments or hit the end of the mbuf chain.
1746 	 */
1747 	total_len = 0;
1748 
1749 	for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1750 		if (m->m_len != 0) {
1751 			if (frag == TL_MAXFRAGS)
1752 				break;
1753 			total_len+= m->m_len;
1754 			c->tl_ptr->tl_frag[frag].tlist_dadr =
1755 				vtophys(mtod(m, vm_offset_t));
1756 			c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1757 			frag++;
1758 		}
1759 	}
1760 
1761 	/*
1762 	 * Handle special cases.
1763 	 * Special case #1: we used up all 10 fragments, but
1764 	 * we have more mbufs left in the chain. Copy the
1765 	 * data into an mbuf cluster. Note that we don't
1766 	 * bother clearing the values in the other fragment
1767 	 * pointers/counters; it wouldn't gain us anything,
1768 	 * and would waste cycles.
1769 	 */
1770 	if (m != NULL) {
1771 		struct mbuf *m_new;
1772 
1773 		m_new = m_getl(m_head->m_pkthdr.len, M_NOWAIT, MT_DATA,
1774 			       M_PKTHDR, NULL);
1775 		if (m_new == NULL) {
1776 			if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1777 			return (1);
1778 		}
1779 		m_copydata(m_head, 0, m_head->m_pkthdr.len,
1780 			   mtod(m_new, void *));
1781 		m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1782 		m_freem(m_head);
1783 		m_head = m_new;
1784 		f = &c->tl_ptr->tl_frag[0];
1785 		f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1786 		f->tlist_dcnt = total_len = m_new->m_len;
1787 		frag = 1;
1788 	}
1789 
1790 	/*
1791 	 * Special case #2: the frame is smaller than the minimum
1792 	 * frame size. We have to pad it to make the chip happy.
1793 	 */
1794 	if (total_len < TL_MIN_FRAMELEN) {
1795 		if (frag == TL_MAXFRAGS) {
1796 			if_printf(&sc->arpcom.ac_if, "all frags filled but "
1797 				  "frame still to small!\n");
1798 		}
1799 		f = &c->tl_ptr->tl_frag[frag];
1800 		f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1801 		f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1802 		total_len += f->tlist_dcnt;
1803 		frag++;
1804 	}
1805 
1806 	c->tl_mbuf = m_head;
1807 	c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1808 	c->tl_ptr->tlist_frsize = total_len;
1809 	c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1810 	c->tl_ptr->tlist_fptr = 0;
1811 
1812 	return(0);
1813 }
1814 
1815 /*
1816  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1817  * to the mbuf data regions directly in the transmit lists. We also save a
1818  * copy of the pointers since the transmit list fragment pointers are
1819  * physical addresses.
1820  */
1821 static void
tl_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1822 tl_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1823 {
1824 	struct tl_softc		*sc;
1825 	struct mbuf		*m_head = NULL;
1826 	u_int32_t		cmd;
1827 	struct tl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
1828 
1829 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1830 
1831 	sc = ifp->if_softc;
1832 
1833 	/*
1834 	 * Check for an available queue slot. If there are none,
1835 	 * punt.
1836 	 */
1837 	if (sc->tl_cdata.tl_tx_free == NULL) {
1838 		ifq_set_oactive(&ifp->if_snd);
1839 		return;
1840 	}
1841 
1842 	start_tx = sc->tl_cdata.tl_tx_free;
1843 
1844 	while(sc->tl_cdata.tl_tx_free != NULL) {
1845 		m_head = ifq_dequeue(&ifp->if_snd);
1846 		if (m_head == NULL)
1847 			break;
1848 
1849 		/* Pick a chain member off the free list. */
1850 		cur_tx = sc->tl_cdata.tl_tx_free;
1851 		sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1852 
1853 		cur_tx->tl_next = NULL;
1854 
1855 		/* Pack the data into the list. */
1856 		tl_encap(sc, cur_tx, m_head);
1857 
1858 		/* Chain it together */
1859 		if (prev != NULL) {
1860 			prev->tl_next = cur_tx;
1861 			prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1862 		}
1863 		prev = cur_tx;
1864 
1865 		BPF_MTAP(ifp, cur_tx->tl_mbuf);
1866 	}
1867 
1868 	/*
1869 	 * If there are no packets queued, bail.
1870 	 */
1871 	if (cur_tx == NULL)
1872 		return;
1873 
1874 	/*
1875 	 * That's all we can stands, we can't stands no more.
1876 	 * If there are no other transfers pending, then issue the
1877 	 * TX GO command to the adapter to start things moving.
1878 	 * Otherwise, just leave the data in the queue and let
1879 	 * the EOF/EOC interrupt handler send.
1880 	 */
1881 	if (sc->tl_cdata.tl_tx_head == NULL) {
1882 		sc->tl_cdata.tl_tx_head = start_tx;
1883 		sc->tl_cdata.tl_tx_tail = cur_tx;
1884 
1885 		if (sc->tl_txeoc) {
1886 			sc->tl_txeoc = 0;
1887 			CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1888 			cmd = CSR_READ_4(sc, TL_HOSTCMD);
1889 			cmd &= ~TL_CMD_RT;
1890 			cmd |= TL_CMD_GO|TL_CMD_INTSON;
1891 			CMD_PUT(sc, cmd);
1892 		}
1893 	} else {
1894 		sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1895 		sc->tl_cdata.tl_tx_tail = cur_tx;
1896 	}
1897 
1898 	/*
1899 	 * Set a timeout in case the chip goes out to lunch.
1900 	 */
1901 	ifp->if_timer = 5;
1902 
1903 	return;
1904 }
1905 
1906 static void
tl_init(void * xsc)1907 tl_init(void *xsc)
1908 {
1909 	struct tl_softc		*sc = xsc;
1910 	struct ifnet		*ifp = &sc->arpcom.ac_if;
1911 	struct mii_data		*mii;
1912 
1913 	/*
1914 	 * Cancel pending I/O.
1915 	 */
1916 	tl_stop(sc);
1917 
1918 	/* Initialize TX FIFO threshold */
1919 	tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1920 	tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1921 
1922         /* Set PCI burst size */
1923 	tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
1924 
1925 	/*
1926 	 * Set 'capture all frames' bit for promiscuous mode.
1927 	 */
1928 	if (ifp->if_flags & IFF_PROMISC)
1929 		tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
1930 	else
1931 		tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
1932 
1933 	/*
1934 	 * Set capture broadcast bit to capture broadcast frames.
1935 	 */
1936 	if (ifp->if_flags & IFF_BROADCAST)
1937 		tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1938 	else
1939 		tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1940 
1941 	tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
1942 
1943 	/* Init our MAC address */
1944 	tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
1945 
1946 	/* Init multicast filter, if needed. */
1947 	tl_setmulti(sc);
1948 
1949 	/* Init circular RX list. */
1950 	if (tl_list_rx_init(sc) == ENOBUFS) {
1951 		if_printf(ifp, "initialization failed: no "
1952 			  "memory for rx buffers\n");
1953 		tl_stop(sc);
1954 		return;
1955 	}
1956 
1957 	/* Init TX pointers. */
1958 	tl_list_tx_init(sc);
1959 
1960 	/* Enable PCI interrupts. */
1961 	CMD_SET(sc, TL_CMD_INTSON);
1962 
1963 	/* Load the address of the rx list */
1964 	CMD_SET(sc, TL_CMD_RT);
1965 	CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
1966 
1967 	if (!sc->tl_bitrate) {
1968 		if (sc->tl_miibus != NULL) {
1969 			mii = device_get_softc(sc->tl_miibus);
1970 			mii_mediachg(mii);
1971 		}
1972 	}
1973 
1974 	/* Send the RX go command */
1975 	CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
1976 
1977 	ifp->if_flags |= IFF_RUNNING;
1978 	ifq_clr_oactive(&ifp->if_snd);
1979 
1980 	/* Start the stats update counter */
1981 	callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1982 }
1983 
1984 /*
1985  * Set media options.
1986  */
1987 static int
tl_ifmedia_upd(struct ifnet * ifp)1988 tl_ifmedia_upd(struct ifnet *ifp)
1989 {
1990 	struct tl_softc		*sc;
1991 	struct mii_data		*mii = NULL;
1992 
1993 	sc = ifp->if_softc;
1994 
1995 	if (sc->tl_bitrate)
1996 		tl_setmode(sc, sc->ifmedia.ifm_media);
1997 	else {
1998 		mii = device_get_softc(sc->tl_miibus);
1999 		mii_mediachg(mii);
2000 	}
2001 
2002 	return(0);
2003 }
2004 
2005 /*
2006  * Report current media status.
2007  */
2008 static void
tl_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)2009 tl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2010 {
2011 	struct tl_softc		*sc;
2012 	struct mii_data		*mii;
2013 
2014 	sc = ifp->if_softc;
2015 
2016 	ifmr->ifm_active = IFM_ETHER;
2017 
2018 	if (sc->tl_bitrate) {
2019 		if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2020 			ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2021 		else
2022 			ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2023 		if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2024 			ifmr->ifm_active |= IFM_HDX;
2025 		else
2026 			ifmr->ifm_active |= IFM_FDX;
2027 		return;
2028 	} else {
2029 		mii = device_get_softc(sc->tl_miibus);
2030 		mii_pollstat(mii);
2031 		ifmr->ifm_active = mii->mii_media_active;
2032 		ifmr->ifm_status = mii->mii_media_status;
2033 	}
2034 
2035 	return;
2036 }
2037 
2038 static int
tl_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)2039 tl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2040 {
2041 	struct tl_softc		*sc = ifp->if_softc;
2042 	struct ifreq		*ifr = (struct ifreq *) data;
2043 	int			error = 0;
2044 
2045 	switch(command) {
2046 	case SIOCSIFFLAGS:
2047 		if (ifp->if_flags & IFF_UP) {
2048 			if (ifp->if_flags & IFF_RUNNING &&
2049 			    ifp->if_flags & IFF_PROMISC &&
2050 			    !(sc->tl_if_flags & IFF_PROMISC)) {
2051 				tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2052 				tl_setmulti(sc);
2053 			} else if (ifp->if_flags & IFF_RUNNING &&
2054 			    !(ifp->if_flags & IFF_PROMISC) &&
2055 			    sc->tl_if_flags & IFF_PROMISC) {
2056 				tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2057 				tl_setmulti(sc);
2058 			} else
2059 				tl_init(sc);
2060 		} else {
2061 			if (ifp->if_flags & IFF_RUNNING) {
2062 				tl_stop(sc);
2063 			}
2064 		}
2065 		sc->tl_if_flags = ifp->if_flags;
2066 		error = 0;
2067 		break;
2068 	case SIOCADDMULTI:
2069 	case SIOCDELMULTI:
2070 		tl_setmulti(sc);
2071 		error = 0;
2072 		break;
2073 	case SIOCSIFMEDIA:
2074 	case SIOCGIFMEDIA:
2075 		if (sc->tl_bitrate)
2076 			error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2077 		else {
2078 			struct mii_data		*mii;
2079 			mii = device_get_softc(sc->tl_miibus);
2080 			error = ifmedia_ioctl(ifp, ifr,
2081 			    &mii->mii_media, command);
2082 		}
2083 		break;
2084 	default:
2085 		error = ether_ioctl(ifp, command, data);
2086 		break;
2087 	}
2088 	return(error);
2089 }
2090 
2091 static void
tl_watchdog(struct ifnet * ifp)2092 tl_watchdog(struct ifnet *ifp)
2093 {
2094 	struct tl_softc		*sc;
2095 
2096 	sc = ifp->if_softc;
2097 
2098 	if_printf(ifp, "device timeout\n");
2099 
2100 	IFNET_STAT_INC(ifp, oerrors, 1);
2101 
2102 	tl_softreset(sc, 1);
2103 	tl_init(sc);
2104 
2105 	return;
2106 }
2107 
2108 /*
2109  * Stop the adapter and free any mbufs allocated to the
2110  * RX and TX lists.
2111  */
2112 static void
tl_stop(struct tl_softc * sc)2113 tl_stop(struct tl_softc *sc)
2114 {
2115 	int		i;
2116 	struct ifnet		*ifp;
2117 
2118 	ifp = &sc->arpcom.ac_if;
2119 
2120 	/* Stop the stats updater. */
2121 	callout_stop(&sc->tl_stat_timer);
2122 
2123 	/* Stop the transmitter */
2124 	CMD_CLR(sc, TL_CMD_RT);
2125 	CMD_SET(sc, TL_CMD_STOP);
2126 	CSR_WRITE_4(sc, TL_CH_PARM, 0);
2127 
2128 	/* Stop the receiver */
2129 	CMD_SET(sc, TL_CMD_RT);
2130 	CMD_SET(sc, TL_CMD_STOP);
2131 	CSR_WRITE_4(sc, TL_CH_PARM, 0);
2132 
2133 	/*
2134 	 * Disable host interrupts.
2135 	 */
2136 	CMD_SET(sc, TL_CMD_INTSOFF);
2137 
2138 	/*
2139 	 * Clear list pointer.
2140 	 */
2141 	CSR_WRITE_4(sc, TL_CH_PARM, 0);
2142 
2143 	/*
2144 	 * Free the RX lists.
2145 	 */
2146 	for (i = 0; i < TL_RX_LIST_CNT; i++) {
2147 		if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2148 			m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2149 			sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2150 		}
2151 	}
2152 	bzero((char *)&sc->tl_ldata->tl_rx_list,
2153 		sizeof(sc->tl_ldata->tl_rx_list));
2154 
2155 	/*
2156 	 * Free the TX list buffers.
2157 	 */
2158 	for (i = 0; i < TL_TX_LIST_CNT; i++) {
2159 		if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2160 			m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2161 			sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2162 		}
2163 	}
2164 	bzero((char *)&sc->tl_ldata->tl_tx_list,
2165 		sizeof(sc->tl_ldata->tl_tx_list));
2166 
2167 	ifp->if_flags &= ~IFF_RUNNING;
2168 	ifq_clr_oactive(&ifp->if_snd);
2169 
2170 	return;
2171 }
2172 
2173 /*
2174  * Stop all chip I/O so that the kernel's probe routines don't
2175  * get confused by errant DMAs when rebooting.
2176  */
2177 static void
tl_shutdown(device_t dev)2178 tl_shutdown(device_t dev)
2179 {
2180 	struct tl_softc		*sc;
2181 
2182 	sc = device_get_softc(dev);
2183 
2184 	tl_stop(sc);
2185 
2186 	return;
2187 }
2188