1 /* automatically generated by m68k-bus-auto.sh, do not edit! */ 2 _TME_RCSID("$Id: m68k-bus-auto.sh,v 1.3 2007/02/12 23:47:11 fredette Exp $"); 3 4 /* we use OP3, OP2, OP1, and OP0 to represent bytes of lesser 5 significance to more significance, respectively, matching Table 5-5 6 in the MC68020 User's Manual (linear page 56 in my .ps copy). 7 8 the Motorola OPn convention numbers bytes by decreasing 9 significance (OP2 is less significant than OP1), and since Motorola 10 CPUs are big-endian, this means that a higher numbered byte is 11 meant to go to a higher address, which is good, because we can then 12 use this to easily form indexes for TME_BUS_LANE_ROUTE, which 13 expects a higher numbered index to correspond to a higher address 14 in memory. 15 16 however, since the same Motorola OPn convention always calls the 17 least significant byte of any value OP3, regardless of the total 18 size of the value, we need to adjust each OPn given the total 19 size of the value, so that OP3 in a 24-bit value means address + 2, 20 but OP3 in a 32-bit value means address + 3: */ 21 #define SIZ8_OP(n) ((n) - 3) 22 #define SIZ16_OP(n) ((n) - 2) 23 #define SIZ24_OP(n) ((n) - 1) 24 #define SIZ32_OP(n) ((n) - 0) 25 26 /* the 16-bit bus router used on the 68000 and 68010: */ 27 const tme_bus_lane_t tme_m68k_router_16[TME_M68K_BUS_ROUTER_SIZE(TME_BUS16_LOG2)] = { 28 29 /* [m68k] initiator maximum cycle size: 8 bits 30 [m68k] initiator A0: 0 31 [gen] responding port size: 8 bits 32 [gen] responding port least lane: 0 (lanes D7-D0 - incorrect for 16-bit m68k) 33 (code 1.0.1.0): */ 34 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 35 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 36 37 /* [m68k] initiator maximum cycle size: 8 bits 38 [m68k] initiator A0: 0 39 [gen] responding port size: 8 bits 40 [gen] responding port least lane: 1 (lanes D15-D8) 41 (code 1.0.1.1): */ 42 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 43 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 44 45 /* [m68k] initiator maximum cycle size: 8 bits 46 [m68k] initiator A0: 0 47 [gen] responding port size: 16 bits 48 [gen] responding port least lane: 0 (lanes D15-D8 D7-D0) 49 (code 1.0.2.0): */ 50 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 51 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 52 53 /* [m68k] initiator maximum cycle size: 8 bits 54 [m68k] initiator A0: 0 55 [gen] responding port size: 16 bits 56 [gen] responding port least lane: 1 (lanes D23-D16 D15-D8 - invalid, array placeholder) 57 (code 1.0.2.1): */ 58 /* D7-D0 */ TME_BUS_LANE_ABORT, 59 /* D15-D8 */ TME_BUS_LANE_ABORT, 60 61 /* [m68k] initiator maximum cycle size: 8 bits 62 [m68k] initiator A0: 1 63 [gen] responding port size: 8 bits 64 [gen] responding port least lane: 0 (lanes D7-D0) 65 (code 1.1.1.0): */ 66 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 67 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 68 69 /* [m68k] initiator maximum cycle size: 8 bits 70 [m68k] initiator A0: 1 71 [gen] responding port size: 8 bits 72 [gen] responding port least lane: 1 (lanes D15-D8 - incorrect for 16-bit m68k) 73 (code 1.1.1.1): */ 74 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 75 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 76 77 /* [m68k] initiator maximum cycle size: 8 bits 78 [m68k] initiator A0: 1 79 [gen] responding port size: 16 bits 80 [gen] responding port least lane: 0 (lanes D15-D8 D7-D0) 81 (code 1.1.2.0): */ 82 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 83 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 84 85 /* [m68k] initiator maximum cycle size: 8 bits 86 [m68k] initiator A0: 1 87 [gen] responding port size: 16 bits 88 [gen] responding port least lane: 1 (lanes D23-D16 D15-D8 - invalid, array placeholder) 89 (code 1.1.2.1): */ 90 /* D7-D0 */ TME_BUS_LANE_ABORT, 91 /* D15-D8 */ TME_BUS_LANE_ABORT, 92 93 /* [m68k] initiator maximum cycle size: 16 bits 94 [m68k] initiator A0: 0 95 [gen] responding port size: 8 bits 96 [gen] responding port least lane: 0 (lanes D7-D0) 97 (code 2.0.1.0): */ 98 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 99 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 100 101 /* [m68k] initiator maximum cycle size: 16 bits 102 [m68k] initiator A0: 0 103 [gen] responding port size: 8 bits 104 [gen] responding port least lane: 1 (lanes D15-D8) 105 (code 2.0.1.1): */ 106 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 107 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 108 109 /* [m68k] initiator maximum cycle size: 16 bits 110 [m68k] initiator A0: 0 111 [gen] responding port size: 16 bits 112 [gen] responding port least lane: 0 (lanes D15-D8 D7-D0) 113 (code 2.0.2.0): */ 114 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 115 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 116 117 /* [m68k] initiator maximum cycle size: 16 bits 118 [m68k] initiator A0: 0 119 [gen] responding port size: 16 bits 120 [gen] responding port least lane: 1 (lanes D23-D16 D15-D8 - invalid, array placeholder) 121 (code 2.0.2.1): */ 122 /* D7-D0 */ TME_BUS_LANE_ABORT, 123 /* D15-D8 */ TME_BUS_LANE_ABORT, 124 125 /* [m68k] initiator maximum cycle size: 16 bits 126 [m68k] initiator A0: 1 127 [gen] responding port size: 8 bits 128 [gen] responding port least lane: 0 (lanes D7-D0) 129 (code 2.1.1.0): */ 130 /* D7-D0 */ TME_BUS_LANE_ABORT, 131 /* D15-D8 */ TME_BUS_LANE_ABORT, 132 133 /* [m68k] initiator maximum cycle size: 16 bits 134 [m68k] initiator A0: 1 135 [gen] responding port size: 8 bits 136 [gen] responding port least lane: 1 (lanes D15-D8) 137 (code 2.1.1.1): */ 138 /* D7-D0 */ TME_BUS_LANE_ABORT, 139 /* D15-D8 */ TME_BUS_LANE_ABORT, 140 141 /* [m68k] initiator maximum cycle size: 16 bits 142 [m68k] initiator A0: 1 143 [gen] responding port size: 16 bits 144 [gen] responding port least lane: 0 (lanes D15-D8 D7-D0) 145 (code 2.1.2.0): */ 146 /* D7-D0 */ TME_BUS_LANE_ABORT, 147 /* D15-D8 */ TME_BUS_LANE_ABORT, 148 149 /* [m68k] initiator maximum cycle size: 16 bits 150 [m68k] initiator A0: 1 151 [gen] responding port size: 16 bits 152 [gen] responding port least lane: 1 (lanes D23-D16 D15-D8 - invalid, array placeholder) 153 (code 2.1.2.1): */ 154 /* D7-D0 */ TME_BUS_LANE_ABORT, 155 /* D15-D8 */ TME_BUS_LANE_ABORT, 156 }; 157 158 /* the 32-bit bus router used on the 68020 and 68030: */ 159 const tme_bus_lane_t tme_m68k_router_32[TME_M68K_BUS_ROUTER_SIZE(TME_BUS32_LOG2)] = { 160 161 /* [m68k] initiator maximum cycle size: 8 bits 162 [m68k] initiator A1,A0: 00 163 [gen] responder port size: 8 bits 164 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 165 (code 1.0.1.0, OP3 lane 3): */ 166 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 167 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 168 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 169 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 170 171 /* [m68k] initiator maximum cycle size: 8 bits 172 [m68k] initiator A1,A0: 00 173 [gen] responder port size: 8 bits 174 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 175 (code 1.0.1.1, OP3 lane 3): */ 176 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 177 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 178 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 179 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 180 181 /* [m68k] initiator maximum cycle size: 8 bits 182 [m68k] initiator A1,A0: 00 183 [gen] responder port size: 8 bits 184 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 185 (code 1.0.1.2, OP3 lane 3): */ 186 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 187 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 188 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 189 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 190 191 /* [m68k] initiator maximum cycle size: 8 bits 192 [m68k] initiator A1,A0: 00 193 [gen] responder port size: 8 bits 194 [gen] responder port least lane: 3 (lanes D31-D24) 195 (code 1.0.1.3, OP3 lane 3): */ 196 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 197 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 198 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 199 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 200 201 /* [m68k] initiator maximum cycle size: 8 bits 202 [m68k] initiator A1,A0: 00 203 [gen] responder port size: 16 bits 204 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 205 (code 1.0.2.0, OP3 lane 3): */ 206 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 207 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 208 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 209 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 210 211 /* [m68k] initiator maximum cycle size: 8 bits 212 [m68k] initiator A1,A0: 00 213 [gen] responder port size: 16 bits 214 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 215 (code 1.0.2.1, OP3 lane 3): */ 216 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 217 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 218 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 219 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 220 221 /* [m68k] initiator maximum cycle size: 8 bits 222 [m68k] initiator A1,A0: 00 223 [gen] responder port size: 16 bits 224 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 225 (code 1.0.2.2, OP3 lane 3): */ 226 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 227 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 228 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 229 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 230 231 /* [m68k] initiator maximum cycle size: 8 bits 232 [m68k] initiator A1,A0: 00 233 [gen] responder port size: 16 bits 234 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 235 (code 1.0.2.3, OP3 lane 3): */ 236 /* D7-D0 */ TME_BUS_LANE_ABORT, 237 /* D15-D8 */ TME_BUS_LANE_ABORT, 238 /* D23-D16 */ TME_BUS_LANE_ABORT, 239 /* D31-D24 */ TME_BUS_LANE_ABORT, 240 241 /* [m68k] initiator maximum cycle size: 8 bits 242 [m68k] initiator A1,A0: 00 243 [gen] responder port size: 32 bits 244 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 245 (code 1.0.4.0, OP3 lane 3): */ 246 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 247 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 248 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 249 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 250 251 /* [m68k] initiator maximum cycle size: 8 bits 252 [m68k] initiator A1,A0: 00 253 [gen] responder port size: 32 bits 254 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 255 (code 1.0.4.1, OP3 lane 3): */ 256 /* D7-D0 */ TME_BUS_LANE_ABORT, 257 /* D15-D8 */ TME_BUS_LANE_ABORT, 258 /* D23-D16 */ TME_BUS_LANE_ABORT, 259 /* D31-D24 */ TME_BUS_LANE_ABORT, 260 261 /* [m68k] initiator maximum cycle size: 8 bits 262 [m68k] initiator A1,A0: 00 263 [gen] responder port size: 32 bits 264 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 265 (code 1.0.4.2, OP3 lane 3): */ 266 /* D7-D0 */ TME_BUS_LANE_ABORT, 267 /* D15-D8 */ TME_BUS_LANE_ABORT, 268 /* D23-D16 */ TME_BUS_LANE_ABORT, 269 /* D31-D24 */ TME_BUS_LANE_ABORT, 270 271 /* [m68k] initiator maximum cycle size: 8 bits 272 [m68k] initiator A1,A0: 00 273 [gen] responder port size: 32 bits 274 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 275 (code 1.0.4.3, OP3 lane 3): */ 276 /* D7-D0 */ TME_BUS_LANE_ABORT, 277 /* D15-D8 */ TME_BUS_LANE_ABORT, 278 /* D23-D16 */ TME_BUS_LANE_ABORT, 279 /* D31-D24 */ TME_BUS_LANE_ABORT, 280 281 /* [m68k] initiator maximum cycle size: 8 bits 282 [m68k] initiator A1,A0: 01 283 [gen] responder port size: 8 bits 284 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 285 (code 1.1.1.0, OP3 lane 3): */ 286 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 287 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 288 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 289 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 290 291 /* [m68k] initiator maximum cycle size: 8 bits 292 [m68k] initiator A1,A0: 01 293 [gen] responder port size: 8 bits 294 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 295 (code 1.1.1.1, OP3 lane 3): */ 296 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 297 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 298 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 299 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 300 301 /* [m68k] initiator maximum cycle size: 8 bits 302 [m68k] initiator A1,A0: 01 303 [gen] responder port size: 8 bits 304 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 305 (code 1.1.1.2, OP3 lane 3): */ 306 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 307 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 308 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 309 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 310 311 /* [m68k] initiator maximum cycle size: 8 bits 312 [m68k] initiator A1,A0: 01 313 [gen] responder port size: 8 bits 314 [gen] responder port least lane: 3 (lanes D31-D24) 315 (code 1.1.1.3, OP3 lane 3): */ 316 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 317 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 318 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 319 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 320 321 /* [m68k] initiator maximum cycle size: 8 bits 322 [m68k] initiator A1,A0: 01 323 [gen] responder port size: 16 bits 324 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 325 (code 1.1.2.0, OP3 lane 2): */ 326 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 327 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 328 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 329 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 330 331 /* [m68k] initiator maximum cycle size: 8 bits 332 [m68k] initiator A1,A0: 01 333 [gen] responder port size: 16 bits 334 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 335 (code 1.1.2.1, OP3 lane 2): */ 336 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 337 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 338 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 339 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 340 341 /* [m68k] initiator maximum cycle size: 8 bits 342 [m68k] initiator A1,A0: 01 343 [gen] responder port size: 16 bits 344 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 345 (code 1.1.2.2, OP3 lane 2): */ 346 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 347 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 348 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 349 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 350 351 /* [m68k] initiator maximum cycle size: 8 bits 352 [m68k] initiator A1,A0: 01 353 [gen] responder port size: 16 bits 354 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 355 (code 1.1.2.3, OP3 lane 2): */ 356 /* D7-D0 */ TME_BUS_LANE_ABORT, 357 /* D15-D8 */ TME_BUS_LANE_ABORT, 358 /* D23-D16 */ TME_BUS_LANE_ABORT, 359 /* D31-D24 */ TME_BUS_LANE_ABORT, 360 361 /* [m68k] initiator maximum cycle size: 8 bits 362 [m68k] initiator A1,A0: 01 363 [gen] responder port size: 32 bits 364 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 365 (code 1.1.4.0, OP3 lane 2): */ 366 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 367 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 368 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 369 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 370 371 /* [m68k] initiator maximum cycle size: 8 bits 372 [m68k] initiator A1,A0: 01 373 [gen] responder port size: 32 bits 374 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 375 (code 1.1.4.1, OP3 lane 2): */ 376 /* D7-D0 */ TME_BUS_LANE_ABORT, 377 /* D15-D8 */ TME_BUS_LANE_ABORT, 378 /* D23-D16 */ TME_BUS_LANE_ABORT, 379 /* D31-D24 */ TME_BUS_LANE_ABORT, 380 381 /* [m68k] initiator maximum cycle size: 8 bits 382 [m68k] initiator A1,A0: 01 383 [gen] responder port size: 32 bits 384 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 385 (code 1.1.4.2, OP3 lane 2): */ 386 /* D7-D0 */ TME_BUS_LANE_ABORT, 387 /* D15-D8 */ TME_BUS_LANE_ABORT, 388 /* D23-D16 */ TME_BUS_LANE_ABORT, 389 /* D31-D24 */ TME_BUS_LANE_ABORT, 390 391 /* [m68k] initiator maximum cycle size: 8 bits 392 [m68k] initiator A1,A0: 01 393 [gen] responder port size: 32 bits 394 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 395 (code 1.1.4.3, OP3 lane 2): */ 396 /* D7-D0 */ TME_BUS_LANE_ABORT, 397 /* D15-D8 */ TME_BUS_LANE_ABORT, 398 /* D23-D16 */ TME_BUS_LANE_ABORT, 399 /* D31-D24 */ TME_BUS_LANE_ABORT, 400 401 /* [m68k] initiator maximum cycle size: 8 bits 402 [m68k] initiator A1,A0: 10 403 [gen] responder port size: 8 bits 404 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 405 (code 1.2.1.0, OP3 lane 3): */ 406 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 407 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 408 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 409 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 410 411 /* [m68k] initiator maximum cycle size: 8 bits 412 [m68k] initiator A1,A0: 10 413 [gen] responder port size: 8 bits 414 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 415 (code 1.2.1.1, OP3 lane 3): */ 416 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 417 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 418 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 419 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 420 421 /* [m68k] initiator maximum cycle size: 8 bits 422 [m68k] initiator A1,A0: 10 423 [gen] responder port size: 8 bits 424 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 425 (code 1.2.1.2, OP3 lane 3): */ 426 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 427 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 428 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 429 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 430 431 /* [m68k] initiator maximum cycle size: 8 bits 432 [m68k] initiator A1,A0: 10 433 [gen] responder port size: 8 bits 434 [gen] responder port least lane: 3 (lanes D31-D24) 435 (code 1.2.1.3, OP3 lane 3): */ 436 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 437 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 438 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 439 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 440 441 /* [m68k] initiator maximum cycle size: 8 bits 442 [m68k] initiator A1,A0: 10 443 [gen] responder port size: 16 bits 444 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 445 (code 1.2.2.0, OP3 lane 3): */ 446 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 447 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 448 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 449 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 450 451 /* [m68k] initiator maximum cycle size: 8 bits 452 [m68k] initiator A1,A0: 10 453 [gen] responder port size: 16 bits 454 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 455 (code 1.2.2.1, OP3 lane 3): */ 456 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 457 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 458 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 459 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 460 461 /* [m68k] initiator maximum cycle size: 8 bits 462 [m68k] initiator A1,A0: 10 463 [gen] responder port size: 16 bits 464 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 465 (code 1.2.2.2, OP3 lane 3): */ 466 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 467 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 468 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 469 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 470 471 /* [m68k] initiator maximum cycle size: 8 bits 472 [m68k] initiator A1,A0: 10 473 [gen] responder port size: 16 bits 474 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 475 (code 1.2.2.3, OP3 lane 3): */ 476 /* D7-D0 */ TME_BUS_LANE_ABORT, 477 /* D15-D8 */ TME_BUS_LANE_ABORT, 478 /* D23-D16 */ TME_BUS_LANE_ABORT, 479 /* D31-D24 */ TME_BUS_LANE_ABORT, 480 481 /* [m68k] initiator maximum cycle size: 8 bits 482 [m68k] initiator A1,A0: 10 483 [gen] responder port size: 32 bits 484 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 485 (code 1.2.4.0, OP3 lane 1): */ 486 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 487 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 488 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 489 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 490 491 /* [m68k] initiator maximum cycle size: 8 bits 492 [m68k] initiator A1,A0: 10 493 [gen] responder port size: 32 bits 494 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 495 (code 1.2.4.1, OP3 lane 1): */ 496 /* D7-D0 */ TME_BUS_LANE_ABORT, 497 /* D15-D8 */ TME_BUS_LANE_ABORT, 498 /* D23-D16 */ TME_BUS_LANE_ABORT, 499 /* D31-D24 */ TME_BUS_LANE_ABORT, 500 501 /* [m68k] initiator maximum cycle size: 8 bits 502 [m68k] initiator A1,A0: 10 503 [gen] responder port size: 32 bits 504 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 505 (code 1.2.4.2, OP3 lane 1): */ 506 /* D7-D0 */ TME_BUS_LANE_ABORT, 507 /* D15-D8 */ TME_BUS_LANE_ABORT, 508 /* D23-D16 */ TME_BUS_LANE_ABORT, 509 /* D31-D24 */ TME_BUS_LANE_ABORT, 510 511 /* [m68k] initiator maximum cycle size: 8 bits 512 [m68k] initiator A1,A0: 10 513 [gen] responder port size: 32 bits 514 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 515 (code 1.2.4.3, OP3 lane 1): */ 516 /* D7-D0 */ TME_BUS_LANE_ABORT, 517 /* D15-D8 */ TME_BUS_LANE_ABORT, 518 /* D23-D16 */ TME_BUS_LANE_ABORT, 519 /* D31-D24 */ TME_BUS_LANE_ABORT, 520 521 /* [m68k] initiator maximum cycle size: 8 bits 522 [m68k] initiator A1,A0: 11 523 [gen] responder port size: 8 bits 524 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 525 (code 1.3.1.0, OP3 lane 3): */ 526 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 527 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 528 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 529 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 530 531 /* [m68k] initiator maximum cycle size: 8 bits 532 [m68k] initiator A1,A0: 11 533 [gen] responder port size: 8 bits 534 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 535 (code 1.3.1.1, OP3 lane 3): */ 536 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 537 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 538 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 539 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 540 541 /* [m68k] initiator maximum cycle size: 8 bits 542 [m68k] initiator A1,A0: 11 543 [gen] responder port size: 8 bits 544 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 545 (code 1.3.1.2, OP3 lane 3): */ 546 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 547 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 548 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 549 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 550 551 /* [m68k] initiator maximum cycle size: 8 bits 552 [m68k] initiator A1,A0: 11 553 [gen] responder port size: 8 bits 554 [gen] responder port least lane: 3 (lanes D31-D24) 555 (code 1.3.1.3, OP3 lane 3): */ 556 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 557 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 558 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 559 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 560 561 /* [m68k] initiator maximum cycle size: 8 bits 562 [m68k] initiator A1,A0: 11 563 [gen] responder port size: 16 bits 564 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 565 (code 1.3.2.0, OP3 lane 2): */ 566 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 567 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 568 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 569 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 570 571 /* [m68k] initiator maximum cycle size: 8 bits 572 [m68k] initiator A1,A0: 11 573 [gen] responder port size: 16 bits 574 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 575 (code 1.3.2.1, OP3 lane 2): */ 576 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 577 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 578 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 579 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 580 581 /* [m68k] initiator maximum cycle size: 8 bits 582 [m68k] initiator A1,A0: 11 583 [gen] responder port size: 16 bits 584 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 585 (code 1.3.2.2, OP3 lane 2): */ 586 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 587 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 588 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 589 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 590 591 /* [m68k] initiator maximum cycle size: 8 bits 592 [m68k] initiator A1,A0: 11 593 [gen] responder port size: 16 bits 594 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 595 (code 1.3.2.3, OP3 lane 2): */ 596 /* D7-D0 */ TME_BUS_LANE_ABORT, 597 /* D15-D8 */ TME_BUS_LANE_ABORT, 598 /* D23-D16 */ TME_BUS_LANE_ABORT, 599 /* D31-D24 */ TME_BUS_LANE_ABORT, 600 601 /* [m68k] initiator maximum cycle size: 8 bits 602 [m68k] initiator A1,A0: 11 603 [gen] responder port size: 32 bits 604 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 605 (code 1.3.4.0, OP3 lane 0): */ 606 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)), 607 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 608 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 609 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ8_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 610 611 /* [m68k] initiator maximum cycle size: 8 bits 612 [m68k] initiator A1,A0: 11 613 [gen] responder port size: 32 bits 614 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 615 (code 1.3.4.1, OP3 lane 0): */ 616 /* D7-D0 */ TME_BUS_LANE_ABORT, 617 /* D15-D8 */ TME_BUS_LANE_ABORT, 618 /* D23-D16 */ TME_BUS_LANE_ABORT, 619 /* D31-D24 */ TME_BUS_LANE_ABORT, 620 621 /* [m68k] initiator maximum cycle size: 8 bits 622 [m68k] initiator A1,A0: 11 623 [gen] responder port size: 32 bits 624 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 625 (code 1.3.4.2, OP3 lane 0): */ 626 /* D7-D0 */ TME_BUS_LANE_ABORT, 627 /* D15-D8 */ TME_BUS_LANE_ABORT, 628 /* D23-D16 */ TME_BUS_LANE_ABORT, 629 /* D31-D24 */ TME_BUS_LANE_ABORT, 630 631 /* [m68k] initiator maximum cycle size: 8 bits 632 [m68k] initiator A1,A0: 11 633 [gen] responder port size: 32 bits 634 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 635 (code 1.3.4.3, OP3 lane 0): */ 636 /* D7-D0 */ TME_BUS_LANE_ABORT, 637 /* D15-D8 */ TME_BUS_LANE_ABORT, 638 /* D23-D16 */ TME_BUS_LANE_ABORT, 639 /* D31-D24 */ TME_BUS_LANE_ABORT, 640 641 /* [m68k] initiator maximum cycle size: 16 bits 642 [m68k] initiator A1,A0: 00 643 [gen] responder port size: 8 bits 644 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 645 (code 2.0.1.0, OP3 lane 2): */ 646 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 647 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 648 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 649 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 650 651 /* [m68k] initiator maximum cycle size: 16 bits 652 [m68k] initiator A1,A0: 00 653 [gen] responder port size: 8 bits 654 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 655 (code 2.0.1.1, OP3 lane 2): */ 656 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 657 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 658 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 659 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 660 661 /* [m68k] initiator maximum cycle size: 16 bits 662 [m68k] initiator A1,A0: 00 663 [gen] responder port size: 8 bits 664 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 665 (code 2.0.1.2, OP3 lane 2): */ 666 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 667 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 668 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 669 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 670 671 /* [m68k] initiator maximum cycle size: 16 bits 672 [m68k] initiator A1,A0: 00 673 [gen] responder port size: 8 bits 674 [gen] responder port least lane: 3 (lanes D31-D24) 675 (code 2.0.1.3, OP3 lane 2): */ 676 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 677 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 678 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 679 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 680 681 /* [m68k] initiator maximum cycle size: 16 bits 682 [m68k] initiator A1,A0: 00 683 [gen] responder port size: 16 bits 684 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 685 (code 2.0.2.0, OP3 lane 2): */ 686 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 687 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 688 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 689 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 690 691 /* [m68k] initiator maximum cycle size: 16 bits 692 [m68k] initiator A1,A0: 00 693 [gen] responder port size: 16 bits 694 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 695 (code 2.0.2.1, OP3 lane 2): */ 696 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 697 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 698 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 699 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 700 701 /* [m68k] initiator maximum cycle size: 16 bits 702 [m68k] initiator A1,A0: 00 703 [gen] responder port size: 16 bits 704 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 705 (code 2.0.2.2, OP3 lane 2): */ 706 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 707 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 708 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 709 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 710 711 /* [m68k] initiator maximum cycle size: 16 bits 712 [m68k] initiator A1,A0: 00 713 [gen] responder port size: 16 bits 714 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 715 (code 2.0.2.3, OP3 lane 2): */ 716 /* D7-D0 */ TME_BUS_LANE_ABORT, 717 /* D15-D8 */ TME_BUS_LANE_ABORT, 718 /* D23-D16 */ TME_BUS_LANE_ABORT, 719 /* D31-D24 */ TME_BUS_LANE_ABORT, 720 721 /* [m68k] initiator maximum cycle size: 16 bits 722 [m68k] initiator A1,A0: 00 723 [gen] responder port size: 32 bits 724 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 725 (code 2.0.4.0, OP3 lane 2): */ 726 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 727 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 728 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 729 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 730 731 /* [m68k] initiator maximum cycle size: 16 bits 732 [m68k] initiator A1,A0: 00 733 [gen] responder port size: 32 bits 734 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 735 (code 2.0.4.1, OP3 lane 2): */ 736 /* D7-D0 */ TME_BUS_LANE_ABORT, 737 /* D15-D8 */ TME_BUS_LANE_ABORT, 738 /* D23-D16 */ TME_BUS_LANE_ABORT, 739 /* D31-D24 */ TME_BUS_LANE_ABORT, 740 741 /* [m68k] initiator maximum cycle size: 16 bits 742 [m68k] initiator A1,A0: 00 743 [gen] responder port size: 32 bits 744 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 745 (code 2.0.4.2, OP3 lane 2): */ 746 /* D7-D0 */ TME_BUS_LANE_ABORT, 747 /* D15-D8 */ TME_BUS_LANE_ABORT, 748 /* D23-D16 */ TME_BUS_LANE_ABORT, 749 /* D31-D24 */ TME_BUS_LANE_ABORT, 750 751 /* [m68k] initiator maximum cycle size: 16 bits 752 [m68k] initiator A1,A0: 00 753 [gen] responder port size: 32 bits 754 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 755 (code 2.0.4.3, OP3 lane 2): */ 756 /* D7-D0 */ TME_BUS_LANE_ABORT, 757 /* D15-D8 */ TME_BUS_LANE_ABORT, 758 /* D23-D16 */ TME_BUS_LANE_ABORT, 759 /* D31-D24 */ TME_BUS_LANE_ABORT, 760 761 /* [m68k] initiator maximum cycle size: 16 bits 762 [m68k] initiator A1,A0: 01 763 [gen] responder port size: 8 bits 764 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 765 (code 2.1.1.0, OP3 lane 2): */ 766 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 767 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 768 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 769 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 770 771 /* [m68k] initiator maximum cycle size: 16 bits 772 [m68k] initiator A1,A0: 01 773 [gen] responder port size: 8 bits 774 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 775 (code 2.1.1.1, OP3 lane 2): */ 776 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 777 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 778 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 779 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 780 781 /* [m68k] initiator maximum cycle size: 16 bits 782 [m68k] initiator A1,A0: 01 783 [gen] responder port size: 8 bits 784 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 785 (code 2.1.1.2, OP3 lane 2): */ 786 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 787 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 788 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 789 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 790 791 /* [m68k] initiator maximum cycle size: 16 bits 792 [m68k] initiator A1,A0: 01 793 [gen] responder port size: 8 bits 794 [gen] responder port least lane: 3 (lanes D31-D24) 795 (code 2.1.1.3, OP3 lane 2): */ 796 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 797 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 798 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 799 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 800 801 /* [m68k] initiator maximum cycle size: 16 bits 802 [m68k] initiator A1,A0: 01 803 [gen] responder port size: 16 bits 804 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 805 (code 2.1.2.0, OP3 lane 1): */ 806 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 807 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 808 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 809 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 810 811 /* [m68k] initiator maximum cycle size: 16 bits 812 [m68k] initiator A1,A0: 01 813 [gen] responder port size: 16 bits 814 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 815 (code 2.1.2.1, OP3 lane 1): */ 816 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 817 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 818 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 819 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 820 821 /* [m68k] initiator maximum cycle size: 16 bits 822 [m68k] initiator A1,A0: 01 823 [gen] responder port size: 16 bits 824 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 825 (code 2.1.2.2, OP3 lane 1): */ 826 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 827 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 828 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 829 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 830 831 /* [m68k] initiator maximum cycle size: 16 bits 832 [m68k] initiator A1,A0: 01 833 [gen] responder port size: 16 bits 834 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 835 (code 2.1.2.3, OP3 lane 1): */ 836 /* D7-D0 */ TME_BUS_LANE_ABORT, 837 /* D15-D8 */ TME_BUS_LANE_ABORT, 838 /* D23-D16 */ TME_BUS_LANE_ABORT, 839 /* D31-D24 */ TME_BUS_LANE_ABORT, 840 841 /* [m68k] initiator maximum cycle size: 16 bits 842 [m68k] initiator A1,A0: 01 843 [gen] responder port size: 32 bits 844 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 845 (code 2.1.4.0, OP3 lane 1): */ 846 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 847 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 848 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 849 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 850 851 /* [m68k] initiator maximum cycle size: 16 bits 852 [m68k] initiator A1,A0: 01 853 [gen] responder port size: 32 bits 854 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 855 (code 2.1.4.1, OP3 lane 1): */ 856 /* D7-D0 */ TME_BUS_LANE_ABORT, 857 /* D15-D8 */ TME_BUS_LANE_ABORT, 858 /* D23-D16 */ TME_BUS_LANE_ABORT, 859 /* D31-D24 */ TME_BUS_LANE_ABORT, 860 861 /* [m68k] initiator maximum cycle size: 16 bits 862 [m68k] initiator A1,A0: 01 863 [gen] responder port size: 32 bits 864 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 865 (code 2.1.4.2, OP3 lane 1): */ 866 /* D7-D0 */ TME_BUS_LANE_ABORT, 867 /* D15-D8 */ TME_BUS_LANE_ABORT, 868 /* D23-D16 */ TME_BUS_LANE_ABORT, 869 /* D31-D24 */ TME_BUS_LANE_ABORT, 870 871 /* [m68k] initiator maximum cycle size: 16 bits 872 [m68k] initiator A1,A0: 01 873 [gen] responder port size: 32 bits 874 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 875 (code 2.1.4.3, OP3 lane 1): */ 876 /* D7-D0 */ TME_BUS_LANE_ABORT, 877 /* D15-D8 */ TME_BUS_LANE_ABORT, 878 /* D23-D16 */ TME_BUS_LANE_ABORT, 879 /* D31-D24 */ TME_BUS_LANE_ABORT, 880 881 /* [m68k] initiator maximum cycle size: 16 bits 882 [m68k] initiator A1,A0: 10 883 [gen] responder port size: 8 bits 884 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 885 (code 2.2.1.0, OP3 lane 2): */ 886 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 887 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 888 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 889 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 890 891 /* [m68k] initiator maximum cycle size: 16 bits 892 [m68k] initiator A1,A0: 10 893 [gen] responder port size: 8 bits 894 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 895 (code 2.2.1.1, OP3 lane 2): */ 896 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 897 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 898 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 899 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 900 901 /* [m68k] initiator maximum cycle size: 16 bits 902 [m68k] initiator A1,A0: 10 903 [gen] responder port size: 8 bits 904 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 905 (code 2.2.1.2, OP3 lane 2): */ 906 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 907 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 908 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 909 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 910 911 /* [m68k] initiator maximum cycle size: 16 bits 912 [m68k] initiator A1,A0: 10 913 [gen] responder port size: 8 bits 914 [gen] responder port least lane: 3 (lanes D31-D24) 915 (code 2.2.1.3, OP3 lane 2): */ 916 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 917 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 918 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 919 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 920 921 /* [m68k] initiator maximum cycle size: 16 bits 922 [m68k] initiator A1,A0: 10 923 [gen] responder port size: 16 bits 924 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 925 (code 2.2.2.0, OP3 lane 2): */ 926 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 927 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 928 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 929 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 930 931 /* [m68k] initiator maximum cycle size: 16 bits 932 [m68k] initiator A1,A0: 10 933 [gen] responder port size: 16 bits 934 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 935 (code 2.2.2.1, OP3 lane 2): */ 936 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 937 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 938 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 939 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 940 941 /* [m68k] initiator maximum cycle size: 16 bits 942 [m68k] initiator A1,A0: 10 943 [gen] responder port size: 16 bits 944 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 945 (code 2.2.2.2, OP3 lane 2): */ 946 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 947 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 948 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 949 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 950 951 /* [m68k] initiator maximum cycle size: 16 bits 952 [m68k] initiator A1,A0: 10 953 [gen] responder port size: 16 bits 954 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 955 (code 2.2.2.3, OP3 lane 2): */ 956 /* D7-D0 */ TME_BUS_LANE_ABORT, 957 /* D15-D8 */ TME_BUS_LANE_ABORT, 958 /* D23-D16 */ TME_BUS_LANE_ABORT, 959 /* D31-D24 */ TME_BUS_LANE_ABORT, 960 961 /* [m68k] initiator maximum cycle size: 16 bits 962 [m68k] initiator A1,A0: 10 963 [gen] responder port size: 32 bits 964 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 965 (code 2.2.4.0, OP3 lane 0): */ 966 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)), 967 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 968 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 969 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 970 971 /* [m68k] initiator maximum cycle size: 16 bits 972 [m68k] initiator A1,A0: 10 973 [gen] responder port size: 32 bits 974 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 975 (code 2.2.4.1, OP3 lane 0): */ 976 /* D7-D0 */ TME_BUS_LANE_ABORT, 977 /* D15-D8 */ TME_BUS_LANE_ABORT, 978 /* D23-D16 */ TME_BUS_LANE_ABORT, 979 /* D31-D24 */ TME_BUS_LANE_ABORT, 980 981 /* [m68k] initiator maximum cycle size: 16 bits 982 [m68k] initiator A1,A0: 10 983 [gen] responder port size: 32 bits 984 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 985 (code 2.2.4.2, OP3 lane 0): */ 986 /* D7-D0 */ TME_BUS_LANE_ABORT, 987 /* D15-D8 */ TME_BUS_LANE_ABORT, 988 /* D23-D16 */ TME_BUS_LANE_ABORT, 989 /* D31-D24 */ TME_BUS_LANE_ABORT, 990 991 /* [m68k] initiator maximum cycle size: 16 bits 992 [m68k] initiator A1,A0: 10 993 [gen] responder port size: 32 bits 994 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 995 (code 2.2.4.3, OP3 lane 0): */ 996 /* D7-D0 */ TME_BUS_LANE_ABORT, 997 /* D15-D8 */ TME_BUS_LANE_ABORT, 998 /* D23-D16 */ TME_BUS_LANE_ABORT, 999 /* D31-D24 */ TME_BUS_LANE_ABORT, 1000 1001 /* [m68k] initiator maximum cycle size: 16 bits 1002 [m68k] initiator A1,A0: 11 1003 [gen] responder port size: 8 bits 1004 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1005 (code 2.3.1.0, OP3 lane 2): */ 1006 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1007 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1008 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1009 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1010 1011 /* [m68k] initiator maximum cycle size: 16 bits 1012 [m68k] initiator A1,A0: 11 1013 [gen] responder port size: 8 bits 1014 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1015 (code 2.3.1.1, OP3 lane 2): */ 1016 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1017 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1018 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1019 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1020 1021 /* [m68k] initiator maximum cycle size: 16 bits 1022 [m68k] initiator A1,A0: 11 1023 [gen] responder port size: 8 bits 1024 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1025 (code 2.3.1.2, OP3 lane 2): */ 1026 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1027 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1028 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1029 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1030 1031 /* [m68k] initiator maximum cycle size: 16 bits 1032 [m68k] initiator A1,A0: 11 1033 [gen] responder port size: 8 bits 1034 [gen] responder port least lane: 3 (lanes D31-D24) 1035 (code 2.3.1.3, OP3 lane 2): */ 1036 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1037 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1038 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1039 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1040 1041 /* [m68k] initiator maximum cycle size: 16 bits 1042 [m68k] initiator A1,A0: 11 1043 [gen] responder port size: 16 bits 1044 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1045 (code 2.3.2.0, OP3 lane 1): */ 1046 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1047 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1048 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1049 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1050 1051 /* [m68k] initiator maximum cycle size: 16 bits 1052 [m68k] initiator A1,A0: 11 1053 [gen] responder port size: 16 bits 1054 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1055 (code 2.3.2.1, OP3 lane 1): */ 1056 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1057 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1058 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1059 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1060 1061 /* [m68k] initiator maximum cycle size: 16 bits 1062 [m68k] initiator A1,A0: 11 1063 [gen] responder port size: 16 bits 1064 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1065 (code 2.3.2.2, OP3 lane 1): */ 1066 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1067 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1068 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1069 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1070 1071 /* [m68k] initiator maximum cycle size: 16 bits 1072 [m68k] initiator A1,A0: 11 1073 [gen] responder port size: 16 bits 1074 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1075 (code 2.3.2.3, OP3 lane 1): */ 1076 /* D7-D0 */ TME_BUS_LANE_ABORT, 1077 /* D15-D8 */ TME_BUS_LANE_ABORT, 1078 /* D23-D16 */ TME_BUS_LANE_ABORT, 1079 /* D31-D24 */ TME_BUS_LANE_ABORT, 1080 1081 /* [m68k] initiator maximum cycle size: 16 bits 1082 [m68k] initiator A1,A0: 11 1083 [gen] responder port size: 32 bits 1084 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1085 (code 2.3.4.0, OP3 lane -1): */ 1086 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)), 1087 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ16_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1088 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1089 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ16_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1090 1091 /* [m68k] initiator maximum cycle size: 16 bits 1092 [m68k] initiator A1,A0: 11 1093 [gen] responder port size: 32 bits 1094 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1095 (code 2.3.4.1, OP3 lane -1): */ 1096 /* D7-D0 */ TME_BUS_LANE_ABORT, 1097 /* D15-D8 */ TME_BUS_LANE_ABORT, 1098 /* D23-D16 */ TME_BUS_LANE_ABORT, 1099 /* D31-D24 */ TME_BUS_LANE_ABORT, 1100 1101 /* [m68k] initiator maximum cycle size: 16 bits 1102 [m68k] initiator A1,A0: 11 1103 [gen] responder port size: 32 bits 1104 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1105 (code 2.3.4.2, OP3 lane -1): */ 1106 /* D7-D0 */ TME_BUS_LANE_ABORT, 1107 /* D15-D8 */ TME_BUS_LANE_ABORT, 1108 /* D23-D16 */ TME_BUS_LANE_ABORT, 1109 /* D31-D24 */ TME_BUS_LANE_ABORT, 1110 1111 /* [m68k] initiator maximum cycle size: 16 bits 1112 [m68k] initiator A1,A0: 11 1113 [gen] responder port size: 32 bits 1114 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1115 (code 2.3.4.3, OP3 lane -1): */ 1116 /* D7-D0 */ TME_BUS_LANE_ABORT, 1117 /* D15-D8 */ TME_BUS_LANE_ABORT, 1118 /* D23-D16 */ TME_BUS_LANE_ABORT, 1119 /* D31-D24 */ TME_BUS_LANE_ABORT, 1120 1121 /* [m68k] initiator maximum cycle size: 24 bits 1122 [m68k] initiator A1,A0: 00 1123 [gen] responder port size: 8 bits 1124 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1125 (code 3.0.1.0, OP3 lane 1): */ 1126 /* D7-D0 */ TME_BUS_LANE_UNDEF | TME_BUS_LANE_WARN, 1127 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1128 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1129 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1130 1131 /* [m68k] initiator maximum cycle size: 24 bits 1132 [m68k] initiator A1,A0: 00 1133 [gen] responder port size: 8 bits 1134 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1135 (code 3.0.1.1, OP3 lane 1): */ 1136 /* D7-D0 */ TME_BUS_LANE_UNDEF, 1137 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1138 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1139 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1140 1141 /* [m68k] initiator maximum cycle size: 24 bits 1142 [m68k] initiator A1,A0: 00 1143 [gen] responder port size: 8 bits 1144 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1145 (code 3.0.1.2, OP3 lane 1): */ 1146 /* D7-D0 */ TME_BUS_LANE_UNDEF, 1147 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1148 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1149 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1150 1151 /* [m68k] initiator maximum cycle size: 24 bits 1152 [m68k] initiator A1,A0: 00 1153 [gen] responder port size: 8 bits 1154 [gen] responder port least lane: 3 (lanes D31-D24) 1155 (code 3.0.1.3, OP3 lane 1): */ 1156 /* D7-D0 */ TME_BUS_LANE_UNDEF, 1157 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1158 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1159 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1160 1161 /* [m68k] initiator maximum cycle size: 24 bits 1162 [m68k] initiator A1,A0: 00 1163 [gen] responder port size: 16 bits 1164 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1165 (code 3.0.2.0, OP3 lane 1): */ 1166 /* D7-D0 */ TME_BUS_LANE_UNDEF | TME_BUS_LANE_WARN, 1167 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1168 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1169 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1170 1171 /* [m68k] initiator maximum cycle size: 24 bits 1172 [m68k] initiator A1,A0: 00 1173 [gen] responder port size: 16 bits 1174 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1175 (code 3.0.2.1, OP3 lane 1): */ 1176 /* D7-D0 */ TME_BUS_LANE_UNDEF, 1177 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1178 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1179 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1180 1181 /* [m68k] initiator maximum cycle size: 24 bits 1182 [m68k] initiator A1,A0: 00 1183 [gen] responder port size: 16 bits 1184 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1185 (code 3.0.2.2, OP3 lane 1): */ 1186 /* D7-D0 */ TME_BUS_LANE_UNDEF, 1187 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1188 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1189 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1190 1191 /* [m68k] initiator maximum cycle size: 24 bits 1192 [m68k] initiator A1,A0: 00 1193 [gen] responder port size: 16 bits 1194 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1195 (code 3.0.2.3, OP3 lane 1): */ 1196 /* D7-D0 */ TME_BUS_LANE_ABORT, 1197 /* D15-D8 */ TME_BUS_LANE_ABORT, 1198 /* D23-D16 */ TME_BUS_LANE_ABORT, 1199 /* D31-D24 */ TME_BUS_LANE_ABORT, 1200 1201 /* [m68k] initiator maximum cycle size: 24 bits 1202 [m68k] initiator A1,A0: 00 1203 [gen] responder port size: 32 bits 1204 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1205 (code 3.0.4.0, OP3 lane 1): */ 1206 /* D7-D0 */ TME_BUS_LANE_UNDEF, 1207 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)), 1208 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1209 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1210 1211 /* [m68k] initiator maximum cycle size: 24 bits 1212 [m68k] initiator A1,A0: 00 1213 [gen] responder port size: 32 bits 1214 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1215 (code 3.0.4.1, OP3 lane 1): */ 1216 /* D7-D0 */ TME_BUS_LANE_ABORT, 1217 /* D15-D8 */ TME_BUS_LANE_ABORT, 1218 /* D23-D16 */ TME_BUS_LANE_ABORT, 1219 /* D31-D24 */ TME_BUS_LANE_ABORT, 1220 1221 /* [m68k] initiator maximum cycle size: 24 bits 1222 [m68k] initiator A1,A0: 00 1223 [gen] responder port size: 32 bits 1224 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1225 (code 3.0.4.2, OP3 lane 1): */ 1226 /* D7-D0 */ TME_BUS_LANE_ABORT, 1227 /* D15-D8 */ TME_BUS_LANE_ABORT, 1228 /* D23-D16 */ TME_BUS_LANE_ABORT, 1229 /* D31-D24 */ TME_BUS_LANE_ABORT, 1230 1231 /* [m68k] initiator maximum cycle size: 24 bits 1232 [m68k] initiator A1,A0: 00 1233 [gen] responder port size: 32 bits 1234 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1235 (code 3.0.4.3, OP3 lane 1): */ 1236 /* D7-D0 */ TME_BUS_LANE_ABORT, 1237 /* D15-D8 */ TME_BUS_LANE_ABORT, 1238 /* D23-D16 */ TME_BUS_LANE_ABORT, 1239 /* D31-D24 */ TME_BUS_LANE_ABORT, 1240 1241 /* [m68k] initiator maximum cycle size: 24 bits 1242 [m68k] initiator A1,A0: 01 1243 [gen] responder port size: 8 bits 1244 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1245 (code 3.1.1.0, OP3 lane 1): */ 1246 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1247 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1248 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1249 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1250 1251 /* [m68k] initiator maximum cycle size: 24 bits 1252 [m68k] initiator A1,A0: 01 1253 [gen] responder port size: 8 bits 1254 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1255 (code 3.1.1.1, OP3 lane 1): */ 1256 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1257 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1258 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1259 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1260 1261 /* [m68k] initiator maximum cycle size: 24 bits 1262 [m68k] initiator A1,A0: 01 1263 [gen] responder port size: 8 bits 1264 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1265 (code 3.1.1.2, OP3 lane 1): */ 1266 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1267 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1268 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1269 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1270 1271 /* [m68k] initiator maximum cycle size: 24 bits 1272 [m68k] initiator A1,A0: 01 1273 [gen] responder port size: 8 bits 1274 [gen] responder port least lane: 3 (lanes D31-D24) 1275 (code 3.1.1.3, OP3 lane 1): */ 1276 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1277 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1278 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1279 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1280 1281 /* [m68k] initiator maximum cycle size: 24 bits 1282 [m68k] initiator A1,A0: 01 1283 [gen] responder port size: 16 bits 1284 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1285 (code 3.1.2.0, OP3 lane 0): */ 1286 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1287 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1288 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1289 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1290 1291 /* [m68k] initiator maximum cycle size: 24 bits 1292 [m68k] initiator A1,A0: 01 1293 [gen] responder port size: 16 bits 1294 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1295 (code 3.1.2.1, OP3 lane 0): */ 1296 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1297 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1298 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1299 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1300 1301 /* [m68k] initiator maximum cycle size: 24 bits 1302 [m68k] initiator A1,A0: 01 1303 [gen] responder port size: 16 bits 1304 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1305 (code 3.1.2.2, OP3 lane 0): */ 1306 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1307 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1308 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1309 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1310 1311 /* [m68k] initiator maximum cycle size: 24 bits 1312 [m68k] initiator A1,A0: 01 1313 [gen] responder port size: 16 bits 1314 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1315 (code 3.1.2.3, OP3 lane 0): */ 1316 /* D7-D0 */ TME_BUS_LANE_ABORT, 1317 /* D15-D8 */ TME_BUS_LANE_ABORT, 1318 /* D23-D16 */ TME_BUS_LANE_ABORT, 1319 /* D31-D24 */ TME_BUS_LANE_ABORT, 1320 1321 /* [m68k] initiator maximum cycle size: 24 bits 1322 [m68k] initiator A1,A0: 01 1323 [gen] responder port size: 32 bits 1324 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1325 (code 3.1.4.0, OP3 lane 0): */ 1326 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(3)), 1327 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1328 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1329 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1330 1331 /* [m68k] initiator maximum cycle size: 24 bits 1332 [m68k] initiator A1,A0: 01 1333 [gen] responder port size: 32 bits 1334 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1335 (code 3.1.4.1, OP3 lane 0): */ 1336 /* D7-D0 */ TME_BUS_LANE_ABORT, 1337 /* D15-D8 */ TME_BUS_LANE_ABORT, 1338 /* D23-D16 */ TME_BUS_LANE_ABORT, 1339 /* D31-D24 */ TME_BUS_LANE_ABORT, 1340 1341 /* [m68k] initiator maximum cycle size: 24 bits 1342 [m68k] initiator A1,A0: 01 1343 [gen] responder port size: 32 bits 1344 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1345 (code 3.1.4.2, OP3 lane 0): */ 1346 /* D7-D0 */ TME_BUS_LANE_ABORT, 1347 /* D15-D8 */ TME_BUS_LANE_ABORT, 1348 /* D23-D16 */ TME_BUS_LANE_ABORT, 1349 /* D31-D24 */ TME_BUS_LANE_ABORT, 1350 1351 /* [m68k] initiator maximum cycle size: 24 bits 1352 [m68k] initiator A1,A0: 01 1353 [gen] responder port size: 32 bits 1354 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1355 (code 3.1.4.3, OP3 lane 0): */ 1356 /* D7-D0 */ TME_BUS_LANE_ABORT, 1357 /* D15-D8 */ TME_BUS_LANE_ABORT, 1358 /* D23-D16 */ TME_BUS_LANE_ABORT, 1359 /* D31-D24 */ TME_BUS_LANE_ABORT, 1360 1361 /* [m68k] initiator maximum cycle size: 24 bits 1362 [m68k] initiator A1,A0: 10 1363 [gen] responder port size: 8 bits 1364 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1365 (code 3.2.1.0, OP3 lane 1): */ 1366 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1367 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1368 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1369 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1370 1371 /* [m68k] initiator maximum cycle size: 24 bits 1372 [m68k] initiator A1,A0: 10 1373 [gen] responder port size: 8 bits 1374 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1375 (code 3.2.1.1, OP3 lane 1): */ 1376 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1377 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1378 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1379 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1380 1381 /* [m68k] initiator maximum cycle size: 24 bits 1382 [m68k] initiator A1,A0: 10 1383 [gen] responder port size: 8 bits 1384 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1385 (code 3.2.1.2, OP3 lane 1): */ 1386 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1387 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1388 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1389 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1390 1391 /* [m68k] initiator maximum cycle size: 24 bits 1392 [m68k] initiator A1,A0: 10 1393 [gen] responder port size: 8 bits 1394 [gen] responder port least lane: 3 (lanes D31-D24) 1395 (code 3.2.1.3, OP3 lane 1): */ 1396 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1397 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1398 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1399 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1400 1401 /* [m68k] initiator maximum cycle size: 24 bits 1402 [m68k] initiator A1,A0: 10 1403 [gen] responder port size: 16 bits 1404 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1405 (code 3.2.2.0, OP3 lane 1): */ 1406 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1407 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1408 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1409 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1410 1411 /* [m68k] initiator maximum cycle size: 24 bits 1412 [m68k] initiator A1,A0: 10 1413 [gen] responder port size: 16 bits 1414 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1415 (code 3.2.2.1, OP3 lane 1): */ 1416 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1417 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1418 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1419 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1420 1421 /* [m68k] initiator maximum cycle size: 24 bits 1422 [m68k] initiator A1,A0: 10 1423 [gen] responder port size: 16 bits 1424 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1425 (code 3.2.2.2, OP3 lane 1): */ 1426 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1427 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1428 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1429 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1430 1431 /* [m68k] initiator maximum cycle size: 24 bits 1432 [m68k] initiator A1,A0: 10 1433 [gen] responder port size: 16 bits 1434 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1435 (code 3.2.2.3, OP3 lane 1): */ 1436 /* D7-D0 */ TME_BUS_LANE_ABORT, 1437 /* D15-D8 */ TME_BUS_LANE_ABORT, 1438 /* D23-D16 */ TME_BUS_LANE_ABORT, 1439 /* D31-D24 */ TME_BUS_LANE_ABORT, 1440 1441 /* [m68k] initiator maximum cycle size: 24 bits 1442 [m68k] initiator A1,A0: 10 1443 [gen] responder port size: 32 bits 1444 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1445 (code 3.2.4.0, OP3 lane -1): */ 1446 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)), 1447 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1448 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1449 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1450 1451 /* [m68k] initiator maximum cycle size: 24 bits 1452 [m68k] initiator A1,A0: 10 1453 [gen] responder port size: 32 bits 1454 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1455 (code 3.2.4.1, OP3 lane -1): */ 1456 /* D7-D0 */ TME_BUS_LANE_ABORT, 1457 /* D15-D8 */ TME_BUS_LANE_ABORT, 1458 /* D23-D16 */ TME_BUS_LANE_ABORT, 1459 /* D31-D24 */ TME_BUS_LANE_ABORT, 1460 1461 /* [m68k] initiator maximum cycle size: 24 bits 1462 [m68k] initiator A1,A0: 10 1463 [gen] responder port size: 32 bits 1464 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1465 (code 3.2.4.2, OP3 lane -1): */ 1466 /* D7-D0 */ TME_BUS_LANE_ABORT, 1467 /* D15-D8 */ TME_BUS_LANE_ABORT, 1468 /* D23-D16 */ TME_BUS_LANE_ABORT, 1469 /* D31-D24 */ TME_BUS_LANE_ABORT, 1470 1471 /* [m68k] initiator maximum cycle size: 24 bits 1472 [m68k] initiator A1,A0: 10 1473 [gen] responder port size: 32 bits 1474 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1475 (code 3.2.4.3, OP3 lane -1): */ 1476 /* D7-D0 */ TME_BUS_LANE_ABORT, 1477 /* D15-D8 */ TME_BUS_LANE_ABORT, 1478 /* D23-D16 */ TME_BUS_LANE_ABORT, 1479 /* D31-D24 */ TME_BUS_LANE_ABORT, 1480 1481 /* [m68k] initiator maximum cycle size: 24 bits 1482 [m68k] initiator A1,A0: 11 1483 [gen] responder port size: 8 bits 1484 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1485 (code 3.3.1.0, OP3 lane 1): */ 1486 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1487 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1488 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1489 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1490 1491 /* [m68k] initiator maximum cycle size: 24 bits 1492 [m68k] initiator A1,A0: 11 1493 [gen] responder port size: 8 bits 1494 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1495 (code 3.3.1.1, OP3 lane 1): */ 1496 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1497 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1498 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1499 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1500 1501 /* [m68k] initiator maximum cycle size: 24 bits 1502 [m68k] initiator A1,A0: 11 1503 [gen] responder port size: 8 bits 1504 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1505 (code 3.3.1.2, OP3 lane 1): */ 1506 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1507 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1508 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1509 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1510 1511 /* [m68k] initiator maximum cycle size: 24 bits 1512 [m68k] initiator A1,A0: 11 1513 [gen] responder port size: 8 bits 1514 [gen] responder port least lane: 3 (lanes D31-D24) 1515 (code 3.3.1.3, OP3 lane 1): */ 1516 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1517 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1518 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1519 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1520 1521 /* [m68k] initiator maximum cycle size: 24 bits 1522 [m68k] initiator A1,A0: 11 1523 [gen] responder port size: 16 bits 1524 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1525 (code 3.3.2.0, OP3 lane 0): */ 1526 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1527 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1528 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1529 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1530 1531 /* [m68k] initiator maximum cycle size: 24 bits 1532 [m68k] initiator A1,A0: 11 1533 [gen] responder port size: 16 bits 1534 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1535 (code 3.3.2.1, OP3 lane 0): */ 1536 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1537 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1538 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1539 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1540 1541 /* [m68k] initiator maximum cycle size: 24 bits 1542 [m68k] initiator A1,A0: 11 1543 [gen] responder port size: 16 bits 1544 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1545 (code 3.3.2.2, OP3 lane 0): */ 1546 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1547 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1548 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1549 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1550 1551 /* [m68k] initiator maximum cycle size: 24 bits 1552 [m68k] initiator A1,A0: 11 1553 [gen] responder port size: 16 bits 1554 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1555 (code 3.3.2.3, OP3 lane 0): */ 1556 /* D7-D0 */ TME_BUS_LANE_ABORT, 1557 /* D15-D8 */ TME_BUS_LANE_ABORT, 1558 /* D23-D16 */ TME_BUS_LANE_ABORT, 1559 /* D31-D24 */ TME_BUS_LANE_ABORT, 1560 1561 /* [m68k] initiator maximum cycle size: 24 bits 1562 [m68k] initiator A1,A0: 11 1563 [gen] responder port size: 32 bits 1564 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1565 (code 3.3.4.0, OP3 lane -2): */ 1566 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)), 1567 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ24_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1568 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1569 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ24_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1570 1571 /* [m68k] initiator maximum cycle size: 24 bits 1572 [m68k] initiator A1,A0: 11 1573 [gen] responder port size: 32 bits 1574 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1575 (code 3.3.4.1, OP3 lane -2): */ 1576 /* D7-D0 */ TME_BUS_LANE_ABORT, 1577 /* D15-D8 */ TME_BUS_LANE_ABORT, 1578 /* D23-D16 */ TME_BUS_LANE_ABORT, 1579 /* D31-D24 */ TME_BUS_LANE_ABORT, 1580 1581 /* [m68k] initiator maximum cycle size: 24 bits 1582 [m68k] initiator A1,A0: 11 1583 [gen] responder port size: 32 bits 1584 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1585 (code 3.3.4.2, OP3 lane -2): */ 1586 /* D7-D0 */ TME_BUS_LANE_ABORT, 1587 /* D15-D8 */ TME_BUS_LANE_ABORT, 1588 /* D23-D16 */ TME_BUS_LANE_ABORT, 1589 /* D31-D24 */ TME_BUS_LANE_ABORT, 1590 1591 /* [m68k] initiator maximum cycle size: 24 bits 1592 [m68k] initiator A1,A0: 11 1593 [gen] responder port size: 32 bits 1594 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1595 (code 3.3.4.3, OP3 lane -2): */ 1596 /* D7-D0 */ TME_BUS_LANE_ABORT, 1597 /* D15-D8 */ TME_BUS_LANE_ABORT, 1598 /* D23-D16 */ TME_BUS_LANE_ABORT, 1599 /* D31-D24 */ TME_BUS_LANE_ABORT, 1600 1601 /* [m68k] initiator maximum cycle size: 32 bits 1602 [m68k] initiator A1,A0: 00 1603 [gen] responder port size: 8 bits 1604 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1605 (code 4.0.1.0, OP3 lane 0): */ 1606 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1607 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1608 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1609 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1610 1611 /* [m68k] initiator maximum cycle size: 32 bits 1612 [m68k] initiator A1,A0: 00 1613 [gen] responder port size: 8 bits 1614 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1615 (code 4.0.1.1, OP3 lane 0): */ 1616 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1617 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1618 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1619 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1620 1621 /* [m68k] initiator maximum cycle size: 32 bits 1622 [m68k] initiator A1,A0: 00 1623 [gen] responder port size: 8 bits 1624 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1625 (code 4.0.1.2, OP3 lane 0): */ 1626 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1627 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1628 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1629 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1630 1631 /* [m68k] initiator maximum cycle size: 32 bits 1632 [m68k] initiator A1,A0: 00 1633 [gen] responder port size: 8 bits 1634 [gen] responder port least lane: 3 (lanes D31-D24) 1635 (code 4.0.1.3, OP3 lane 0): */ 1636 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1637 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1638 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1639 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1640 1641 /* [m68k] initiator maximum cycle size: 32 bits 1642 [m68k] initiator A1,A0: 00 1643 [gen] responder port size: 16 bits 1644 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1645 (code 4.0.2.0, OP3 lane 0): */ 1646 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1647 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1648 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1649 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1650 1651 /* [m68k] initiator maximum cycle size: 32 bits 1652 [m68k] initiator A1,A0: 00 1653 [gen] responder port size: 16 bits 1654 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1655 (code 4.0.2.1, OP3 lane 0): */ 1656 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1657 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1658 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1659 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1660 1661 /* [m68k] initiator maximum cycle size: 32 bits 1662 [m68k] initiator A1,A0: 00 1663 [gen] responder port size: 16 bits 1664 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1665 (code 4.0.2.2, OP3 lane 0): */ 1666 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1667 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1668 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1669 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1670 1671 /* [m68k] initiator maximum cycle size: 32 bits 1672 [m68k] initiator A1,A0: 00 1673 [gen] responder port size: 16 bits 1674 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1675 (code 4.0.2.3, OP3 lane 0): */ 1676 /* D7-D0 */ TME_BUS_LANE_ABORT, 1677 /* D15-D8 */ TME_BUS_LANE_ABORT, 1678 /* D23-D16 */ TME_BUS_LANE_ABORT, 1679 /* D31-D24 */ TME_BUS_LANE_ABORT, 1680 1681 /* [m68k] initiator maximum cycle size: 32 bits 1682 [m68k] initiator A1,A0: 00 1683 [gen] responder port size: 32 bits 1684 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1685 (code 4.0.4.0, OP3 lane 0): */ 1686 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(3)), 1687 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)), 1688 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1689 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1690 1691 /* [m68k] initiator maximum cycle size: 32 bits 1692 [m68k] initiator A1,A0: 00 1693 [gen] responder port size: 32 bits 1694 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1695 (code 4.0.4.1, OP3 lane 0): */ 1696 /* D7-D0 */ TME_BUS_LANE_ABORT, 1697 /* D15-D8 */ TME_BUS_LANE_ABORT, 1698 /* D23-D16 */ TME_BUS_LANE_ABORT, 1699 /* D31-D24 */ TME_BUS_LANE_ABORT, 1700 1701 /* [m68k] initiator maximum cycle size: 32 bits 1702 [m68k] initiator A1,A0: 00 1703 [gen] responder port size: 32 bits 1704 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1705 (code 4.0.4.2, OP3 lane 0): */ 1706 /* D7-D0 */ TME_BUS_LANE_ABORT, 1707 /* D15-D8 */ TME_BUS_LANE_ABORT, 1708 /* D23-D16 */ TME_BUS_LANE_ABORT, 1709 /* D31-D24 */ TME_BUS_LANE_ABORT, 1710 1711 /* [m68k] initiator maximum cycle size: 32 bits 1712 [m68k] initiator A1,A0: 00 1713 [gen] responder port size: 32 bits 1714 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1715 (code 4.0.4.3, OP3 lane 0): */ 1716 /* D7-D0 */ TME_BUS_LANE_ABORT, 1717 /* D15-D8 */ TME_BUS_LANE_ABORT, 1718 /* D23-D16 */ TME_BUS_LANE_ABORT, 1719 /* D31-D24 */ TME_BUS_LANE_ABORT, 1720 1721 /* [m68k] initiator maximum cycle size: 32 bits 1722 [m68k] initiator A1,A0: 01 1723 [gen] responder port size: 8 bits 1724 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1725 (code 4.1.1.0, OP3 lane 0): */ 1726 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1727 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1728 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1729 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1730 1731 /* [m68k] initiator maximum cycle size: 32 bits 1732 [m68k] initiator A1,A0: 01 1733 [gen] responder port size: 8 bits 1734 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1735 (code 4.1.1.1, OP3 lane 0): */ 1736 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1737 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1738 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1739 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1740 1741 /* [m68k] initiator maximum cycle size: 32 bits 1742 [m68k] initiator A1,A0: 01 1743 [gen] responder port size: 8 bits 1744 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1745 (code 4.1.1.2, OP3 lane 0): */ 1746 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1747 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1748 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1749 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1750 1751 /* [m68k] initiator maximum cycle size: 32 bits 1752 [m68k] initiator A1,A0: 01 1753 [gen] responder port size: 8 bits 1754 [gen] responder port least lane: 3 (lanes D31-D24) 1755 (code 4.1.1.3, OP3 lane 0): */ 1756 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1757 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1758 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1759 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1760 1761 /* [m68k] initiator maximum cycle size: 32 bits 1762 [m68k] initiator A1,A0: 01 1763 [gen] responder port size: 16 bits 1764 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1765 (code 4.1.2.0, OP3 lane -1): */ 1766 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1767 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1768 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1769 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1770 1771 /* [m68k] initiator maximum cycle size: 32 bits 1772 [m68k] initiator A1,A0: 01 1773 [gen] responder port size: 16 bits 1774 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1775 (code 4.1.2.1, OP3 lane -1): */ 1776 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1777 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1778 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1779 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1780 1781 /* [m68k] initiator maximum cycle size: 32 bits 1782 [m68k] initiator A1,A0: 01 1783 [gen] responder port size: 16 bits 1784 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1785 (code 4.1.2.2, OP3 lane -1): */ 1786 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1787 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1788 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1789 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1790 1791 /* [m68k] initiator maximum cycle size: 32 bits 1792 [m68k] initiator A1,A0: 01 1793 [gen] responder port size: 16 bits 1794 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1795 (code 4.1.2.3, OP3 lane -1): */ 1796 /* D7-D0 */ TME_BUS_LANE_ABORT, 1797 /* D15-D8 */ TME_BUS_LANE_ABORT, 1798 /* D23-D16 */ TME_BUS_LANE_ABORT, 1799 /* D31-D24 */ TME_BUS_LANE_ABORT, 1800 1801 /* [m68k] initiator maximum cycle size: 32 bits 1802 [m68k] initiator A1,A0: 01 1803 [gen] responder port size: 32 bits 1804 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1805 (code 4.1.4.0, OP3 lane -1): */ 1806 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(2)), 1807 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1808 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1809 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1810 1811 /* [m68k] initiator maximum cycle size: 32 bits 1812 [m68k] initiator A1,A0: 01 1813 [gen] responder port size: 32 bits 1814 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1815 (code 4.1.4.1, OP3 lane -1): */ 1816 /* D7-D0 */ TME_BUS_LANE_ABORT, 1817 /* D15-D8 */ TME_BUS_LANE_ABORT, 1818 /* D23-D16 */ TME_BUS_LANE_ABORT, 1819 /* D31-D24 */ TME_BUS_LANE_ABORT, 1820 1821 /* [m68k] initiator maximum cycle size: 32 bits 1822 [m68k] initiator A1,A0: 01 1823 [gen] responder port size: 32 bits 1824 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1825 (code 4.1.4.2, OP3 lane -1): */ 1826 /* D7-D0 */ TME_BUS_LANE_ABORT, 1827 /* D15-D8 */ TME_BUS_LANE_ABORT, 1828 /* D23-D16 */ TME_BUS_LANE_ABORT, 1829 /* D31-D24 */ TME_BUS_LANE_ABORT, 1830 1831 /* [m68k] initiator maximum cycle size: 32 bits 1832 [m68k] initiator A1,A0: 01 1833 [gen] responder port size: 32 bits 1834 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1835 (code 4.1.4.3, OP3 lane -1): */ 1836 /* D7-D0 */ TME_BUS_LANE_ABORT, 1837 /* D15-D8 */ TME_BUS_LANE_ABORT, 1838 /* D23-D16 */ TME_BUS_LANE_ABORT, 1839 /* D31-D24 */ TME_BUS_LANE_ABORT, 1840 1841 /* [m68k] initiator maximum cycle size: 32 bits 1842 [m68k] initiator A1,A0: 10 1843 [gen] responder port size: 8 bits 1844 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1845 (code 4.2.1.0, OP3 lane 0): */ 1846 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1847 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1848 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1849 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1850 1851 /* [m68k] initiator maximum cycle size: 32 bits 1852 [m68k] initiator A1,A0: 10 1853 [gen] responder port size: 8 bits 1854 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1855 (code 4.2.1.1, OP3 lane 0): */ 1856 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1857 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1858 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1859 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1860 1861 /* [m68k] initiator maximum cycle size: 32 bits 1862 [m68k] initiator A1,A0: 10 1863 [gen] responder port size: 8 bits 1864 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1865 (code 4.2.1.2, OP3 lane 0): */ 1866 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1867 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1868 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1869 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1870 1871 /* [m68k] initiator maximum cycle size: 32 bits 1872 [m68k] initiator A1,A0: 10 1873 [gen] responder port size: 8 bits 1874 [gen] responder port least lane: 3 (lanes D31-D24) 1875 (code 4.2.1.3, OP3 lane 0): */ 1876 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1877 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1878 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1879 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1880 1881 /* [m68k] initiator maximum cycle size: 32 bits 1882 [m68k] initiator A1,A0: 10 1883 [gen] responder port size: 16 bits 1884 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 1885 (code 4.2.2.0, OP3 lane 0): */ 1886 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1887 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1888 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1889 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1890 1891 /* [m68k] initiator maximum cycle size: 32 bits 1892 [m68k] initiator A1,A0: 10 1893 [gen] responder port size: 16 bits 1894 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 1895 (code 4.2.2.1, OP3 lane 0): */ 1896 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1897 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1898 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1899 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1900 1901 /* [m68k] initiator maximum cycle size: 32 bits 1902 [m68k] initiator A1,A0: 10 1903 [gen] responder port size: 16 bits 1904 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 1905 (code 4.2.2.2, OP3 lane 0): */ 1906 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1907 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1908 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1909 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1910 1911 /* [m68k] initiator maximum cycle size: 32 bits 1912 [m68k] initiator A1,A0: 10 1913 [gen] responder port size: 16 bits 1914 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 1915 (code 4.2.2.3, OP3 lane 0): */ 1916 /* D7-D0 */ TME_BUS_LANE_ABORT, 1917 /* D15-D8 */ TME_BUS_LANE_ABORT, 1918 /* D23-D16 */ TME_BUS_LANE_ABORT, 1919 /* D31-D24 */ TME_BUS_LANE_ABORT, 1920 1921 /* [m68k] initiator maximum cycle size: 32 bits 1922 [m68k] initiator A1,A0: 10 1923 [gen] responder port size: 32 bits 1924 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 1925 (code 4.2.4.0, OP3 lane -2): */ 1926 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)), 1927 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1928 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1929 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1930 1931 /* [m68k] initiator maximum cycle size: 32 bits 1932 [m68k] initiator A1,A0: 10 1933 [gen] responder port size: 32 bits 1934 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 1935 (code 4.2.4.1, OP3 lane -2): */ 1936 /* D7-D0 */ TME_BUS_LANE_ABORT, 1937 /* D15-D8 */ TME_BUS_LANE_ABORT, 1938 /* D23-D16 */ TME_BUS_LANE_ABORT, 1939 /* D31-D24 */ TME_BUS_LANE_ABORT, 1940 1941 /* [m68k] initiator maximum cycle size: 32 bits 1942 [m68k] initiator A1,A0: 10 1943 [gen] responder port size: 32 bits 1944 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 1945 (code 4.2.4.2, OP3 lane -2): */ 1946 /* D7-D0 */ TME_BUS_LANE_ABORT, 1947 /* D15-D8 */ TME_BUS_LANE_ABORT, 1948 /* D23-D16 */ TME_BUS_LANE_ABORT, 1949 /* D31-D24 */ TME_BUS_LANE_ABORT, 1950 1951 /* [m68k] initiator maximum cycle size: 32 bits 1952 [m68k] initiator A1,A0: 10 1953 [gen] responder port size: 32 bits 1954 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 1955 (code 4.2.4.3, OP3 lane -2): */ 1956 /* D7-D0 */ TME_BUS_LANE_ABORT, 1957 /* D15-D8 */ TME_BUS_LANE_ABORT, 1958 /* D23-D16 */ TME_BUS_LANE_ABORT, 1959 /* D31-D24 */ TME_BUS_LANE_ABORT, 1960 1961 /* [m68k] initiator maximum cycle size: 32 bits 1962 [m68k] initiator A1,A0: 11 1963 [gen] responder port size: 8 bits 1964 [gen] responder port least lane: 0 (lanes D7-D0 - incorrect for 32-bit m68k) 1965 (code 4.3.1.0, OP3 lane 0): */ 1966 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1967 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1968 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1969 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1970 1971 /* [m68k] initiator maximum cycle size: 32 bits 1972 [m68k] initiator A1,A0: 11 1973 [gen] responder port size: 8 bits 1974 [gen] responder port least lane: 1 (lanes D15-D8 - incorrect for 32-bit m68k) 1975 (code 4.3.1.1, OP3 lane 0): */ 1976 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1977 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1978 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1979 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1980 1981 /* [m68k] initiator maximum cycle size: 32 bits 1982 [m68k] initiator A1,A0: 11 1983 [gen] responder port size: 8 bits 1984 [gen] responder port least lane: 2 (lanes D23-D16 - incorrect for 32-bit m68k) 1985 (code 4.3.1.2, OP3 lane 0): */ 1986 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1987 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1988 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 1989 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 1990 1991 /* [m68k] initiator maximum cycle size: 32 bits 1992 [m68k] initiator A1,A0: 11 1993 [gen] responder port size: 8 bits 1994 [gen] responder port least lane: 3 (lanes D31-D24) 1995 (code 4.3.1.3, OP3 lane 0): */ 1996 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1997 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1998 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 1999 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 2000 2001 /* [m68k] initiator maximum cycle size: 32 bits 2002 [m68k] initiator A1,A0: 11 2003 [gen] responder port size: 16 bits 2004 [gen] responder port least lane: 0 (lanes D15-D8 D7-D0 - incorrect for 32-bit m68k) 2005 (code 4.3.2.0, OP3 lane -1): */ 2006 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 2007 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 2008 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 2009 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2010 2011 /* [m68k] initiator maximum cycle size: 32 bits 2012 [m68k] initiator A1,A0: 11 2013 [gen] responder port size: 16 bits 2014 [gen] responder port least lane: 1 (lanes D23-D16 D15-D8 - incorrect for 32-bit m68k) 2015 (code 4.3.2.1, OP3 lane -1): */ 2016 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2017 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE | TME_BUS_LANE_WARN, 2018 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 2019 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2020 2021 /* [m68k] initiator maximum cycle size: 32 bits 2022 [m68k] initiator A1,A0: 11 2023 [gen] responder port size: 16 bits 2024 [gen] responder port least lane: 2 (lanes D31-D24 D23-D16) 2025 (code 4.3.2.2, OP3 lane -1): */ 2026 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2027 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2028 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 2029 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2030 2031 /* [m68k] initiator maximum cycle size: 32 bits 2032 [m68k] initiator A1,A0: 11 2033 [gen] responder port size: 16 bits 2034 [gen] responder port least lane: 3 (lanes D39-D32 D31-D24 - invalid, array placeholder) 2035 (code 4.3.2.3, OP3 lane -1): */ 2036 /* D7-D0 */ TME_BUS_LANE_ABORT, 2037 /* D15-D8 */ TME_BUS_LANE_ABORT, 2038 /* D23-D16 */ TME_BUS_LANE_ABORT, 2039 /* D31-D24 */ TME_BUS_LANE_ABORT, 2040 2041 /* [m68k] initiator maximum cycle size: 32 bits 2042 [m68k] initiator A1,A0: 11 2043 [gen] responder port size: 32 bits 2044 [gen] responder port least lane: 0 (lanes D31-D24 D23-D16 D15-D8 D7-D0) 2045 (code 4.3.4.0, OP3 lane -3): */ 2046 /* D7-D0 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)), 2047 /* D15-D8 */ TME_BUS_LANE_ROUTE(SIZ32_OP(1)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2048 /* D23-D16 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2049 /* D31-D24 */ TME_BUS_LANE_ROUTE(SIZ32_OP(0)) | TME_BUS_LANE_ROUTE_WRITE_IGNORE, 2050 2051 /* [m68k] initiator maximum cycle size: 32 bits 2052 [m68k] initiator A1,A0: 11 2053 [gen] responder port size: 32 bits 2054 [gen] responder port least lane: 1 (lanes D39-D32 D31-D24 D23-D16 D15-D8 - invalid, array placeholder) 2055 (code 4.3.4.1, OP3 lane -3): */ 2056 /* D7-D0 */ TME_BUS_LANE_ABORT, 2057 /* D15-D8 */ TME_BUS_LANE_ABORT, 2058 /* D23-D16 */ TME_BUS_LANE_ABORT, 2059 /* D31-D24 */ TME_BUS_LANE_ABORT, 2060 2061 /* [m68k] initiator maximum cycle size: 32 bits 2062 [m68k] initiator A1,A0: 11 2063 [gen] responder port size: 32 bits 2064 [gen] responder port least lane: 2 (lanes D47-D40 D39-D32 D31-D24 D23-D16 - invalid, array placeholder) 2065 (code 4.3.4.2, OP3 lane -3): */ 2066 /* D7-D0 */ TME_BUS_LANE_ABORT, 2067 /* D15-D8 */ TME_BUS_LANE_ABORT, 2068 /* D23-D16 */ TME_BUS_LANE_ABORT, 2069 /* D31-D24 */ TME_BUS_LANE_ABORT, 2070 2071 /* [m68k] initiator maximum cycle size: 32 bits 2072 [m68k] initiator A1,A0: 11 2073 [gen] responder port size: 32 bits 2074 [gen] responder port least lane: 3 (lanes D55-D48 D47-D40 D39-D32 D31-D24 - invalid, array placeholder) 2075 (code 4.3.4.3, OP3 lane -3): */ 2076 /* D7-D0 */ TME_BUS_LANE_ABORT, 2077 /* D15-D8 */ TME_BUS_LANE_ABORT, 2078 /* D23-D16 */ TME_BUS_LANE_ABORT, 2079 /* D31-D24 */ TME_BUS_LANE_ABORT, 2080 }; 2081 #undef SIZ8_OP 2082 #undef SIZ16_OP 2083 #undef SIZ24_OP 2084 #undef SIZ32_OP 2085