1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_OBJECT_H__
29 #define __AMDGPU_OBJECT_H__
30
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "amdgpu_res_cursor.h"
34
35 #ifdef CONFIG_MMU_NOTIFIER
36 #include <linux/mmu_notifier.h>
37 #endif
38
39 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX
40 #define AMDGPU_BO_MAX_PLACEMENTS 3
41
42 /* BO flag to indicate a KFD userptr BO */
43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63)
44
45 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
46 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
47
48 struct amdgpu_bo_param {
49 unsigned long size;
50 int byte_align;
51 u32 bo_ptr_size;
52 u32 domain;
53 u32 preferred_domain;
54 u64 flags;
55 enum ttm_bo_type type;
56 bool no_wait_gpu;
57 struct dma_resv *resv;
58 void (*destroy)(struct ttm_buffer_object *bo);
59 /* xcp partition number plus 1, 0 means any partition */
60 int8_t xcp_id_plus1;
61 };
62
63 /* bo virtual addresses in a vm */
64 struct amdgpu_bo_va_mapping {
65 struct amdgpu_bo_va *bo_va;
66 struct list_head list;
67 struct rb_node rb;
68 uint64_t start;
69 uint64_t last;
70 uint64_t __subtree_last;
71 uint64_t offset;
72 uint64_t flags;
73 };
74
75 /* User space allocated BO in a VM */
76 struct amdgpu_bo_va {
77 struct amdgpu_vm_bo_base base;
78
79 /* protected by bo being reserved */
80 unsigned ref_count;
81
82 /* all other members protected by the VM PD being reserved */
83 struct dma_fence *last_pt_update;
84
85 /* mappings for this bo_va */
86 struct list_head invalids;
87 struct list_head valids;
88
89 /* If the mappings are cleared or filled */
90 bool cleared;
91
92 bool is_xgmi;
93 };
94
95 struct amdgpu_bo {
96 /* Protected by tbo.reserved */
97 u32 preferred_domains;
98 u32 allowed_domains;
99 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
100 struct ttm_placement placement;
101 struct ttm_buffer_object tbo;
102 struct ttm_bo_kmap_obj kmap;
103 u64 flags;
104 /* per VM structure for page tables and with virtual addresses */
105 struct amdgpu_vm_bo_base *vm_bo;
106 /* Constant after initialization */
107 struct amdgpu_device *adev;
108 struct amdgpu_bo *parent;
109
110 #ifdef CONFIG_MMU_NOTIFIER
111 struct mmu_interval_notifier notifier;
112 #endif
113 struct kgd_mem *kfd_bo;
114
115 /*
116 * For GPUs with spatial partitioning, xcp partition number, -1 means
117 * any partition. For other ASICs without spatial partition, always 0
118 * for memory accounting.
119 */
120 int8_t xcp_id;
121 };
122
123 struct amdgpu_bo_user {
124 struct amdgpu_bo bo;
125 u64 tiling_flags;
126 u64 metadata_flags;
127 void *metadata;
128 u32 metadata_size;
129
130 };
131
132 struct amdgpu_bo_vm {
133 struct amdgpu_bo bo;
134 struct amdgpu_bo *shadow;
135 struct list_head shadow_list;
136 struct amdgpu_vm_bo_base entries[];
137 };
138
139 struct amdgpu_mem_stats {
140 /* current VRAM usage, includes visible VRAM */
141 uint64_t vram;
142 /* current shared VRAM usage, includes visible VRAM */
143 uint64_t vram_shared;
144 /* current visible VRAM usage */
145 uint64_t visible_vram;
146 /* current GTT usage */
147 uint64_t gtt;
148 /* current shared GTT usage */
149 uint64_t gtt_shared;
150 /* current system memory usage */
151 uint64_t cpu;
152 /* current shared system memory usage */
153 uint64_t cpu_shared;
154 /* sum of evicted buffers, includes visible VRAM */
155 uint64_t evicted_vram;
156 /* sum of evicted buffers due to CPU access */
157 uint64_t evicted_visible_vram;
158 /* how much userspace asked for, includes vis.VRAM */
159 uint64_t requested_vram;
160 /* how much userspace asked for */
161 uint64_t requested_visible_vram;
162 /* how much userspace asked for */
163 uint64_t requested_gtt;
164 };
165
ttm_to_amdgpu_bo(struct ttm_buffer_object * tbo)166 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
167 {
168 return container_of(tbo, struct amdgpu_bo, tbo);
169 }
170
171 /**
172 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
173 * @mem_type: ttm memory type
174 *
175 * Returns corresponding domain of the ttm mem_type
176 */
amdgpu_mem_type_to_domain(u32 mem_type)177 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
178 {
179 switch (mem_type) {
180 case TTM_PL_VRAM:
181 return AMDGPU_GEM_DOMAIN_VRAM;
182 case TTM_PL_TT:
183 return AMDGPU_GEM_DOMAIN_GTT;
184 case TTM_PL_SYSTEM:
185 return AMDGPU_GEM_DOMAIN_CPU;
186 case AMDGPU_PL_GDS:
187 return AMDGPU_GEM_DOMAIN_GDS;
188 case AMDGPU_PL_GWS:
189 return AMDGPU_GEM_DOMAIN_GWS;
190 case AMDGPU_PL_OA:
191 return AMDGPU_GEM_DOMAIN_OA;
192 case AMDGPU_PL_DOORBELL:
193 return AMDGPU_GEM_DOMAIN_DOORBELL;
194 default:
195 break;
196 }
197 return 0;
198 }
199
200 /**
201 * amdgpu_bo_reserve - reserve bo
202 * @bo: bo structure
203 * @no_intr: don't return -ERESTARTSYS on pending signal
204 *
205 * Returns:
206 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
207 * a signal. Release all buffer reservations and return to user-space.
208 */
amdgpu_bo_reserve(struct amdgpu_bo * bo,bool no_intr)209 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
210 {
211 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
212 int r;
213
214 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
215 if (unlikely(r != 0)) {
216 if (r != -ERESTARTSYS)
217 dev_err(adev->dev, "%p reserve failed\n", bo);
218 return r;
219 }
220 return 0;
221 }
222
amdgpu_bo_unreserve(struct amdgpu_bo * bo)223 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
224 {
225 ttm_bo_unreserve(&bo->tbo);
226 }
227
amdgpu_bo_size(struct amdgpu_bo * bo)228 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
229 {
230 return bo->tbo.base.size;
231 }
232
amdgpu_bo_ngpu_pages(struct amdgpu_bo * bo)233 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
234 {
235 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
236 }
237
amdgpu_bo_gpu_page_alignment(struct amdgpu_bo * bo)238 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
239 {
240 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
241 }
242
243 /**
244 * amdgpu_bo_mmap_offset - return mmap offset of bo
245 * @bo: amdgpu object for which we query the offset
246 *
247 * Returns mmap offset of the object.
248 */
amdgpu_bo_mmap_offset(struct amdgpu_bo * bo)249 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
250 {
251 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
252 }
253
254 /**
255 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
256 */
amdgpu_bo_explicit_sync(struct amdgpu_bo * bo)257 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
258 {
259 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
260 }
261
262 /**
263 * amdgpu_bo_encrypted - test if the BO is encrypted
264 * @bo: pointer to a buffer object
265 *
266 * Return true if the buffer object is encrypted, false otherwise.
267 */
amdgpu_bo_encrypted(struct amdgpu_bo * bo)268 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
269 {
270 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
271 }
272
273 /**
274 * amdgpu_bo_shadowed - check if the BO is shadowed
275 *
276 * @bo: BO to be tested.
277 *
278 * Returns:
279 * NULL if not shadowed or else return a BO pointer.
280 */
amdgpu_bo_shadowed(struct amdgpu_bo * bo)281 static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo)
282 {
283 if (bo->tbo.type == ttm_bo_type_kernel)
284 return to_amdgpu_bo_vm(bo)->shadow;
285
286 return NULL;
287 }
288
289 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
290 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
291
292 int amdgpu_bo_create(struct amdgpu_device *adev,
293 struct amdgpu_bo_param *bp,
294 struct amdgpu_bo **bo_ptr);
295 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
296 unsigned long size, int align,
297 u32 domain, struct amdgpu_bo **bo_ptr,
298 u64 *gpu_addr, void **cpu_addr);
299 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
300 unsigned long size, int align,
301 u32 domain, struct amdgpu_bo **bo_ptr,
302 u64 *gpu_addr, void **cpu_addr);
303 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
304 uint64_t offset, uint64_t size,
305 struct amdgpu_bo **bo_ptr, void **cpu_addr);
306 int amdgpu_bo_create_user(struct amdgpu_device *adev,
307 struct amdgpu_bo_param *bp,
308 struct amdgpu_bo_user **ubo_ptr);
309 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
310 struct amdgpu_bo_param *bp,
311 struct amdgpu_bo_vm **ubo_ptr);
312 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
313 void **cpu_addr);
314 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
315 void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
316 void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
317 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
318 void amdgpu_bo_unref(struct amdgpu_bo **bo);
319 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
320 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
321 u64 min_offset, u64 max_offset);
322 void amdgpu_bo_unpin(struct amdgpu_bo *bo);
323 int amdgpu_bo_init(struct amdgpu_device *adev);
324 void amdgpu_bo_fini(struct amdgpu_device *adev);
325 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
326 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
327 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
328 uint32_t metadata_size, uint64_t flags);
329 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
330 size_t buffer_size, uint32_t *metadata_size,
331 uint64_t *flags);
332 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
333 bool evict,
334 struct ttm_resource *new_mem);
335 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
336 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
337 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
338 bool shared);
339 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
340 enum amdgpu_sync_mode sync_mode, void *owner,
341 bool intr);
342 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
343 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
344 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
345 void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
346 struct amdgpu_mem_stats *stats);
347 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);
348 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
349 struct dma_fence **fence);
350 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
351 uint32_t domain);
352
353 /*
354 * sub allocation
355 */
356 static inline struct amdgpu_sa_manager *
to_amdgpu_sa_manager(struct drm_suballoc_manager * manager)357 to_amdgpu_sa_manager(struct drm_suballoc_manager *manager)
358 {
359 return container_of(manager, struct amdgpu_sa_manager, base);
360 }
361
amdgpu_sa_bo_gpu_addr(struct drm_suballoc * sa_bo)362 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo)
363 {
364 return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr +
365 drm_suballoc_soffset(sa_bo);
366 }
367
amdgpu_sa_bo_cpu_addr(struct drm_suballoc * sa_bo)368 static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo)
369 {
370 return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr +
371 drm_suballoc_soffset(sa_bo);
372 }
373
374 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
375 struct amdgpu_sa_manager *sa_manager,
376 unsigned size, u32 align, u32 domain);
377 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
378 struct amdgpu_sa_manager *sa_manager);
379 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
380 struct amdgpu_sa_manager *sa_manager);
381 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
382 struct drm_suballoc **sa_bo,
383 unsigned int size);
384 void amdgpu_sa_bo_free(struct amdgpu_device *adev,
385 struct drm_suballoc **sa_bo,
386 struct dma_fence *fence);
387 #if defined(CONFIG_DEBUG_FS)
388 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
389 struct seq_file *m);
390 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
391 #endif
392 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
393
394 bool amdgpu_bo_support_uswc(u64 bo_flags);
395
396
397 #endif
398