1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14 #if defined(__FreeBSD__)
15 #include <linux/seq_file.h>
16 #include <linux/lockdep.h>
17 #include <linux/interrupt.h>
18 #include <linux/pm.h>
19 #endif
20
21 struct rtw89_dev;
22 struct rtw89_pci_info;
23
24 extern const struct ieee80211_ops rtw89_ops;
25
26 #define MASKBYTE0 0xff
27 #define MASKBYTE1 0xff00
28 #define MASKBYTE2 0xff0000
29 #define MASKBYTE3 0xff000000
30 #define MASKBYTE4 0xff00000000ULL
31 #define MASKHWORD 0xffff0000
32 #define MASKLWORD 0x0000ffff
33 #define MASKDWORD 0xffffffff
34 #define RFREG_MASK 0xfffff
35 #define INV_RF_DATA 0xffffffff
36
37 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
38 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
39 #define CFO_TRACK_MAX_USER 64
40 #define MAX_RSSI 110
41 #define RSSI_FACTOR 1
42 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
43 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
44 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
45
46 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
47 #define RTW89_HTC_VARIANT_HE 3
48 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
49 #define RTW89_HTC_VARIANT_HE_CID_OM 1
50 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
51 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
52
53 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
54 enum htc_om_channel_width {
55 HTC_OM_CHANNEL_WIDTH_20 = 0,
56 HTC_OM_CHANNEL_WIDTH_40 = 1,
57 HTC_OM_CHANNEL_WIDTH_80 = 2,
58 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
59 };
60 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
61 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
62 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
63 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
64 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
65 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
66
67 #define RTW89_TF_PAD GENMASK(11, 0)
68 #define RTW89_TF_BASIC_USER_INFO_SZ 6
69
70 #define RTW89_GET_TF_USER_INFO_AID12(data) \
71 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
72 #define RTW89_GET_TF_USER_INFO_RUA(data) \
73 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
74 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
75 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
76
77 enum rtw89_subband {
78 RTW89_CH_2G = 0,
79 RTW89_CH_5G_BAND_1 = 1,
80 /* RTW89_CH_5G_BAND_2 = 2, unused */
81 RTW89_CH_5G_BAND_3 = 3,
82 RTW89_CH_5G_BAND_4 = 4,
83
84 RTW89_CH_6G_BAND_IDX0, /* Low */
85 RTW89_CH_6G_BAND_IDX1, /* Low */
86 RTW89_CH_6G_BAND_IDX2, /* Mid */
87 RTW89_CH_6G_BAND_IDX3, /* Mid */
88 RTW89_CH_6G_BAND_IDX4, /* High */
89 RTW89_CH_6G_BAND_IDX5, /* High */
90 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
91 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
92
93 RTW89_SUBBAND_NR,
94 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
95 };
96
97 enum rtw89_gain_offset {
98 RTW89_GAIN_OFFSET_2G_CCK,
99 RTW89_GAIN_OFFSET_2G_OFDM,
100 RTW89_GAIN_OFFSET_5G_LOW,
101 RTW89_GAIN_OFFSET_5G_MID,
102 RTW89_GAIN_OFFSET_5G_HIGH,
103
104 RTW89_GAIN_OFFSET_NR,
105 };
106
107 enum rtw89_hci_type {
108 RTW89_HCI_TYPE_PCIE,
109 RTW89_HCI_TYPE_USB,
110 RTW89_HCI_TYPE_SDIO,
111 };
112
113 enum rtw89_core_chip_id {
114 RTL8852A,
115 RTL8852B,
116 RTL8852C,
117 RTL8851B,
118 RTL8922A,
119 };
120
121 enum rtw89_chip_gen {
122 RTW89_CHIP_AX,
123 RTW89_CHIP_BE,
124
125 RTW89_CHIP_GEN_NUM,
126 };
127
128 enum rtw89_cv {
129 CHIP_CAV,
130 CHIP_CBV,
131 CHIP_CCV,
132 CHIP_CDV,
133 CHIP_CEV,
134 CHIP_CFV,
135 CHIP_CV_MAX,
136 CHIP_CV_INVALID = CHIP_CV_MAX,
137 };
138
139 enum rtw89_bacam_ver {
140 RTW89_BACAM_V0,
141 RTW89_BACAM_V1,
142
143 RTW89_BACAM_V0_EXT = 99,
144 };
145
146 enum rtw89_core_tx_type {
147 RTW89_CORE_TX_TYPE_DATA,
148 RTW89_CORE_TX_TYPE_MGMT,
149 RTW89_CORE_TX_TYPE_FWCMD,
150 };
151
152 enum rtw89_core_rx_type {
153 RTW89_CORE_RX_TYPE_WIFI = 0,
154 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
155 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
156 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
157 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
158 RTW89_CORE_RX_TYPE_SS2FW = 5,
159 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
160 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
161 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
162 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
163 RTW89_CORE_RX_TYPE_C2H = 10,
164 RTW89_CORE_RX_TYPE_CSI = 11,
165 RTW89_CORE_RX_TYPE_CQI = 12,
166 RTW89_CORE_RX_TYPE_H2C = 13,
167 RTW89_CORE_RX_TYPE_FWDL = 14,
168 };
169
170 enum rtw89_txq_flags {
171 RTW89_TXQ_F_AMPDU = 0,
172 RTW89_TXQ_F_BLOCK_BA = 1,
173 RTW89_TXQ_F_FORBID_BA = 2,
174 };
175
176 enum rtw89_net_type {
177 RTW89_NET_TYPE_NO_LINK = 0,
178 RTW89_NET_TYPE_AD_HOC = 1,
179 RTW89_NET_TYPE_INFRA = 2,
180 RTW89_NET_TYPE_AP_MODE = 3,
181 };
182
183 enum rtw89_wifi_role {
184 RTW89_WIFI_ROLE_NONE,
185 RTW89_WIFI_ROLE_STATION,
186 RTW89_WIFI_ROLE_AP,
187 RTW89_WIFI_ROLE_AP_VLAN,
188 RTW89_WIFI_ROLE_ADHOC,
189 RTW89_WIFI_ROLE_ADHOC_MASTER,
190 RTW89_WIFI_ROLE_MESH_POINT,
191 RTW89_WIFI_ROLE_MONITOR,
192 RTW89_WIFI_ROLE_P2P_DEVICE,
193 RTW89_WIFI_ROLE_P2P_CLIENT,
194 RTW89_WIFI_ROLE_P2P_GO,
195 RTW89_WIFI_ROLE_NAN,
196 RTW89_WIFI_ROLE_MLME_MAX
197 };
198
199 enum rtw89_upd_mode {
200 RTW89_ROLE_CREATE,
201 RTW89_ROLE_REMOVE,
202 RTW89_ROLE_TYPE_CHANGE,
203 RTW89_ROLE_INFO_CHANGE,
204 RTW89_ROLE_CON_DISCONN,
205 RTW89_ROLE_BAND_SW,
206 RTW89_ROLE_FW_RESTORE,
207 };
208
209 enum rtw89_self_role {
210 RTW89_SELF_ROLE_CLIENT,
211 RTW89_SELF_ROLE_AP,
212 RTW89_SELF_ROLE_AP_CLIENT
213 };
214
215 enum rtw89_msk_sO_el {
216 RTW89_NO_MSK,
217 RTW89_SMA,
218 RTW89_TMA,
219 RTW89_BSSID
220 };
221
222 enum rtw89_sch_tx_sel {
223 RTW89_SCH_TX_SEL_ALL,
224 RTW89_SCH_TX_SEL_HIQ,
225 RTW89_SCH_TX_SEL_MG0,
226 RTW89_SCH_TX_SEL_MACID,
227 };
228
229 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
230 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
231 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
232 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
233 */
234 enum rtw89_add_cam_sec_mode {
235 RTW89_ADDR_CAM_SEC_NONE = 0,
236 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
237 RTW89_ADDR_CAM_SEC_NORMAL = 2,
238 RTW89_ADDR_CAM_SEC_4GROUP = 3,
239 };
240
241 enum rtw89_sec_key_type {
242 RTW89_SEC_KEY_TYPE_NONE = 0,
243 RTW89_SEC_KEY_TYPE_WEP40 = 1,
244 RTW89_SEC_KEY_TYPE_WEP104 = 2,
245 RTW89_SEC_KEY_TYPE_TKIP = 3,
246 RTW89_SEC_KEY_TYPE_WAPI = 4,
247 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
248 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
249 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
250 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
251 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
252 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
253 };
254
255 enum rtw89_port {
256 RTW89_PORT_0 = 0,
257 RTW89_PORT_1 = 1,
258 RTW89_PORT_2 = 2,
259 RTW89_PORT_3 = 3,
260 RTW89_PORT_4 = 4,
261 RTW89_PORT_NUM
262 };
263
264 enum rtw89_band {
265 RTW89_BAND_2G = 0,
266 RTW89_BAND_5G = 1,
267 RTW89_BAND_6G = 2,
268 RTW89_BAND_NUM,
269 };
270
271 enum rtw89_hw_rate {
272 RTW89_HW_RATE_CCK1 = 0x0,
273 RTW89_HW_RATE_CCK2 = 0x1,
274 RTW89_HW_RATE_CCK5_5 = 0x2,
275 RTW89_HW_RATE_CCK11 = 0x3,
276 RTW89_HW_RATE_OFDM6 = 0x4,
277 RTW89_HW_RATE_OFDM9 = 0x5,
278 RTW89_HW_RATE_OFDM12 = 0x6,
279 RTW89_HW_RATE_OFDM18 = 0x7,
280 RTW89_HW_RATE_OFDM24 = 0x8,
281 RTW89_HW_RATE_OFDM36 = 0x9,
282 RTW89_HW_RATE_OFDM48 = 0xA,
283 RTW89_HW_RATE_OFDM54 = 0xB,
284 RTW89_HW_RATE_MCS0 = 0x80,
285 RTW89_HW_RATE_MCS1 = 0x81,
286 RTW89_HW_RATE_MCS2 = 0x82,
287 RTW89_HW_RATE_MCS3 = 0x83,
288 RTW89_HW_RATE_MCS4 = 0x84,
289 RTW89_HW_RATE_MCS5 = 0x85,
290 RTW89_HW_RATE_MCS6 = 0x86,
291 RTW89_HW_RATE_MCS7 = 0x87,
292 RTW89_HW_RATE_MCS8 = 0x88,
293 RTW89_HW_RATE_MCS9 = 0x89,
294 RTW89_HW_RATE_MCS10 = 0x8A,
295 RTW89_HW_RATE_MCS11 = 0x8B,
296 RTW89_HW_RATE_MCS12 = 0x8C,
297 RTW89_HW_RATE_MCS13 = 0x8D,
298 RTW89_HW_RATE_MCS14 = 0x8E,
299 RTW89_HW_RATE_MCS15 = 0x8F,
300 RTW89_HW_RATE_MCS16 = 0x90,
301 RTW89_HW_RATE_MCS17 = 0x91,
302 RTW89_HW_RATE_MCS18 = 0x92,
303 RTW89_HW_RATE_MCS19 = 0x93,
304 RTW89_HW_RATE_MCS20 = 0x94,
305 RTW89_HW_RATE_MCS21 = 0x95,
306 RTW89_HW_RATE_MCS22 = 0x96,
307 RTW89_HW_RATE_MCS23 = 0x97,
308 RTW89_HW_RATE_MCS24 = 0x98,
309 RTW89_HW_RATE_MCS25 = 0x99,
310 RTW89_HW_RATE_MCS26 = 0x9A,
311 RTW89_HW_RATE_MCS27 = 0x9B,
312 RTW89_HW_RATE_MCS28 = 0x9C,
313 RTW89_HW_RATE_MCS29 = 0x9D,
314 RTW89_HW_RATE_MCS30 = 0x9E,
315 RTW89_HW_RATE_MCS31 = 0x9F,
316 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
317 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
318 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
319 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
320 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
321 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
322 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
323 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
324 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
325 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
326 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
327 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
328 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
329 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
330 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
331 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
332 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
333 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
334 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
335 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
336 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
337 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
338 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
339 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
340 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
341 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
342 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
343 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
344 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
345 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
346 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
347 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
348 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
349 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
350 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
351 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
352 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
353 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
354 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
355 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
356 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
357 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
358 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
359 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
360 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
361 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
362 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
363 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
364 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
365 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
366 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
367 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
368 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
369 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
370 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
371 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
372 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
373 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
374 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
375 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
376 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
377 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
378 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
379 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
380 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
381 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
382 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
383 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
384 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
385 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
386 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
387 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
388 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
389 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
390 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
391 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
392 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
393 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
394 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
395 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
396 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
397 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
398 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
399 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
400 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
401 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
402 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
403 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
404
405 RTW89_HW_RATE_V1_MCS0 = 0x100,
406 RTW89_HW_RATE_V1_MCS1 = 0x101,
407 RTW89_HW_RATE_V1_MCS2 = 0x102,
408 RTW89_HW_RATE_V1_MCS3 = 0x103,
409 RTW89_HW_RATE_V1_MCS4 = 0x104,
410 RTW89_HW_RATE_V1_MCS5 = 0x105,
411 RTW89_HW_RATE_V1_MCS6 = 0x106,
412 RTW89_HW_RATE_V1_MCS7 = 0x107,
413 RTW89_HW_RATE_V1_MCS8 = 0x108,
414 RTW89_HW_RATE_V1_MCS9 = 0x109,
415 RTW89_HW_RATE_V1_MCS10 = 0x10A,
416 RTW89_HW_RATE_V1_MCS11 = 0x10B,
417 RTW89_HW_RATE_V1_MCS12 = 0x10C,
418 RTW89_HW_RATE_V1_MCS13 = 0x10D,
419 RTW89_HW_RATE_V1_MCS14 = 0x10E,
420 RTW89_HW_RATE_V1_MCS15 = 0x10F,
421 RTW89_HW_RATE_V1_MCS16 = 0x110,
422 RTW89_HW_RATE_V1_MCS17 = 0x111,
423 RTW89_HW_RATE_V1_MCS18 = 0x112,
424 RTW89_HW_RATE_V1_MCS19 = 0x113,
425 RTW89_HW_RATE_V1_MCS20 = 0x114,
426 RTW89_HW_RATE_V1_MCS21 = 0x115,
427 RTW89_HW_RATE_V1_MCS22 = 0x116,
428 RTW89_HW_RATE_V1_MCS23 = 0x117,
429 RTW89_HW_RATE_V1_MCS24 = 0x118,
430 RTW89_HW_RATE_V1_MCS25 = 0x119,
431 RTW89_HW_RATE_V1_MCS26 = 0x11A,
432 RTW89_HW_RATE_V1_MCS27 = 0x11B,
433 RTW89_HW_RATE_V1_MCS28 = 0x11C,
434 RTW89_HW_RATE_V1_MCS29 = 0x11D,
435 RTW89_HW_RATE_V1_MCS30 = 0x11E,
436 RTW89_HW_RATE_V1_MCS31 = 0x11F,
437 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
438 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
439 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
440 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
441 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
442 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
443 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
444 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
445 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
446 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
447 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
448 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
449 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
450 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
451 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
452 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
453 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
454 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
455 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
456 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
457 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
458 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
459 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
460 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
461 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
462 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
463 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
464 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
465 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
466 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
467 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
468 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
469 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
470 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
471 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
472 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
473 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
474 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
475 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
476 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
477 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
478 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
479 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
480 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
481 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
482 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
483 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
484 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
485 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
486 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
487 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
488 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
489 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
490 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
491 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
492 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
493 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
494 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
495 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
496 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
497 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
498 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
499 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
500 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
501 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
502 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
503 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
504 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
505 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
506 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
507 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
508 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
509 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
510 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
511 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
512 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
513 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
514 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
515 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
516 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
517 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
518 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
519 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
520 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
521 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
522 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
523 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
524 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
525 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
526 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
527 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
528 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
529 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
530 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
531 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
532 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
533 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
534 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
535 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
536 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
537 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
538 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
539 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
540 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
541 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
542 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
543 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
544 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
545 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
546 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
547 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
548 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
549 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
550 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
551 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
552 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
553 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
554 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
555 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
556 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
557 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
558 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
559 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
560 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
561 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
562 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
563 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
564 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
565 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
566 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
567 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
568 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
569 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
570 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
571 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
572 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
573 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
574 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
575 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
576 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
577 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
578 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
579 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
580 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
581 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
582 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
583 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
584 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
585 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
586 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
587 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
588 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
589 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
590 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
591
592 RTW89_HW_RATE_NR,
593 RTW89_HW_RATE_INVAL,
594
595 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
596 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
597 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
598 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
599 };
600
601 /* 2G channels,
602 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
603 */
604 #define RTW89_2G_CH_NUM 14
605
606 /* 5G channels,
607 * 36, 38, 40, 42, 44, 46, 48, 50,
608 * 52, 54, 56, 58, 60, 62, 64,
609 * 100, 102, 104, 106, 108, 110, 112, 114,
610 * 116, 118, 120, 122, 124, 126, 128, 130,
611 * 132, 134, 136, 138, 140, 142, 144,
612 * 149, 151, 153, 155, 157, 159, 161, 163,
613 * 165, 167, 169, 171, 173, 175, 177
614 */
615 #define RTW89_5G_CH_NUM 53
616
617 /* 6G channels,
618 * 1, 3, 5, 7, 9, 11, 13, 15,
619 * 17, 19, 21, 23, 25, 27, 29, 33,
620 * 35, 37, 39, 41, 43, 45, 47, 49,
621 * 51, 53, 55, 57, 59, 61, 65, 67,
622 * 69, 71, 73, 75, 77, 79, 81, 83,
623 * 85, 87, 89, 91, 93, 97, 99, 101,
624 * 103, 105, 107, 109, 111, 113, 115, 117,
625 * 119, 121, 123, 125, 129, 131, 133, 135,
626 * 137, 139, 141, 143, 145, 147, 149, 151,
627 * 153, 155, 157, 161, 163, 165, 167, 169,
628 * 171, 173, 175, 177, 179, 181, 183, 185,
629 * 187, 189, 193, 195, 197, 199, 201, 203,
630 * 205, 207, 209, 211, 213, 215, 217, 219,
631 * 221, 225, 227, 229, 231, 233, 235, 237,
632 * 239, 241, 243, 245, 247, 249, 251, 253,
633 */
634 #define RTW89_6G_CH_NUM 120
635
636 enum rtw89_rate_section {
637 RTW89_RS_CCK,
638 RTW89_RS_OFDM,
639 RTW89_RS_MCS, /* for HT/VHT/HE */
640 RTW89_RS_HEDCM,
641 RTW89_RS_OFFSET,
642 RTW89_RS_NUM,
643 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
644 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
645 };
646
647 enum rtw89_rate_num {
648 RTW89_RATE_CCK_NUM = 4,
649 RTW89_RATE_OFDM_NUM = 8,
650 RTW89_RATE_MCS_NUM = 12,
651 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
652 RTW89_RATE_OFFSET_NUM = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
653 };
654
655 enum rtw89_nss {
656 RTW89_NSS_1 = 0,
657 RTW89_NSS_2 = 1,
658 /* HE DCM only support 1ss and 2ss */
659 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
660 RTW89_NSS_3 = 2,
661 RTW89_NSS_4 = 3,
662 RTW89_NSS_NUM,
663 };
664
665 enum rtw89_ntx {
666 RTW89_1TX = 0,
667 RTW89_2TX = 1,
668 RTW89_NTX_NUM,
669 };
670
671 enum rtw89_beamforming_type {
672 RTW89_NONBF = 0,
673 RTW89_BF = 1,
674 RTW89_BF_NUM,
675 };
676
677 enum rtw89_regulation_type {
678 RTW89_WW = 0,
679 RTW89_ETSI = 1,
680 RTW89_FCC = 2,
681 RTW89_MKK = 3,
682 RTW89_NA = 4,
683 RTW89_IC = 5,
684 RTW89_KCC = 6,
685 RTW89_ACMA = 7,
686 RTW89_NCC = 8,
687 RTW89_MEXICO = 9,
688 RTW89_CHILE = 10,
689 RTW89_UKRAINE = 11,
690 RTW89_CN = 12,
691 RTW89_QATAR = 13,
692 RTW89_UK = 14,
693 RTW89_REGD_NUM,
694 };
695
696 enum rtw89_reg_6ghz_power {
697 RTW89_REG_6GHZ_POWER_VLP = 0,
698 RTW89_REG_6GHZ_POWER_LPI = 1,
699 RTW89_REG_6GHZ_POWER_STD = 2,
700
701 NUM_OF_RTW89_REG_6GHZ_POWER,
702 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
703 };
704
705 enum rtw89_fw_pkt_ofld_type {
706 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
707 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
708 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
709 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
710 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
711 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
712 RTW89_PKT_OFLD_TYPE_NDP = 6,
713 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
714 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
715 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
716 RTW89_PKT_OFLD_TYPE_NUM,
717 };
718
719 struct rtw89_txpwr_byrate {
720 s8 cck[RTW89_RATE_CCK_NUM];
721 s8 ofdm[RTW89_RATE_OFDM_NUM];
722 s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM];
723 s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
724 s8 offset[RTW89_RATE_OFFSET_NUM];
725 };
726
727 enum rtw89_bandwidth_section_num {
728 RTW89_BW20_SEC_NUM = 8,
729 RTW89_BW40_SEC_NUM = 4,
730 RTW89_BW80_SEC_NUM = 2,
731 };
732
733 #define RTW89_TXPWR_LMT_PAGE_SIZE 40
734
735 struct rtw89_txpwr_limit {
736 s8 cck_20m[RTW89_BF_NUM];
737 s8 cck_40m[RTW89_BF_NUM];
738 s8 ofdm[RTW89_BF_NUM];
739 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
740 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
741 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
742 s8 mcs_160m[RTW89_BF_NUM];
743 s8 mcs_40m_0p5[RTW89_BF_NUM];
744 s8 mcs_40m_2p5[RTW89_BF_NUM];
745 };
746
747 #define RTW89_RU_SEC_NUM 8
748
749 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
750
751 struct rtw89_txpwr_limit_ru {
752 s8 ru26[RTW89_RU_SEC_NUM];
753 s8 ru52[RTW89_RU_SEC_NUM];
754 s8 ru106[RTW89_RU_SEC_NUM];
755 };
756
757 struct rtw89_rate_desc {
758 enum rtw89_nss nss;
759 enum rtw89_rate_section rs;
760 u8 idx;
761 };
762
763 #define PHY_STS_HDR_LEN 8
764 #define RF_PATH_MAX 4
765 #define RTW89_MAX_PPDU_CNT 8
766 struct rtw89_rx_phy_ppdu {
767 void *buf;
768 u32 len;
769 u8 rssi_avg;
770 u8 rssi[RF_PATH_MAX];
771 u8 mac_id;
772 u8 chan_idx;
773 u8 ie;
774 u16 rate;
775 struct {
776 bool has;
777 u8 avg_snr;
778 u8 evm_max;
779 u8 evm_min;
780 } ofdm;
781 bool to_self;
782 bool valid;
783 };
784
785 enum rtw89_mac_idx {
786 RTW89_MAC_0 = 0,
787 RTW89_MAC_1 = 1,
788 };
789
790 enum rtw89_phy_idx {
791 RTW89_PHY_0 = 0,
792 RTW89_PHY_1 = 1,
793 RTW89_PHY_MAX
794 };
795
796 enum rtw89_sub_entity_idx {
797 RTW89_SUB_ENTITY_0 = 0,
798
799 NUM_OF_RTW89_SUB_ENTITY,
800 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
801 };
802
803 enum rtw89_rf_path {
804 RF_PATH_A = 0,
805 RF_PATH_B = 1,
806 RF_PATH_C = 2,
807 RF_PATH_D = 3,
808 RF_PATH_AB,
809 RF_PATH_AC,
810 RF_PATH_AD,
811 RF_PATH_BC,
812 RF_PATH_BD,
813 RF_PATH_CD,
814 RF_PATH_ABC,
815 RF_PATH_ABD,
816 RF_PATH_ACD,
817 RF_PATH_BCD,
818 RF_PATH_ABCD,
819 };
820
821 enum rtw89_rf_path_bit {
822 RF_A = BIT(0),
823 RF_B = BIT(1),
824 RF_C = BIT(2),
825 RF_D = BIT(3),
826
827 RF_AB = (RF_A | RF_B),
828 RF_AC = (RF_A | RF_C),
829 RF_AD = (RF_A | RF_D),
830 RF_BC = (RF_B | RF_C),
831 RF_BD = (RF_B | RF_D),
832 RF_CD = (RF_C | RF_D),
833
834 RF_ABC = (RF_A | RF_B | RF_C),
835 RF_ABD = (RF_A | RF_B | RF_D),
836 RF_ACD = (RF_A | RF_C | RF_D),
837 RF_BCD = (RF_B | RF_C | RF_D),
838
839 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
840 };
841
842 enum rtw89_bandwidth {
843 RTW89_CHANNEL_WIDTH_20 = 0,
844 RTW89_CHANNEL_WIDTH_40 = 1,
845 RTW89_CHANNEL_WIDTH_80 = 2,
846 RTW89_CHANNEL_WIDTH_160 = 3,
847 RTW89_CHANNEL_WIDTH_80_80 = 4,
848 RTW89_CHANNEL_WIDTH_5 = 5,
849 RTW89_CHANNEL_WIDTH_10 = 6,
850 };
851
852 enum rtw89_ps_mode {
853 RTW89_PS_MODE_NONE = 0,
854 RTW89_PS_MODE_RFOFF = 1,
855 RTW89_PS_MODE_CLK_GATED = 2,
856 RTW89_PS_MODE_PWR_GATED = 3,
857 };
858
859 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
860 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
861 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
862 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
863
864 enum rtw89_ru_bandwidth {
865 RTW89_RU26 = 0,
866 RTW89_RU52 = 1,
867 RTW89_RU106 = 2,
868 RTW89_RU_NUM,
869 };
870
871 enum rtw89_sc_offset {
872 RTW89_SC_DONT_CARE = 0,
873 RTW89_SC_20_UPPER = 1,
874 RTW89_SC_20_LOWER = 2,
875 RTW89_SC_20_UPMOST = 3,
876 RTW89_SC_20_LOWEST = 4,
877 RTW89_SC_20_UP2X = 5,
878 RTW89_SC_20_LOW2X = 6,
879 RTW89_SC_20_UP3X = 7,
880 RTW89_SC_20_LOW3X = 8,
881 RTW89_SC_40_UPPER = 9,
882 RTW89_SC_40_LOWER = 10,
883 };
884
885 enum rtw89_wow_flags {
886 RTW89_WOW_FLAG_EN_MAGIC_PKT,
887 RTW89_WOW_FLAG_EN_REKEY_PKT,
888 RTW89_WOW_FLAG_EN_DISCONNECT,
889 RTW89_WOW_FLAG_NUM,
890 };
891
892 struct rtw89_chan {
893 u8 channel;
894 u8 primary_channel;
895 enum rtw89_band band_type;
896 enum rtw89_bandwidth band_width;
897
898 /* The follow-up are derived from the above. We must ensure that it
899 * is assigned correctly in rtw89_chan_create() if new one is added.
900 */
901 u32 freq;
902 enum rtw89_subband subband_type;
903 enum rtw89_sc_offset pri_ch_idx;
904 };
905
906 struct rtw89_chan_rcd {
907 u8 prev_primary_channel;
908 enum rtw89_band prev_band_type;
909 };
910
911 struct rtw89_channel_help_params {
912 u32 tx_en;
913 };
914
915 struct rtw89_port_reg {
916 u32 port_cfg;
917 u32 tbtt_prohib;
918 u32 bcn_area;
919 u32 bcn_early;
920 u32 tbtt_early;
921 u32 tbtt_agg;
922 u32 bcn_space;
923 u32 bcn_forcetx;
924 u32 bcn_err_cnt;
925 u32 bcn_err_flag;
926 u32 dtim_ctrl;
927 u32 tbtt_shift;
928 u32 bcn_cnt_tmr;
929 u32 tsftr_l;
930 u32 tsftr_h;
931 };
932
933 struct rtw89_txwd_body {
934 __le32 dword0;
935 __le32 dword1;
936 __le32 dword2;
937 __le32 dword3;
938 __le32 dword4;
939 __le32 dword5;
940 } __packed;
941
942 struct rtw89_txwd_body_v1 {
943 __le32 dword0;
944 __le32 dword1;
945 __le32 dword2;
946 __le32 dword3;
947 __le32 dword4;
948 __le32 dword5;
949 __le32 dword6;
950 __le32 dword7;
951 } __packed;
952
953 struct rtw89_txwd_info {
954 __le32 dword0;
955 __le32 dword1;
956 __le32 dword2;
957 __le32 dword3;
958 __le32 dword4;
959 __le32 dword5;
960 } __packed;
961
962 struct rtw89_rx_desc_info {
963 u16 pkt_size;
964 u8 pkt_type;
965 u8 drv_info_size;
966 u8 shift;
967 u8 wl_hd_iv_len;
968 bool long_rxdesc;
969 bool bb_sel;
970 bool mac_info_valid;
971 u16 data_rate;
972 u8 gi_ltf;
973 u8 bw;
974 u32 free_run_cnt;
975 u8 user_id;
976 bool sr_en;
977 u8 ppdu_cnt;
978 u8 ppdu_type;
979 bool icv_err;
980 bool crc32_err;
981 bool hw_dec;
982 bool sw_dec;
983 bool addr1_match;
984 u8 frag;
985 u16 seq;
986 u8 frame_type;
987 u8 rx_pl_id;
988 bool addr_cam_valid;
989 u8 addr_cam_id;
990 u8 sec_cam_id;
991 u8 mac_id;
992 u16 offset;
993 u16 rxd_len;
994 bool ready;
995 };
996
997 struct rtw89_rxdesc_short {
998 __le32 dword0;
999 __le32 dword1;
1000 __le32 dword2;
1001 __le32 dword3;
1002 } __packed;
1003
1004 struct rtw89_rxdesc_long {
1005 __le32 dword0;
1006 __le32 dword1;
1007 __le32 dword2;
1008 __le32 dword3;
1009 __le32 dword4;
1010 __le32 dword5;
1011 __le32 dword6;
1012 __le32 dword7;
1013 } __packed;
1014
1015 struct rtw89_tx_desc_info {
1016 u16 pkt_size;
1017 u8 wp_offset;
1018 u8 mac_id;
1019 u8 qsel;
1020 u8 ch_dma;
1021 u8 hdr_llc_len;
1022 bool is_bmc;
1023 bool en_wd_info;
1024 bool wd_page;
1025 bool use_rate;
1026 bool dis_data_fb;
1027 bool tid_indicate;
1028 bool agg_en;
1029 bool bk;
1030 u8 ampdu_density;
1031 u8 ampdu_num;
1032 bool sec_en;
1033 u8 addr_info_nr;
1034 u8 sec_keyid;
1035 u8 sec_type;
1036 u8 sec_cam_idx;
1037 u8 sec_seq[6];
1038 u16 data_rate;
1039 u16 data_retry_lowest_rate;
1040 bool fw_dl;
1041 u16 seq;
1042 bool a_ctrl_bsr;
1043 u8 hw_ssn_sel;
1044 #define RTW89_MGMT_HW_SSN_SEL 1
1045 u8 hw_seq_mode;
1046 #define RTW89_MGMT_HW_SEQ_MODE 1
1047 bool hiq;
1048 u8 port;
1049 bool er_cap;
1050 };
1051
1052 struct rtw89_core_tx_request {
1053 enum rtw89_core_tx_type tx_type;
1054
1055 struct sk_buff *skb;
1056 struct ieee80211_vif *vif;
1057 struct ieee80211_sta *sta;
1058 struct rtw89_tx_desc_info desc_info;
1059 };
1060
1061 struct rtw89_txq {
1062 struct list_head list;
1063 unsigned long flags;
1064 int wait_cnt;
1065 };
1066
1067 struct rtw89_mac_ax_gnt {
1068 u8 gnt_bt_sw_en;
1069 u8 gnt_bt;
1070 u8 gnt_wl_sw_en;
1071 u8 gnt_wl;
1072 } __packed;
1073
1074 #define RTW89_MAC_AX_COEX_GNT_NR 2
1075 struct rtw89_mac_ax_coex_gnt {
1076 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1077 };
1078
1079 enum rtw89_btc_ncnt {
1080 BTC_NCNT_POWER_ON = 0x0,
1081 BTC_NCNT_POWER_OFF,
1082 BTC_NCNT_INIT_COEX,
1083 BTC_NCNT_SCAN_START,
1084 BTC_NCNT_SCAN_FINISH,
1085 BTC_NCNT_SPECIAL_PACKET,
1086 BTC_NCNT_SWITCH_BAND,
1087 BTC_NCNT_RFK_TIMEOUT,
1088 BTC_NCNT_SHOW_COEX_INFO,
1089 BTC_NCNT_ROLE_INFO,
1090 BTC_NCNT_CONTROL,
1091 BTC_NCNT_RADIO_STATE,
1092 BTC_NCNT_CUSTOMERIZE,
1093 BTC_NCNT_WL_RFK,
1094 BTC_NCNT_WL_STA,
1095 BTC_NCNT_FWINFO,
1096 BTC_NCNT_TIMER,
1097 BTC_NCNT_NUM
1098 };
1099
1100 enum rtw89_btc_btinfo {
1101 BTC_BTINFO_L0 = 0,
1102 BTC_BTINFO_L1,
1103 BTC_BTINFO_L2,
1104 BTC_BTINFO_L3,
1105 BTC_BTINFO_H0,
1106 BTC_BTINFO_H1,
1107 BTC_BTINFO_H2,
1108 BTC_BTINFO_H3,
1109 BTC_BTINFO_MAX
1110 };
1111
1112 enum rtw89_btc_dcnt {
1113 BTC_DCNT_RUN = 0x0,
1114 BTC_DCNT_CX_RUNINFO,
1115 BTC_DCNT_RPT,
1116 BTC_DCNT_RPT_HANG,
1117 BTC_DCNT_CYCLE,
1118 BTC_DCNT_CYCLE_HANG,
1119 BTC_DCNT_W1,
1120 BTC_DCNT_W1_HANG,
1121 BTC_DCNT_B1,
1122 BTC_DCNT_B1_HANG,
1123 BTC_DCNT_TDMA_NONSYNC,
1124 BTC_DCNT_SLOT_NONSYNC,
1125 BTC_DCNT_BTCNT_HANG,
1126 BTC_DCNT_WL_SLOT_DRIFT,
1127 BTC_DCNT_WL_STA_LAST,
1128 BTC_DCNT_BT_SLOT_DRIFT,
1129 BTC_DCNT_BT_SLOT_FLOOD,
1130 BTC_DCNT_FDDT_TRIG,
1131 BTC_DCNT_E2G,
1132 BTC_DCNT_E2G_HANG,
1133 BTC_DCNT_NUM
1134 };
1135
1136 enum rtw89_btc_wl_state_cnt {
1137 BTC_WCNT_SCANAP = 0x0,
1138 BTC_WCNT_DHCP,
1139 BTC_WCNT_EAPOL,
1140 BTC_WCNT_ARP,
1141 BTC_WCNT_SCBDUPDATE,
1142 BTC_WCNT_RFK_REQ,
1143 BTC_WCNT_RFK_GO,
1144 BTC_WCNT_RFK_REJECT,
1145 BTC_WCNT_RFK_TIMEOUT,
1146 BTC_WCNT_CH_UPDATE,
1147 BTC_WCNT_NUM
1148 };
1149
1150 enum rtw89_btc_bt_state_cnt {
1151 BTC_BCNT_RETRY = 0x0,
1152 BTC_BCNT_REINIT,
1153 BTC_BCNT_REENABLE,
1154 BTC_BCNT_SCBDREAD,
1155 BTC_BCNT_RELINK,
1156 BTC_BCNT_IGNOWL,
1157 BTC_BCNT_INQPAG,
1158 BTC_BCNT_INQ,
1159 BTC_BCNT_PAGE,
1160 BTC_BCNT_ROLESW,
1161 BTC_BCNT_AFH,
1162 BTC_BCNT_INFOUPDATE,
1163 BTC_BCNT_INFOSAME,
1164 BTC_BCNT_SCBDUPDATE,
1165 BTC_BCNT_HIPRI_TX,
1166 BTC_BCNT_HIPRI_RX,
1167 BTC_BCNT_LOPRI_TX,
1168 BTC_BCNT_LOPRI_RX,
1169 BTC_BCNT_POLUT,
1170 BTC_BCNT_RATECHG,
1171 BTC_BCNT_NUM
1172 };
1173
1174 enum rtw89_btc_bt_profile {
1175 BTC_BT_NOPROFILE = 0,
1176 BTC_BT_HFP = BIT(0),
1177 BTC_BT_HID = BIT(1),
1178 BTC_BT_A2DP = BIT(2),
1179 BTC_BT_PAN = BIT(3),
1180 BTC_PROFILE_MAX = 4,
1181 };
1182
1183 struct rtw89_btc_ant_info {
1184 u8 type; /* shared, dedicated */
1185 u8 num;
1186 u8 isolation;
1187
1188 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1189 u8 diversity: 1;
1190 u8 btg_pos: 2;
1191 u8 stream_cnt: 4;
1192 };
1193
1194 enum rtw89_tfc_dir {
1195 RTW89_TFC_UL,
1196 RTW89_TFC_DL,
1197 };
1198
1199 struct rtw89_btc_wl_smap {
1200 u32 busy: 1;
1201 u32 scan: 1;
1202 u32 connecting: 1;
1203 u32 roaming: 1;
1204 u32 _4way: 1;
1205 u32 rf_off: 1;
1206 u32 lps: 2;
1207 u32 ips: 1;
1208 u32 init_ok: 1;
1209 u32 traffic_dir : 2;
1210 u32 rf_off_pre: 1;
1211 u32 lps_pre: 2;
1212 };
1213
1214 enum rtw89_tfc_lv {
1215 RTW89_TFC_IDLE,
1216 RTW89_TFC_ULTRA_LOW,
1217 RTW89_TFC_LOW,
1218 RTW89_TFC_MID,
1219 RTW89_TFC_HIGH,
1220 };
1221
1222 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1223 DECLARE_EWMA(tp, 10, 2);
1224
1225 struct rtw89_traffic_stats {
1226 /* units in bytes */
1227 u64 tx_unicast;
1228 u64 rx_unicast;
1229 u32 tx_avg_len;
1230 u32 rx_avg_len;
1231
1232 /* count for packets */
1233 u64 tx_cnt;
1234 u64 rx_cnt;
1235
1236 /* units in Mbps */
1237 u32 tx_throughput;
1238 u32 rx_throughput;
1239 u32 tx_throughput_raw;
1240 u32 rx_throughput_raw;
1241
1242 u32 rx_tf_acc;
1243 u32 rx_tf_periodic;
1244
1245 enum rtw89_tfc_lv tx_tfc_lv;
1246 enum rtw89_tfc_lv rx_tfc_lv;
1247 struct ewma_tp tx_ewma_tp;
1248 struct ewma_tp rx_ewma_tp;
1249
1250 u16 tx_rate;
1251 u16 rx_rate;
1252 };
1253
1254 struct rtw89_btc_statistic {
1255 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1256 struct rtw89_traffic_stats traffic;
1257 };
1258
1259 #define BTC_WL_RSSI_THMAX 4
1260
1261 struct rtw89_btc_wl_link_info {
1262 struct rtw89_btc_statistic stat;
1263 enum rtw89_tfc_dir dir;
1264 u8 rssi_state[BTC_WL_RSSI_THMAX];
1265 u8 mac_addr[ETH_ALEN];
1266 u8 busy;
1267 u8 ch;
1268 u8 bw;
1269 u8 band;
1270 u8 role;
1271 u8 pid;
1272 u8 phy;
1273 u8 dtim_period;
1274 u8 mode;
1275
1276 u8 mac_id;
1277 u8 tx_retry;
1278
1279 u32 bcn_period;
1280 u32 busy_t;
1281 u32 tx_time;
1282 u32 client_cnt;
1283 u32 rx_rate_drop_cnt;
1284
1285 u32 active: 1;
1286 u32 noa: 1;
1287 u32 client_ps: 1;
1288 u32 connected: 2;
1289 };
1290
1291 union rtw89_btc_wl_state_map {
1292 u32 val;
1293 struct rtw89_btc_wl_smap map;
1294 };
1295
1296 struct rtw89_btc_bt_hfp_desc {
1297 u32 exist: 1;
1298 u32 type: 2;
1299 u32 rsvd: 29;
1300 };
1301
1302 struct rtw89_btc_bt_hid_desc {
1303 u32 exist: 1;
1304 u32 slot_info: 2;
1305 u32 pair_cnt: 2;
1306 u32 type: 8;
1307 u32 rsvd: 19;
1308 };
1309
1310 struct rtw89_btc_bt_a2dp_desc {
1311 u8 exist: 1;
1312 u8 exist_last: 1;
1313 u8 play_latency: 1;
1314 u8 type: 3;
1315 u8 active: 1;
1316 u8 sink: 1;
1317
1318 u8 bitpool;
1319 u16 vendor_id;
1320 u32 device_name;
1321 u32 flush_time;
1322 };
1323
1324 struct rtw89_btc_bt_pan_desc {
1325 u32 exist: 1;
1326 u32 type: 1;
1327 u32 active: 1;
1328 u32 rsvd: 29;
1329 };
1330
1331 struct rtw89_btc_bt_rfk_info {
1332 u32 run: 1;
1333 u32 req: 1;
1334 u32 timeout: 1;
1335 u32 rsvd: 29;
1336 };
1337
1338 union rtw89_btc_bt_rfk_info_map {
1339 u32 val;
1340 struct rtw89_btc_bt_rfk_info map;
1341 };
1342
1343 struct rtw89_btc_bt_ver_info {
1344 u32 fw_coex; /* match with which coex_ver */
1345 u32 fw;
1346 };
1347
1348 struct rtw89_btc_bool_sta_chg {
1349 u32 now: 1;
1350 u32 last: 1;
1351 u32 remain: 1;
1352 u32 srvd: 29;
1353 };
1354
1355 struct rtw89_btc_u8_sta_chg {
1356 u8 now;
1357 u8 last;
1358 u8 remain;
1359 u8 rsvd;
1360 };
1361
1362 struct rtw89_btc_wl_scan_info {
1363 u8 band[RTW89_PHY_MAX];
1364 u8 phy_map;
1365 u8 rsvd;
1366 };
1367
1368 struct rtw89_btc_wl_dbcc_info {
1369 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1370 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1371 u8 real_band[RTW89_PHY_MAX];
1372 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1373 };
1374
1375 struct rtw89_btc_wl_active_role {
1376 u8 connected: 1;
1377 u8 pid: 3;
1378 u8 phy: 1;
1379 u8 noa: 1;
1380 u8 band: 2;
1381
1382 u8 client_ps: 1;
1383 u8 bw: 7;
1384
1385 u8 role;
1386 u8 ch;
1387
1388 u16 tx_lvl;
1389 u16 rx_lvl;
1390 u16 tx_rate;
1391 u16 rx_rate;
1392 };
1393
1394 struct rtw89_btc_wl_active_role_v1 {
1395 u8 connected: 1;
1396 u8 pid: 3;
1397 u8 phy: 1;
1398 u8 noa: 1;
1399 u8 band: 2;
1400
1401 u8 client_ps: 1;
1402 u8 bw: 7;
1403
1404 u8 role;
1405 u8 ch;
1406
1407 u16 tx_lvl;
1408 u16 rx_lvl;
1409 u16 tx_rate;
1410 u16 rx_rate;
1411
1412 u32 noa_duration; /* ms */
1413 };
1414
1415 struct rtw89_btc_wl_active_role_v2 {
1416 u8 connected: 1;
1417 u8 pid: 3;
1418 u8 phy: 1;
1419 u8 noa: 1;
1420 u8 band: 2;
1421
1422 u8 client_ps: 1;
1423 u8 bw: 7;
1424
1425 u8 role;
1426 u8 ch;
1427
1428 u32 noa_duration; /* ms */
1429 };
1430
1431 struct rtw89_btc_wl_role_info_bpos {
1432 u16 none: 1;
1433 u16 station: 1;
1434 u16 ap: 1;
1435 u16 vap: 1;
1436 u16 adhoc: 1;
1437 u16 adhoc_master: 1;
1438 u16 mesh: 1;
1439 u16 moniter: 1;
1440 u16 p2p_device: 1;
1441 u16 p2p_gc: 1;
1442 u16 p2p_go: 1;
1443 u16 nan: 1;
1444 };
1445
1446 struct rtw89_btc_wl_scc_ctrl {
1447 u8 null_role1;
1448 u8 null_role2;
1449 u8 ebt_null; /* if tx null at EBT slot */
1450 };
1451
1452 union rtw89_btc_wl_role_info_map {
1453 u16 val;
1454 struct rtw89_btc_wl_role_info_bpos role;
1455 };
1456
1457 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1458 u8 connect_cnt;
1459 u8 link_mode;
1460 union rtw89_btc_wl_role_info_map role_map;
1461 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1462 };
1463
1464 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1465 u8 connect_cnt;
1466 u8 link_mode;
1467 union rtw89_btc_wl_role_info_map role_map;
1468 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1469 u32 mrole_type; /* btc_wl_mrole_type */
1470 u32 mrole_noa_duration; /* ms */
1471
1472 u32 dbcc_en: 1;
1473 u32 dbcc_chg: 1;
1474 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1475 u32 link_mode_chg: 1;
1476 u32 rsvd: 27;
1477 };
1478
1479 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1480 u8 connect_cnt;
1481 u8 link_mode;
1482 union rtw89_btc_wl_role_info_map role_map;
1483 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1484 u32 mrole_type; /* btc_wl_mrole_type */
1485 u32 mrole_noa_duration; /* ms */
1486
1487 u32 dbcc_en: 1;
1488 u32 dbcc_chg: 1;
1489 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1490 u32 link_mode_chg: 1;
1491 u32 rsvd: 27;
1492 };
1493
1494 struct rtw89_btc_wl_ver_info {
1495 u32 fw_coex; /* match with which coex_ver */
1496 u32 fw;
1497 u32 mac;
1498 u32 bb;
1499 u32 rf;
1500 };
1501
1502 struct rtw89_btc_wl_afh_info {
1503 u8 en;
1504 u8 ch;
1505 u8 bw;
1506 u8 rsvd;
1507 } __packed;
1508
1509 struct rtw89_btc_wl_rfk_info {
1510 u32 state: 2;
1511 u32 path_map: 4;
1512 u32 phy_map: 2;
1513 u32 band: 2;
1514 u32 type: 8;
1515 u32 rsvd: 14;
1516 };
1517
1518 struct rtw89_btc_bt_smap {
1519 u32 connect: 1;
1520 u32 ble_connect: 1;
1521 u32 acl_busy: 1;
1522 u32 sco_busy: 1;
1523 u32 mesh_busy: 1;
1524 u32 inq_pag: 1;
1525 };
1526
1527 union rtw89_btc_bt_state_map {
1528 u32 val;
1529 struct rtw89_btc_bt_smap map;
1530 };
1531
1532 #define BTC_BT_RSSI_THMAX 4
1533 #define BTC_BT_AFH_GROUP 12
1534 #define BTC_BT_AFH_LE_GROUP 5
1535
1536 struct rtw89_btc_bt_link_info {
1537 struct rtw89_btc_u8_sta_chg profile_cnt;
1538 struct rtw89_btc_bool_sta_chg multi_link;
1539 struct rtw89_btc_bool_sta_chg relink;
1540 struct rtw89_btc_bt_hfp_desc hfp_desc;
1541 struct rtw89_btc_bt_hid_desc hid_desc;
1542 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1543 struct rtw89_btc_bt_pan_desc pan_desc;
1544 union rtw89_btc_bt_state_map status;
1545
1546 u8 sut_pwr_level[BTC_PROFILE_MAX];
1547 u8 golden_rx_shift[BTC_PROFILE_MAX];
1548 u8 rssi_state[BTC_BT_RSSI_THMAX];
1549 u8 afh_map[BTC_BT_AFH_GROUP];
1550 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1551
1552 u32 role_sw: 1;
1553 u32 slave_role: 1;
1554 u32 afh_update: 1;
1555 u32 cqddr: 1;
1556 u32 rssi: 8;
1557 u32 tx_3m: 1;
1558 u32 rsvd: 19;
1559 };
1560
1561 struct rtw89_btc_3rdcx_info {
1562 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1563 u8 hw_coex;
1564 u16 rsvd;
1565 };
1566
1567 struct rtw89_btc_dm_emap {
1568 u32 init: 1;
1569 u32 pta_owner: 1;
1570 u32 wl_rfk_timeout: 1;
1571 u32 bt_rfk_timeout: 1;
1572 u32 wl_fw_hang: 1;
1573 u32 cycle_hang: 1;
1574 u32 w1_hang: 1;
1575 u32 b1_hang: 1;
1576 u32 tdma_no_sync: 1;
1577 u32 slot_no_sync: 1;
1578 u32 wl_slot_drift: 1;
1579 u32 bt_slot_drift: 1;
1580 u32 role_num_mismatch: 1;
1581 u32 null1_tx_late: 1;
1582 u32 bt_afh_conflict: 1;
1583 u32 bt_leafh_conflict: 1;
1584 u32 bt_slot_flood: 1;
1585 u32 wl_e2g_hang: 1;
1586 u32 wl_ver_mismatch: 1;
1587 u32 bt_ver_mismatch: 1;
1588 };
1589
1590 union rtw89_btc_dm_error_map {
1591 u32 val;
1592 struct rtw89_btc_dm_emap map;
1593 };
1594
1595 struct rtw89_btc_rf_para {
1596 u32 tx_pwr_freerun;
1597 u32 rx_gain_freerun;
1598 u32 tx_pwr_perpkt;
1599 u32 rx_gain_perpkt;
1600 };
1601
1602 struct rtw89_btc_wl_nhm {
1603 u8 instant_wl_nhm_dbm;
1604 u8 instant_wl_nhm_per_mhz;
1605 u16 valid_record_times;
1606 s8 record_pwr[16];
1607 u8 record_ratio[16];
1608 s8 pwr; /* dbm_per_MHz */
1609 u8 ratio;
1610 u8 current_status;
1611 u8 refresh;
1612 bool start_flag;
1613 s8 pwr_max;
1614 s8 pwr_min;
1615 };
1616
1617 struct rtw89_btc_wl_info {
1618 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1619 struct rtw89_btc_wl_rfk_info rfk_info;
1620 struct rtw89_btc_wl_ver_info ver_info;
1621 struct rtw89_btc_wl_afh_info afh_info;
1622 struct rtw89_btc_wl_role_info role_info;
1623 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1624 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1625 struct rtw89_btc_wl_scan_info scan_info;
1626 struct rtw89_btc_wl_dbcc_info dbcc_info;
1627 struct rtw89_btc_rf_para rf_para;
1628 struct rtw89_btc_wl_nhm nhm;
1629 union rtw89_btc_wl_state_map status;
1630
1631 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1632 u8 rssi_level;
1633 u8 cn_report;
1634
1635 bool scbd_change;
1636 u32 scbd;
1637 };
1638
1639 struct rtw89_btc_module {
1640 struct rtw89_btc_ant_info ant;
1641 u8 rfe_type;
1642 u8 cv;
1643
1644 u8 bt_solo: 1;
1645 u8 bt_pos: 1;
1646 u8 switch_type: 1;
1647 u8 wa_type: 3;
1648
1649 u8 kt_ver_adie;
1650 };
1651
1652 #define RTW89_BTC_DM_MAXSTEP 30
1653 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1654
1655 struct rtw89_btc_dm_step {
1656 u16 step[RTW89_BTC_DM_MAXSTEP];
1657 u8 step_pos;
1658 bool step_ov;
1659 };
1660
1661 struct rtw89_btc_init_info {
1662 struct rtw89_btc_module module;
1663 u8 wl_guard_ch;
1664
1665 u8 wl_only: 1;
1666 u8 wl_init_ok: 1;
1667 u8 dbcc_en: 1;
1668 u8 cx_other: 1;
1669 u8 bt_only: 1;
1670
1671 u16 rsvd;
1672 };
1673
1674 struct rtw89_btc_wl_tx_limit_para {
1675 u16 enable;
1676 u32 tx_time; /* unit: us */
1677 u16 tx_retry;
1678 };
1679
1680 enum rtw89_btc_bt_scan_type {
1681 BTC_SCAN_INQ = 0,
1682 BTC_SCAN_PAGE,
1683 BTC_SCAN_BLE,
1684 BTC_SCAN_INIT,
1685 BTC_SCAN_TV,
1686 BTC_SCAN_ADV,
1687 BTC_SCAN_MAX1,
1688 };
1689
1690 enum rtw89_btc_ble_scan_type {
1691 CXSCAN_BG = 0,
1692 CXSCAN_INIT,
1693 CXSCAN_LE,
1694 CXSCAN_MAX
1695 };
1696
1697 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1698 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1699
1700 struct rtw89_btc_bt_scan_info_v1 {
1701 __le16 win;
1702 __le16 intvl;
1703 __le32 flags;
1704 } __packed;
1705
1706 struct rtw89_btc_bt_scan_info_v2 {
1707 __le16 win;
1708 __le16 intvl;
1709 } __packed;
1710
1711 struct rtw89_btc_fbtc_btscan_v1 {
1712 u8 fver; /* btc_ver::fcxbtscan */
1713 u8 rsvd;
1714 __le16 rsvd2;
1715 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1716 } __packed;
1717
1718 struct rtw89_btc_fbtc_btscan_v2 {
1719 u8 fver; /* btc_ver::fcxbtscan */
1720 u8 type;
1721 __le16 rsvd2;
1722 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1723 } __packed;
1724
1725 union rtw89_btc_fbtc_btscan {
1726 struct rtw89_btc_fbtc_btscan_v1 v1;
1727 struct rtw89_btc_fbtc_btscan_v2 v2;
1728 };
1729
1730 struct rtw89_btc_bt_info {
1731 struct rtw89_btc_bt_link_info link_info;
1732 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
1733 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
1734 struct rtw89_btc_bt_ver_info ver_info;
1735 struct rtw89_btc_bool_sta_chg enable;
1736 struct rtw89_btc_bool_sta_chg inq_pag;
1737 struct rtw89_btc_rf_para rf_para;
1738 union rtw89_btc_bt_rfk_info_map rfk_info;
1739
1740 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1741
1742 u32 scbd;
1743 u32 feature;
1744
1745 u32 mbx_avl: 1;
1746 u32 whql_test: 1;
1747 u32 igno_wl: 1;
1748 u32 reinit: 1;
1749 u32 ble_scan_en: 1;
1750 u32 btg_type: 1;
1751 u32 inq: 1;
1752 u32 pag: 1;
1753 u32 run_patch_code: 1;
1754 u32 hi_lna_rx: 1;
1755 u32 scan_rx_low_pri: 1;
1756 u32 scan_info_update: 1;
1757 u32 rsvd: 20;
1758 };
1759
1760 struct rtw89_btc_cx {
1761 struct rtw89_btc_wl_info wl;
1762 struct rtw89_btc_bt_info bt;
1763 struct rtw89_btc_3rdcx_info other;
1764 u32 state_map;
1765 u32 cnt_bt[BTC_BCNT_NUM];
1766 u32 cnt_wl[BTC_WCNT_NUM];
1767 };
1768
1769 struct rtw89_btc_fbtc_tdma {
1770 u8 type; /* btc_ver::fcxtdma */
1771 u8 rxflctrl;
1772 u8 txpause;
1773 u8 wtgle_n;
1774 u8 leak_n;
1775 u8 ext_ctrl;
1776 u8 rxflctrl_role;
1777 u8 option_ctrl;
1778 } __packed;
1779
1780 struct rtw89_btc_fbtc_tdma_v3 {
1781 u8 fver; /* btc_ver::fcxtdma */
1782 u8 rsvd;
1783 __le16 rsvd1;
1784 struct rtw89_btc_fbtc_tdma tdma;
1785 } __packed;
1786
1787 union rtw89_btc_fbtc_tdma_le32 {
1788 struct rtw89_btc_fbtc_tdma v1;
1789 struct rtw89_btc_fbtc_tdma_v3 v3;
1790 };
1791
1792 #define CXMREG_MAX 30
1793 #define CXMREG_MAX_V2 20
1794 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1795 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1796
1797 enum rtw89_btc_bt_sta_counter {
1798 BTC_BCNT_RFK_REQ = 0,
1799 BTC_BCNT_RFK_GO = 1,
1800 BTC_BCNT_RFK_REJECT = 2,
1801 BTC_BCNT_RFK_FAIL = 3,
1802 BTC_BCNT_RFK_TIMEOUT = 4,
1803 BTC_BCNT_HI_TX = 5,
1804 BTC_BCNT_HI_RX = 6,
1805 BTC_BCNT_LO_TX = 7,
1806 BTC_BCNT_LO_RX = 8,
1807 BTC_BCNT_POLLUTED = 9,
1808 BTC_BCNT_STA_MAX
1809 };
1810
1811 enum rtw89_btc_bt_sta_counter_v105 {
1812 BTC_BCNT_RFK_REQ_V105 = 0,
1813 BTC_BCNT_HI_TX_V105 = 1,
1814 BTC_BCNT_HI_RX_V105 = 2,
1815 BTC_BCNT_LO_TX_V105 = 3,
1816 BTC_BCNT_LO_RX_V105 = 4,
1817 BTC_BCNT_POLLUTED_V105 = 5,
1818 BTC_BCNT_STA_MAX_V105
1819 };
1820
1821 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
1822 u16 fver; /* btc_ver::fcxbtcrpt */
1823 u16 rpt_cnt; /* tmr counters */
1824 u32 wl_fw_coex_ver; /* match which driver's coex version */
1825 u32 wl_fw_cx_offload;
1826 u32 wl_fw_ver;
1827 u32 rpt_enable;
1828 u32 rpt_para; /* ms */
1829 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1830 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1831 u32 mb_recv_cnt; /* fw recv mailbox counter */
1832 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1833 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1834 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1835 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
1836 u32 c2h_cnt; /* fw send c2h counter */
1837 u32 h2c_cnt; /* fw recv h2c counter */
1838 } __packed;
1839
1840 struct rtw89_btc_fbtc_rpt_ctrl_info {
1841 __le32 cnt; /* fw report counter */
1842 __le32 en; /* report map */
1843 __le32 para; /* not used */
1844
1845 __le32 cnt_c2h; /* fw send c2h counter */
1846 __le32 cnt_h2c; /* fw recv h2c counter */
1847 __le32 len_c2h; /* The total length of the last C2H */
1848
1849 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1850 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1851 } __packed;
1852
1853 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
1854 __le32 cx_ver; /* match which driver's coex version */
1855 __le32 fw_ver;
1856 __le32 en; /* report map */
1857
1858 __le16 cnt; /* fw report counter */
1859 __le16 cnt_c2h; /* fw send c2h counter */
1860 __le16 cnt_h2c; /* fw recv h2c counter */
1861 __le16 len_c2h; /* The total length of the last C2H */
1862
1863 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1864 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1865 } __packed;
1866
1867 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
1868 __le32 cx_ver; /* match which driver's coex version */
1869 __le32 cx_offload;
1870 __le32 fw_ver;
1871 } __packed;
1872
1873 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
1874 __le32 cnt_empty; /* a2dp empty count */
1875 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
1876 __le32 cnt_tx;
1877 __le32 cnt_ack;
1878 __le32 cnt_nack;
1879 } __packed;
1880
1881 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
1882 __le32 cnt_send_ok; /* fw send mailbox ok counter */
1883 __le32 cnt_send_fail; /* fw send mailbox fail counter */
1884 __le32 cnt_recv; /* fw recv mailbox counter */
1885 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
1886 } __packed;
1887
1888 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
1889 u8 fver;
1890 u8 rsvd;
1891 __le16 rsvd1;
1892 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
1893 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
1894 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1895 __le32 bt_cnt[BTC_BCNT_STA_MAX];
1896 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
1897 } __packed;
1898
1899 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
1900 u8 fver;
1901 u8 rsvd;
1902 __le16 rsvd1;
1903
1904 u8 gnt_val[RTW89_PHY_MAX][4];
1905 __le16 bt_cnt[BTC_BCNT_STA_MAX];
1906
1907 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1908 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1909 } __packed;
1910
1911 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
1912 u8 fver;
1913 u8 rsvd;
1914 __le16 rsvd1;
1915
1916 u8 gnt_val[RTW89_PHY_MAX][4];
1917 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
1918
1919 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1920 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1921 } __packed;
1922
1923 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
1924 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
1925 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
1926 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
1927 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
1928 };
1929
1930 enum rtw89_fbtc_ext_ctrl_type {
1931 CXECTL_OFF = 0x0, /* tdma off */
1932 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1933 CXECTL_EXT = 0x2,
1934 CXECTL_MAX
1935 };
1936
1937 union rtw89_btc_fbtc_rxflct {
1938 u8 val;
1939 u8 type: 3;
1940 u8 tgln_n: 5;
1941 };
1942
1943 enum rtw89_btc_cxst_state {
1944 CXST_OFF = 0x0,
1945 CXST_B2W = 0x1,
1946 CXST_W1 = 0x2,
1947 CXST_W2 = 0x3,
1948 CXST_W2B = 0x4,
1949 CXST_B1 = 0x5,
1950 CXST_B2 = 0x6,
1951 CXST_B3 = 0x7,
1952 CXST_B4 = 0x8,
1953 CXST_LK = 0x9,
1954 CXST_BLK = 0xa,
1955 CXST_E2G = 0xb,
1956 CXST_E5G = 0xc,
1957 CXST_EBT = 0xd,
1958 CXST_ENULL = 0xe,
1959 CXST_WLK = 0xf,
1960 CXST_W1FDD = 0x10,
1961 CXST_B1FDD = 0x11,
1962 CXST_MAX = 0x12,
1963 };
1964
1965 enum rtw89_btc_cxevnt {
1966 CXEVNT_TDMA_ENTRY = 0x0,
1967 CXEVNT_WL_TMR,
1968 CXEVNT_B1_TMR,
1969 CXEVNT_B2_TMR,
1970 CXEVNT_B3_TMR,
1971 CXEVNT_B4_TMR,
1972 CXEVNT_W2B_TMR,
1973 CXEVNT_B2W_TMR,
1974 CXEVNT_BCN_EARLY,
1975 CXEVNT_A2DP_EMPTY,
1976 CXEVNT_LK_END,
1977 CXEVNT_RX_ISR,
1978 CXEVNT_RX_FC0,
1979 CXEVNT_RX_FC1,
1980 CXEVNT_BT_RELINK,
1981 CXEVNT_BT_RETRY,
1982 CXEVNT_E2G,
1983 CXEVNT_E5G,
1984 CXEVNT_EBT,
1985 CXEVNT_ENULL,
1986 CXEVNT_DRV_WLK,
1987 CXEVNT_BCN_OK,
1988 CXEVNT_BT_CHANGE,
1989 CXEVNT_EBT_EXTEND,
1990 CXEVNT_E2G_NULL1,
1991 CXEVNT_B1FDD_TMR,
1992 CXEVNT_MAX
1993 };
1994
1995 enum {
1996 CXBCN_ALL = 0x0,
1997 CXBCN_ALL_OK,
1998 CXBCN_BT_SLOT,
1999 CXBCN_BT_OK,
2000 CXBCN_MAX
2001 };
2002
2003 enum btc_slot_type {
2004 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2005 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2006 CXSTYPE_NUM,
2007 };
2008
2009 enum { /* TIME */
2010 CXT_BT = 0x0,
2011 CXT_WL = 0x1,
2012 CXT_MAX
2013 };
2014
2015 enum { /* TIME-A2DP */
2016 CXT_FLCTRL_OFF = 0x0,
2017 CXT_FLCTRL_ON = 0x1,
2018 CXT_FLCTRL_MAX
2019 };
2020
2021 enum { /* STEP TYPE */
2022 CXSTEP_NONE = 0x0,
2023 CXSTEP_EVNT = 0x1,
2024 CXSTEP_SLOT = 0x2,
2025 CXSTEP_MAX,
2026 };
2027
2028 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2029 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2030 RPT_BT_AFH_SEQ_LE = 0x20
2031 };
2032
2033 #define BTC_DBG_MAX1 32
2034 struct rtw89_btc_fbtc_gpio_dbg {
2035 u8 fver; /* btc_ver::fcxgpiodbg */
2036 u8 rsvd;
2037 u16 rsvd2;
2038 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2039 u32 pre_state; /* the debug signal is 1 or 0 */
2040 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2041 } __packed;
2042
2043 struct rtw89_btc_fbtc_mreg_val_v1 {
2044 u8 fver; /* btc_ver::fcxmreg */
2045 u8 reg_num;
2046 __le16 rsvd;
2047 __le32 mreg_val[CXMREG_MAX];
2048 } __packed;
2049
2050 struct rtw89_btc_fbtc_mreg_val_v2 {
2051 u8 fver; /* btc_ver::fcxmreg */
2052 u8 reg_num;
2053 __le16 rsvd;
2054 __le32 mreg_val[CXMREG_MAX_V2];
2055 } __packed;
2056
2057 union rtw89_btc_fbtc_mreg_val {
2058 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2059 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2060 };
2061
2062 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2063 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2064 .offset = cpu_to_le32(__offset), }
2065
2066 struct rtw89_btc_fbtc_mreg {
2067 __le16 type;
2068 __le16 bytes;
2069 __le32 offset;
2070 } __packed;
2071
2072 struct rtw89_btc_fbtc_slot {
2073 __le16 dur;
2074 __le32 cxtbl;
2075 __le16 cxtype;
2076 } __packed;
2077
2078 struct rtw89_btc_fbtc_slots {
2079 u8 fver; /* btc_ver::fcxslots */
2080 u8 tbl_num;
2081 __le16 rsvd;
2082 __le32 update_map;
2083 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2084 } __packed;
2085
2086 struct rtw89_btc_fbtc_step {
2087 u8 type;
2088 u8 val;
2089 __le16 difft;
2090 } __packed;
2091
2092 struct rtw89_btc_fbtc_steps_v2 {
2093 u8 fver; /* btc_ver::fcxstep */
2094 u8 rsvd;
2095 __le16 cnt;
2096 __le16 pos_old;
2097 __le16 pos_new;
2098 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2099 } __packed;
2100
2101 struct rtw89_btc_fbtc_steps_v3 {
2102 u8 fver;
2103 u8 en;
2104 __le16 rsvd;
2105 __le32 cnt;
2106 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2107 } __packed;
2108
2109 union rtw89_btc_fbtc_steps_info {
2110 struct rtw89_btc_fbtc_steps_v2 v2;
2111 struct rtw89_btc_fbtc_steps_v3 v3;
2112 };
2113
2114 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2115 u8 fver; /* btc_ver::fcxcysta */
2116 u8 rsvd;
2117 __le16 cycles; /* total cycle number */
2118 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2119 __le16 a2dpept; /* a2dp empty cnt */
2120 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2121 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2122 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2123 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2124 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2125 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2126 __le16 tavg_a2dpept; /* avg a2dp empty time */
2127 __le16 tmax_a2dpept; /* max a2dp empty time */
2128 __le16 tavg_lk; /* avg leak-slot time */
2129 __le16 tmax_lk; /* max leak-slot time */
2130 __le32 slot_cnt[CXST_MAX]; /* slot count */
2131 __le32 bcn_cnt[CXBCN_MAX];
2132 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2133 __le32 collision_cnt; /* counter for event/timer occur at same time */
2134 __le32 skip_cnt;
2135 __le32 exception;
2136 __le32 except_cnt;
2137 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2138 } __packed;
2139
2140 struct rtw89_btc_fbtc_fdd_try_info {
2141 __le16 cycles[CXT_FLCTRL_MAX];
2142 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2143 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2144 } __packed;
2145
2146 struct rtw89_btc_fbtc_cycle_time_info {
2147 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2148 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2149 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2150 } __packed;
2151
2152 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2153 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2154 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2155 } __packed;
2156
2157 struct rtw89_btc_fbtc_a2dp_trx_stat {
2158 u8 empty_cnt;
2159 u8 retry_cnt;
2160 u8 tx_rate;
2161 u8 tx_cnt;
2162 u8 ack_cnt;
2163 u8 nack_cnt;
2164 u8 rsvd1;
2165 u8 rsvd2;
2166 } __packed;
2167
2168 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2169 u8 empty_cnt;
2170 u8 retry_cnt;
2171 u8 tx_rate;
2172 u8 tx_cnt;
2173 u8 ack_cnt;
2174 u8 nack_cnt;
2175 u8 no_empty_cnt;
2176 u8 rsvd;
2177 } __packed;
2178
2179 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2180 __le16 cnt; /* a2dp empty cnt */
2181 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2182 __le16 tavg; /* avg a2dp empty time */
2183 __le16 tmax; /* max a2dp empty time */
2184 } __packed;
2185
2186 struct rtw89_btc_fbtc_cycle_leak_info {
2187 __le32 cnt_rximr; /* the rximr occur at leak slot */
2188 __le16 tavg; /* avg leak-slot time */
2189 __le16 tmax; /* max leak-slot time */
2190 } __packed;
2191
2192 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2193 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2194
2195 struct rtw89_btc_fbtc_cycle_fddt_info {
2196 __le16 train_cycle;
2197 __le16 tp;
2198
2199 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2200 s8 bt_tx_power; /* decrease Tx power (dB) */
2201 s8 bt_rx_gain; /* LNA constrain level */
2202 u8 no_empty_cnt;
2203
2204 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2205 u8 cn; /* condition_num */
2206 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2207 u8 train_result; /* refer to enum btc_fddt_check_map */
2208 } __packed;
2209
2210 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2211 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2212
2213 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2214 __le16 train_cycle;
2215 __le16 tp;
2216
2217 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2218 s8 bt_tx_power; /* decrease Tx power (dB) */
2219 s8 bt_rx_gain; /* LNA constrain level */
2220 u8 no_empty_cnt;
2221
2222 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2223 u8 cn; /* condition_num */
2224 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2225 u8 train_result; /* refer to enum btc_fddt_check_map */
2226 } __packed;
2227
2228 struct rtw89_btc_fbtc_fddt_cell_status {
2229 s8 wl_tx_pwr;
2230 s8 bt_tx_pwr;
2231 s8 bt_rx_gain;
2232 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2233 } __packed;
2234
2235 struct rtw89_btc_fbtc_fddt_cell_status_v5 {
2236 s8 wl_tx_pwr;
2237 s8 bt_tx_pwr;
2238 s8 bt_rx_gain;
2239 } __packed;
2240
2241 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2242 u8 fver;
2243 u8 rsvd;
2244 __le16 cycles; /* total cycle number */
2245 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2246 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2247 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2248 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2249 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2250 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2251 __le32 slot_cnt[CXST_MAX]; /* slot count */
2252 __le32 bcn_cnt[CXBCN_MAX];
2253 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2254 __le32 skip_cnt;
2255 __le32 except_cnt;
2256 __le32 except_map;
2257 } __packed;
2258
2259 #define FDD_TRAIN_WL_DIRECTION 2
2260 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2261 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2262
2263 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2264 u8 fver;
2265 u8 rsvd;
2266 u8 collision_cnt; /* counter for event/timer occur at the same time */
2267 u8 except_cnt;
2268
2269 __le16 skip_cnt;
2270 __le16 cycles; /* total cycle number */
2271
2272 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2273 __le16 slot_cnt[CXST_MAX]; /* slot count */
2274 __le16 bcn_cnt[CXBCN_MAX];
2275 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2276 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2277 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2278 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2279 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2280 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2281 [FDD_TRAIN_WL_RSSI_LEVEL]
2282 [FDD_TRAIN_BT_RSSI_LEVEL];
2283 __le32 except_map;
2284 } __packed;
2285
2286 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2287 u8 fver;
2288 u8 rsvd;
2289 u8 collision_cnt; /* counter for event/timer occur at the same time */
2290 u8 except_cnt;
2291 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2292
2293 __le16 skip_cnt;
2294 __le16 cycles; /* total cycle number */
2295
2296 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2297 __le16 slot_cnt[CXST_MAX]; /* slot count */
2298 __le16 bcn_cnt[CXBCN_MAX];
2299 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2300 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2301 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2302 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2303 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2304 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION]
2305 [FDD_TRAIN_WL_RSSI_LEVEL]
2306 [FDD_TRAIN_BT_RSSI_LEVEL];
2307 __le32 except_map;
2308 } __packed;
2309
2310 union rtw89_btc_fbtc_cysta_info {
2311 struct rtw89_btc_fbtc_cysta_v2 v2;
2312 struct rtw89_btc_fbtc_cysta_v3 v3;
2313 struct rtw89_btc_fbtc_cysta_v4 v4;
2314 struct rtw89_btc_fbtc_cysta_v5 v5;
2315 };
2316
2317 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2318 u8 fver; /* btc_ver::fcxnullsta */
2319 u8 rsvd;
2320 __le16 rsvd2;
2321 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2322 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2323 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2324 } __packed;
2325
2326 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2327 u8 fver; /* btc_ver::fcxnullsta */
2328 u8 rsvd;
2329 __le16 rsvd2;
2330 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2331 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2332 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2333 } __packed;
2334
2335 union rtw89_btc_fbtc_cynullsta_info {
2336 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2337 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2338 };
2339
2340 struct rtw89_btc_fbtc_btver {
2341 u8 fver; /* btc_ver::fcxbtver */
2342 u8 rsvd;
2343 __le16 rsvd2;
2344 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2345 __le32 fw_ver;
2346 __le32 feature;
2347 } __packed;
2348
2349 struct rtw89_btc_fbtc_btafh {
2350 u8 fver; /* btc_ver::fcxbtafh */
2351 u8 rsvd;
2352 __le16 rsvd2;
2353 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2354 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2355 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2356 } __packed;
2357
2358 struct rtw89_btc_fbtc_btafh_v2 {
2359 u8 fver; /* btc_ver::fcxbtafh */
2360 u8 rsvd;
2361 u8 rsvd2;
2362 u8 map_type;
2363 u8 afh_l[4];
2364 u8 afh_m[4];
2365 u8 afh_h[4];
2366 u8 afh_le_a[4];
2367 u8 afh_le_b[4];
2368 } __packed;
2369
2370 struct rtw89_btc_fbtc_btdevinfo {
2371 u8 fver; /* btc_ver::fcxbtdevinfo */
2372 u8 rsvd;
2373 __le16 vendor_id;
2374 __le32 dev_name; /* only 24 bits valid */
2375 __le32 flush_time;
2376 } __packed;
2377
2378 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2379 struct rtw89_btc_rf_trx_para {
2380 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2381 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2382 u8 bt_tx_power; /* decrease Tx power (dB) */
2383 u8 bt_rx_gain; /* LNA constrain level */
2384 };
2385
2386 struct rtw89_btc_trx_info {
2387 u8 tx_lvl;
2388 u8 rx_lvl;
2389 u8 wl_rssi;
2390 u8 bt_rssi;
2391
2392 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2393 s8 rx_gain; /* rx gain table index (TBD.) */
2394 s8 bt_tx_power; /* decrease Tx power (dB) */
2395 s8 bt_rx_gain; /* LNA constrain level */
2396
2397 u8 cn; /* condition_num */
2398 s8 nhm;
2399 u8 bt_profile;
2400 u8 rsvd2;
2401
2402 u16 tx_rate;
2403 u16 rx_rate;
2404
2405 u32 tx_tp;
2406 u32 rx_tp;
2407 u32 rx_err_ratio;
2408 };
2409
2410 struct rtw89_btc_dm {
2411 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2412 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
2413 struct rtw89_btc_fbtc_tdma tdma;
2414 struct rtw89_btc_fbtc_tdma tdma_now;
2415 struct rtw89_mac_ax_coex_gnt gnt;
2416 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
2417 struct rtw89_btc_rf_trx_para rf_trx_para;
2418 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2419 struct rtw89_btc_dm_step dm_step;
2420 struct rtw89_btc_wl_scc_ctrl wl_scc;
2421 struct rtw89_btc_trx_info trx_info;
2422 union rtw89_btc_dm_error_map error;
2423 u32 cnt_dm[BTC_DCNT_NUM];
2424 u32 cnt_notify[BTC_NCNT_NUM];
2425
2426 u32 update_slot_map;
2427 u32 set_ant_path;
2428
2429 u32 wl_only: 1;
2430 u32 wl_fw_cx_offload: 1;
2431 u32 freerun: 1;
2432 u32 fddt_train: 1;
2433 u32 wl_ps_ctrl: 2;
2434 u32 wl_mimo_ps: 1;
2435 u32 leak_ap: 1;
2436 u32 noisy_level: 3;
2437 u32 coex_info_map: 8;
2438 u32 bt_only: 1;
2439 u32 wl_btg_rx: 1;
2440 u32 trx_para_level: 8;
2441 u32 wl_stb_chg: 1;
2442 u32 pta_owner: 1;
2443 u32 tdma_instant_excute: 1;
2444
2445 u16 slot_dur[CXST_MAX];
2446
2447 u8 run_reason;
2448 u8 run_action;
2449
2450 u8 wl_lna2: 1;
2451 };
2452
2453 struct rtw89_btc_ctrl {
2454 u32 manual: 1;
2455 u32 igno_bt: 1;
2456 u32 always_freerun: 1;
2457 u32 trace_step: 16;
2458 u32 rsvd: 12;
2459 };
2460
2461 struct rtw89_btc_dbg {
2462 /* cmd "rb" */
2463 bool rb_done;
2464 u32 rb_val;
2465 };
2466
2467 enum rtw89_btc_btf_fw_event {
2468 BTF_EVNT_RPT = 0,
2469 BTF_EVNT_BT_INFO = 1,
2470 BTF_EVNT_BT_SCBD = 2,
2471 BTF_EVNT_BT_REG = 3,
2472 BTF_EVNT_CX_RUNINFO = 4,
2473 BTF_EVNT_BT_PSD = 5,
2474 BTF_EVNT_BUF_OVERFLOW,
2475 BTF_EVNT_C2H_LOOPBACK,
2476 BTF_EVNT_MAX,
2477 };
2478
2479 enum btf_fw_event_report {
2480 BTC_RPT_TYPE_CTRL = 0x0,
2481 BTC_RPT_TYPE_TDMA,
2482 BTC_RPT_TYPE_SLOT,
2483 BTC_RPT_TYPE_CYSTA,
2484 BTC_RPT_TYPE_STEP,
2485 BTC_RPT_TYPE_NULLSTA,
2486 BTC_RPT_TYPE_MREG,
2487 BTC_RPT_TYPE_GPIO_DBG,
2488 BTC_RPT_TYPE_BT_VER,
2489 BTC_RPT_TYPE_BT_SCAN,
2490 BTC_RPT_TYPE_BT_AFH,
2491 BTC_RPT_TYPE_BT_DEVICE,
2492 BTC_RPT_TYPE_TEST,
2493 BTC_RPT_TYPE_MAX = 31
2494 };
2495
2496 enum rtw_btc_btf_reg_type {
2497 REG_MAC = 0x0,
2498 REG_BB = 0x1,
2499 REG_RF = 0x2,
2500 REG_BT_RF = 0x3,
2501 REG_BT_MODEM = 0x4,
2502 REG_BT_BLUEWIZE = 0x5,
2503 REG_BT_VENDOR = 0x6,
2504 REG_BT_LE = 0x7,
2505 REG_MAX_TYPE,
2506 };
2507
2508 struct rtw89_btc_rpt_cmn_info {
2509 u32 rx_cnt;
2510 u32 rx_len;
2511 u32 req_len; /* expected rsp len */
2512 u8 req_fver; /* expected rsp fver */
2513 u8 rsp_fver; /* fver from fw */
2514 u8 valid;
2515 } __packed;
2516
2517 union rtw89_btc_fbtc_btafh_info {
2518 struct rtw89_btc_fbtc_btafh v1;
2519 struct rtw89_btc_fbtc_btafh_v2 v2;
2520 };
2521
2522 struct rtw89_btc_report_ctrl_state {
2523 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2524 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2525 };
2526
2527 struct rtw89_btc_rpt_fbtc_tdma {
2528 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2529 union rtw89_btc_fbtc_tdma_le32 finfo;
2530 };
2531
2532 struct rtw89_btc_rpt_fbtc_slots {
2533 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2534 struct rtw89_btc_fbtc_slots finfo; /* info from fw */
2535 };
2536
2537 struct rtw89_btc_rpt_fbtc_cysta {
2538 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2539 union rtw89_btc_fbtc_cysta_info finfo;
2540 };
2541
2542 struct rtw89_btc_rpt_fbtc_step {
2543 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2544 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2545 };
2546
2547 struct rtw89_btc_rpt_fbtc_nullsta {
2548 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2549 union rtw89_btc_fbtc_cynullsta_info finfo;
2550 };
2551
2552 struct rtw89_btc_rpt_fbtc_mreg {
2553 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2554 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
2555 };
2556
2557 struct rtw89_btc_rpt_fbtc_gpio_dbg {
2558 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2559 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
2560 };
2561
2562 struct rtw89_btc_rpt_fbtc_btver {
2563 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2564 struct rtw89_btc_fbtc_btver finfo; /* info from fw */
2565 };
2566
2567 struct rtw89_btc_rpt_fbtc_btscan {
2568 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2569 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
2570 };
2571
2572 struct rtw89_btc_rpt_fbtc_btafh {
2573 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2574 union rtw89_btc_fbtc_btafh_info finfo;
2575 };
2576
2577 struct rtw89_btc_rpt_fbtc_btdev {
2578 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2579 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
2580 };
2581
2582 enum rtw89_btc_btfre_type {
2583 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
2584 BTFRE_UNDEF_TYPE,
2585 BTFRE_EXCEPTION,
2586 BTFRE_MAX,
2587 };
2588
2589 struct rtw89_btc_btf_fwinfo {
2590 u32 cnt_c2h;
2591 u32 cnt_h2c;
2592 u32 cnt_h2c_fail;
2593 u32 event[BTF_EVNT_MAX];
2594
2595 u32 err[BTFRE_MAX];
2596 u32 len_mismch;
2597 u32 fver_mismch;
2598 u32 rpt_en_map;
2599
2600 struct rtw89_btc_report_ctrl_state rpt_ctrl;
2601 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
2602 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
2603 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
2604 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
2605 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
2606 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
2607 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
2608 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
2609 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
2610 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
2611 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
2612 };
2613
2614 struct rtw89_btc_ver {
2615 enum rtw89_core_chip_id chip_id;
2616 u32 fw_ver_code;
2617
2618 u8 fcxbtcrpt;
2619 u8 fcxtdma;
2620 u8 fcxslots;
2621 u8 fcxcysta;
2622 u8 fcxstep;
2623 u8 fcxnullsta;
2624 u8 fcxmreg;
2625 u8 fcxgpiodbg;
2626 u8 fcxbtver;
2627 u8 fcxbtscan;
2628 u8 fcxbtafh;
2629 u8 fcxbtdevinfo;
2630 u8 fwlrole;
2631 u8 frptmap;
2632 u8 fcxctrl;
2633
2634 u16 info_buf;
2635 u8 max_role_num;
2636 };
2637
2638 #define RTW89_BTC_POLICY_MAXLEN 512
2639
2640 struct rtw89_btc {
2641 const struct rtw89_btc_ver *ver;
2642
2643 struct rtw89_btc_cx cx;
2644 struct rtw89_btc_dm dm;
2645 struct rtw89_btc_ctrl ctrl;
2646 struct rtw89_btc_module mdinfo;
2647 struct rtw89_btc_btf_fwinfo fwinfo;
2648 struct rtw89_btc_dbg dbg;
2649
2650 struct work_struct eapol_notify_work;
2651 struct work_struct arp_notify_work;
2652 struct work_struct dhcp_notify_work;
2653 struct work_struct icmp_notify_work;
2654
2655 u32 bt_req_len;
2656
2657 u8 policy[RTW89_BTC_POLICY_MAXLEN];
2658 u16 policy_len;
2659 u16 policy_type;
2660 bool bt_req_en;
2661 bool update_policy_force;
2662 bool lps;
2663 };
2664
2665 enum rtw89_ra_mode {
2666 RTW89_RA_MODE_CCK = BIT(0),
2667 RTW89_RA_MODE_OFDM = BIT(1),
2668 RTW89_RA_MODE_HT = BIT(2),
2669 RTW89_RA_MODE_VHT = BIT(3),
2670 RTW89_RA_MODE_HE = BIT(4),
2671 };
2672
2673 enum rtw89_ra_report_mode {
2674 RTW89_RA_RPT_MODE_LEGACY,
2675 RTW89_RA_RPT_MODE_HT,
2676 RTW89_RA_RPT_MODE_VHT,
2677 RTW89_RA_RPT_MODE_HE,
2678 };
2679
2680 enum rtw89_dig_noisy_level {
2681 RTW89_DIG_NOISY_LEVEL0 = -1,
2682 RTW89_DIG_NOISY_LEVEL1 = 0,
2683 RTW89_DIG_NOISY_LEVEL2 = 1,
2684 RTW89_DIG_NOISY_LEVEL3 = 2,
2685 RTW89_DIG_NOISY_LEVEL_MAX = 3,
2686 };
2687
2688 enum rtw89_gi_ltf {
2689 RTW89_GILTF_LGI_4XHE32 = 0,
2690 RTW89_GILTF_SGI_4XHE08 = 1,
2691 RTW89_GILTF_2XHE16 = 2,
2692 RTW89_GILTF_2XHE08 = 3,
2693 RTW89_GILTF_1XHE16 = 4,
2694 RTW89_GILTF_1XHE08 = 5,
2695 RTW89_GILTF_MAX
2696 };
2697
2698 enum rtw89_rx_frame_type {
2699 RTW89_RX_TYPE_MGNT = 0,
2700 RTW89_RX_TYPE_CTRL = 1,
2701 RTW89_RX_TYPE_DATA = 2,
2702 RTW89_RX_TYPE_RSVD = 3,
2703 };
2704
2705 struct rtw89_ra_info {
2706 u8 is_dis_ra:1;
2707 /* Bit0 : CCK
2708 * Bit1 : OFDM
2709 * Bit2 : HT
2710 * Bit3 : VHT
2711 * Bit4 : HE
2712 * Bit5 : EHT
2713 */
2714 u8 mode_ctrl:6;
2715 u8 bw_cap:3; /* enum rtw89_bandwidth */
2716 u8 macid;
2717 u8 dcm_cap:1;
2718 u8 er_cap:1;
2719 u8 init_rate_lv:2;
2720 u8 upd_all:1;
2721 u8 en_sgi:1;
2722 u8 ldpc_cap:1;
2723 u8 stbc_cap:1;
2724 u8 ss_num:3;
2725 u8 giltf:3;
2726 u8 upd_bw_nss_mask:1;
2727 u8 upd_mask:1;
2728 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
2729 /* BFee CSI */
2730 u8 band_num;
2731 u8 ra_csi_rate_en:1;
2732 u8 fixed_csi_rate_en:1;
2733 u8 cr_tbl_sel:1;
2734 u8 fix_giltf_en:1;
2735 u8 fix_giltf:3;
2736 u8 rsvd2:1;
2737 u8 csi_mcs_ss_idx;
2738 u8 csi_mode:2;
2739 u8 csi_gi_ltf:3;
2740 u8 csi_bw:3;
2741 };
2742
2743 #define RTW89_PPDU_MAX_USR 4
2744 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
2745 #define RTW89_PPDU_MAC_INFO_SIZE 8
2746 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
2747
2748 #define RTW89_MAX_RX_AGG_NUM 64
2749 #define RTW89_MAX_TX_AGG_NUM 128
2750
2751 struct rtw89_ampdu_params {
2752 u16 agg_num;
2753 bool amsdu;
2754 };
2755
2756 struct rtw89_ra_report {
2757 struct rate_info txrate;
2758 u32 bit_rate;
2759 u16 hw_rate;
2760 bool might_fallback_legacy;
2761 };
2762
2763 DECLARE_EWMA(rssi, 10, 16);
2764 DECLARE_EWMA(evm, 10, 16);
2765 DECLARE_EWMA(snr, 10, 16);
2766
2767 struct rtw89_ba_cam_entry {
2768 struct list_head list;
2769 u8 tid;
2770 };
2771
2772 #define RTW89_MAX_ADDR_CAM_NUM 128
2773 #define RTW89_MAX_BSSID_CAM_NUM 20
2774 #define RTW89_MAX_SEC_CAM_NUM 128
2775 #define RTW89_MAX_BA_CAM_NUM 8
2776 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
2777
2778 struct rtw89_addr_cam_entry {
2779 u8 addr_cam_idx;
2780 u8 offset;
2781 u8 len;
2782 u8 valid : 1;
2783 u8 addr_mask : 6;
2784 u8 wapi : 1;
2785 u8 mask_sel : 2;
2786 u8 bssid_cam_idx: 6;
2787
2788 u8 sec_ent_mode;
2789 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
2790 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
2791 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
2792 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
2793 };
2794
2795 struct rtw89_bssid_cam_entry {
2796 u8 bssid[ETH_ALEN];
2797 u8 phy_idx;
2798 u8 bssid_cam_idx;
2799 u8 offset;
2800 u8 len;
2801 u8 valid : 1;
2802 u8 num;
2803 };
2804
2805 struct rtw89_sec_cam_entry {
2806 u8 sec_cam_idx;
2807 u8 offset;
2808 u8 len;
2809 u8 type : 4;
2810 u8 ext_key : 1;
2811 u8 spp_mode : 1;
2812 /* 256 bits */
2813 u8 key[32];
2814 };
2815
2816 struct rtw89_sta {
2817 u8 mac_id;
2818 bool disassoc;
2819 bool er_cap;
2820 struct rtw89_dev *rtwdev;
2821 struct rtw89_vif *rtwvif;
2822 struct rtw89_ra_info ra;
2823 struct rtw89_ra_report ra_report;
2824 int max_agg_wait;
2825 u8 prev_rssi;
2826 struct ewma_rssi avg_rssi;
2827 struct ewma_rssi rssi[RF_PATH_MAX];
2828 struct ewma_snr avg_snr;
2829 struct ewma_evm evm_min[RF_PATH_MAX];
2830 struct ewma_evm evm_max[RF_PATH_MAX];
2831 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
2832 struct ieee80211_rx_status rx_status;
2833 u16 rx_hw_rate;
2834 __le32 htc_template;
2835 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
2836 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2837 struct list_head ba_cam_list;
2838 struct sk_buff_head roc_queue;
2839
2840 bool use_cfg_mask;
2841 struct cfg80211_bitrate_mask mask;
2842
2843 bool cctl_tx_time;
2844 u32 ampdu_max_time:4;
2845 bool cctl_tx_retry_limit;
2846 u32 data_tx_cnt_lmt:6;
2847 };
2848
2849 struct rtw89_efuse {
2850 bool valid;
2851 bool power_k_valid;
2852 u8 xtal_cap;
2853 u8 addr[ETH_ALEN];
2854 u8 rfe_type;
2855 char country_code[2];
2856 };
2857
2858 struct rtw89_phy_rate_pattern {
2859 u64 ra_mask;
2860 u16 rate;
2861 u8 ra_mode;
2862 bool enable;
2863 };
2864
2865 struct rtw89_tx_wait_info {
2866 struct rcu_head rcu_head;
2867 struct completion completion;
2868 bool tx_done;
2869 };
2870
2871 struct rtw89_tx_skb_data {
2872 struct rtw89_tx_wait_info __rcu *wait;
2873 u8 hci_priv[];
2874 };
2875
2876 #define RTW89_ROC_IDLE_TIMEOUT 500
2877 #define RTW89_ROC_TX_TIMEOUT 30
2878 enum rtw89_roc_state {
2879 RTW89_ROC_IDLE,
2880 RTW89_ROC_NORMAL,
2881 RTW89_ROC_MGMT,
2882 };
2883
2884 struct rtw89_roc {
2885 struct ieee80211_channel chan;
2886 struct delayed_work roc_work;
2887 enum ieee80211_roc_type type;
2888 enum rtw89_roc_state state;
2889 int duration;
2890 };
2891
2892 #define RTW89_P2P_MAX_NOA_NUM 2
2893
2894 struct rtw89_vif {
2895 struct list_head list;
2896 struct rtw89_dev *rtwdev;
2897 struct rtw89_roc roc;
2898 enum rtw89_sub_entity_idx sub_entity_idx;
2899 enum rtw89_reg_6ghz_power reg_6ghz_power;
2900
2901 u8 mac_id;
2902 u8 port;
2903 u8 mac_addr[ETH_ALEN];
2904 u8 bssid[ETH_ALEN];
2905 u8 phy_idx;
2906 u8 mac_idx;
2907 u8 net_type;
2908 u8 wifi_role;
2909 u8 self_role;
2910 u8 wmm;
2911 u8 bcn_hit_cond;
2912 u8 hit_rule;
2913 u8 last_noa_nr;
2914 bool offchan;
2915 bool trigger;
2916 bool lsig_txop;
2917 u8 tgt_ind;
2918 u8 frm_tgt_ind;
2919 bool wowlan_pattern;
2920 bool wowlan_uc;
2921 bool wowlan_magic;
2922 bool is_hesta;
2923 bool last_a_ctrl;
2924 bool dyn_tb_bedge_en;
2925 u8 def_tri_idx;
2926 u32 tdls_peer;
2927 struct work_struct update_beacon_work;
2928 struct rtw89_addr_cam_entry addr_cam;
2929 struct rtw89_bssid_cam_entry bssid_cam;
2930 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2931 struct rtw89_traffic_stats stats;
2932 struct rtw89_phy_rate_pattern rate_pattern;
2933 struct cfg80211_scan_request *scan_req;
2934 struct ieee80211_scan_ies *scan_ies;
2935 struct list_head general_pkt_list;
2936 };
2937
2938 enum rtw89_lv1_rcvy_step {
2939 RTW89_LV1_RCVY_STEP_1,
2940 RTW89_LV1_RCVY_STEP_2,
2941 };
2942
2943 struct rtw89_hci_ops {
2944 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2945 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2946 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2947 void (*reset)(struct rtw89_dev *rtwdev);
2948 int (*start)(struct rtw89_dev *rtwdev);
2949 void (*stop)(struct rtw89_dev *rtwdev);
2950 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2951 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
2952 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2953
2954 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2955 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2956 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2957 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2958 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2959 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2960
2961 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2962 int (*mac_post_init)(struct rtw89_dev *rtwdev);
2963 int (*deinit)(struct rtw89_dev *rtwdev);
2964
2965 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
2966 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
2967 void (*dump_err_status)(struct rtw89_dev *rtwdev);
2968 int (*napi_poll)(struct napi_struct *napi, int budget);
2969
2970 /* Deal with locks inside recovery_start and recovery_complete callbacks
2971 * by hci instance, and handle things which need to consider under SER.
2972 * e.g. turn on/off interrupts except for the one for halt notification.
2973 */
2974 void (*recovery_start)(struct rtw89_dev *rtwdev);
2975 void (*recovery_complete)(struct rtw89_dev *rtwdev);
2976
2977 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
2978 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
2979 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
2980 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
2981 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
2982 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
2983 void (*disable_intr)(struct rtw89_dev *rtwdev);
2984 void (*enable_intr)(struct rtw89_dev *rtwdev);
2985 int (*rst_bdram)(struct rtw89_dev *rtwdev);
2986 };
2987
2988 struct rtw89_hci_info {
2989 const struct rtw89_hci_ops *ops;
2990 enum rtw89_hci_type type;
2991 u32 rpwm_addr;
2992 u32 cpwm_addr;
2993 bool paused;
2994 };
2995
2996 struct rtw89_chip_ops {
2997 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
2998 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
2999 void (*bb_reset)(struct rtw89_dev *rtwdev,
3000 enum rtw89_phy_idx phy_idx);
3001 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3002 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3003 u32 addr, u32 mask);
3004 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3005 u32 addr, u32 mask, u32 data);
3006 void (*set_channel)(struct rtw89_dev *rtwdev,
3007 const struct rtw89_chan *chan,
3008 enum rtw89_mac_idx mac_idx,
3009 enum rtw89_phy_idx phy_idx);
3010 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3011 struct rtw89_channel_help_params *p,
3012 const struct rtw89_chan *chan,
3013 enum rtw89_mac_idx mac_idx,
3014 enum rtw89_phy_idx phy_idx);
3015 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
3016 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3017 void (*fem_setup)(struct rtw89_dev *rtwdev);
3018 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3019 void (*rfk_init)(struct rtw89_dev *rtwdev);
3020 void (*rfk_channel)(struct rtw89_dev *rtwdev);
3021 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3022 enum rtw89_phy_idx phy_idx);
3023 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
3024 void (*rfk_track)(struct rtw89_dev *rtwdev);
3025 void (*power_trim)(struct rtw89_dev *rtwdev);
3026 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3027 const struct rtw89_chan *chan,
3028 enum rtw89_phy_idx phy_idx);
3029 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3030 enum rtw89_phy_idx phy_idx);
3031 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3032 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3033 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
3034 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3035 struct rtw89_rx_phy_ppdu *phy_ppdu,
3036 struct ieee80211_rx_status *status);
3037 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
3038 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3039 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3040 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3041 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3042 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3043 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3044 struct rtw89_rx_desc_info *desc_info,
3045 u8 *data, u32 data_offset);
3046 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3047 struct rtw89_tx_desc_info *desc_info,
3048 void *txdesc);
3049 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3050 struct rtw89_tx_desc_info *desc_info,
3051 void *txdesc);
3052 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3053 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3054 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3055 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3056 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3057 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3058 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3059 struct rtw89_vif *rtwvif,
3060 struct rtw89_sta *rtwsta);
3061
3062 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3063 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3064 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3065 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3066 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3067 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3068 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3069 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3070 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3071 };
3072
3073 enum rtw89_dma_ch {
3074 RTW89_DMA_ACH0 = 0,
3075 RTW89_DMA_ACH1 = 1,
3076 RTW89_DMA_ACH2 = 2,
3077 RTW89_DMA_ACH3 = 3,
3078 RTW89_DMA_ACH4 = 4,
3079 RTW89_DMA_ACH5 = 5,
3080 RTW89_DMA_ACH6 = 6,
3081 RTW89_DMA_ACH7 = 7,
3082 RTW89_DMA_B0MG = 8,
3083 RTW89_DMA_B0HI = 9,
3084 RTW89_DMA_B1MG = 10,
3085 RTW89_DMA_B1HI = 11,
3086 RTW89_DMA_H2C = 12,
3087 RTW89_DMA_CH_NUM = 13
3088 };
3089
3090 enum rtw89_qta_mode {
3091 RTW89_QTA_SCC,
3092 RTW89_QTA_DLFW,
3093 RTW89_QTA_WOW,
3094
3095 /* keep last */
3096 RTW89_QTA_INVALID,
3097 };
3098
3099 struct rtw89_hfc_ch_cfg {
3100 u16 min;
3101 u16 max;
3102 #define grp_0 0
3103 #define grp_1 1
3104 #define grp_num 2
3105 u8 grp;
3106 };
3107
3108 struct rtw89_hfc_ch_info {
3109 u16 aval;
3110 u16 used;
3111 };
3112
3113 struct rtw89_hfc_pub_cfg {
3114 u16 grp0;
3115 u16 grp1;
3116 u16 pub_max;
3117 u16 wp_thrd;
3118 };
3119
3120 struct rtw89_hfc_pub_info {
3121 u16 g0_used;
3122 u16 g1_used;
3123 u16 g0_aval;
3124 u16 g1_aval;
3125 u16 pub_aval;
3126 u16 wp_aval;
3127 };
3128
3129 struct rtw89_hfc_prec_cfg {
3130 u16 ch011_prec;
3131 u16 h2c_prec;
3132 u16 wp_ch07_prec;
3133 u16 wp_ch811_prec;
3134 u8 ch011_full_cond;
3135 u8 h2c_full_cond;
3136 u8 wp_ch07_full_cond;
3137 u8 wp_ch811_full_cond;
3138 };
3139
3140 struct rtw89_hfc_param {
3141 bool en;
3142 bool h2c_en;
3143 u8 mode;
3144 const struct rtw89_hfc_ch_cfg *ch_cfg;
3145 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3146 struct rtw89_hfc_pub_cfg pub_cfg;
3147 struct rtw89_hfc_pub_info pub_info;
3148 struct rtw89_hfc_prec_cfg prec_cfg;
3149 };
3150
3151 struct rtw89_hfc_param_ini {
3152 const struct rtw89_hfc_ch_cfg *ch_cfg;
3153 const struct rtw89_hfc_pub_cfg *pub_cfg;
3154 const struct rtw89_hfc_prec_cfg *prec_cfg;
3155 u8 mode;
3156 };
3157
3158 struct rtw89_dle_size {
3159 u16 pge_size;
3160 u16 lnk_pge_num;
3161 u16 unlnk_pge_num;
3162 };
3163
3164 struct rtw89_wde_quota {
3165 u16 hif;
3166 u16 wcpu;
3167 u16 pkt_in;
3168 u16 cpu_io;
3169 };
3170
3171 struct rtw89_ple_quota {
3172 u16 cma0_tx;
3173 u16 cma1_tx;
3174 u16 c2h;
3175 u16 h2c;
3176 u16 wcpu;
3177 u16 mpdu_proc;
3178 u16 cma0_dma;
3179 u16 cma1_dma;
3180 u16 bb_rpt;
3181 u16 wd_rel;
3182 u16 cpu_io;
3183 u16 tx_rpt;
3184 };
3185
3186 struct rtw89_dle_mem {
3187 enum rtw89_qta_mode mode;
3188 const struct rtw89_dle_size *wde_size;
3189 const struct rtw89_dle_size *ple_size;
3190 const struct rtw89_wde_quota *wde_min_qt;
3191 const struct rtw89_wde_quota *wde_max_qt;
3192 const struct rtw89_ple_quota *ple_min_qt;
3193 const struct rtw89_ple_quota *ple_max_qt;
3194 };
3195
3196 struct rtw89_reg_def {
3197 u32 addr;
3198 u32 mask;
3199 };
3200
3201 struct rtw89_reg2_def {
3202 u32 addr;
3203 u32 data;
3204 };
3205
3206 struct rtw89_reg3_def {
3207 u32 addr;
3208 u32 mask;
3209 u32 data;
3210 };
3211
3212 struct rtw89_reg5_def {
3213 u8 flag; /* recognized by parsers */
3214 u8 path;
3215 u32 addr;
3216 u32 mask;
3217 u32 data;
3218 };
3219
3220 struct rtw89_phy_table {
3221 const struct rtw89_reg2_def *regs;
3222 u32 n_regs;
3223 enum rtw89_rf_path rf_path;
3224 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3225 enum rtw89_rf_path rf_path, void *data);
3226 };
3227
3228 struct rtw89_txpwr_table {
3229 const void *data;
3230 u32 size;
3231 void (*load)(struct rtw89_dev *rtwdev,
3232 const struct rtw89_txpwr_table *tbl);
3233 };
3234
3235 struct rtw89_txpwr_rule_2ghz {
3236 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3237 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3238 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3239 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3240 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3241 };
3242
3243 struct rtw89_txpwr_rule_5ghz {
3244 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3245 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3246 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3247 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3248 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3249 };
3250
3251 struct rtw89_txpwr_rule_6ghz {
3252 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3253 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3254 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3255 [RTW89_6G_CH_NUM];
3256 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3257 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3258 [RTW89_6G_CH_NUM];
3259 };
3260
3261 struct rtw89_rfe_parms {
3262 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3263 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3264 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3265 };
3266
3267 struct rtw89_rfe_parms_conf {
3268 const struct rtw89_rfe_parms *rfe_parms;
3269 u8 rfe_type;
3270 };
3271
3272 struct rtw89_page_regs {
3273 u32 hci_fc_ctrl;
3274 u32 ch_page_ctrl;
3275 u32 ach_page_ctrl;
3276 u32 ach_page_info;
3277 u32 pub_page_info3;
3278 u32 pub_page_ctrl1;
3279 u32 pub_page_ctrl2;
3280 u32 pub_page_info1;
3281 u32 pub_page_info2;
3282 u32 wp_page_ctrl1;
3283 u32 wp_page_ctrl2;
3284 u32 wp_page_info1;
3285 };
3286
3287 struct rtw89_imr_info {
3288 u32 wdrls_imr_set;
3289 u32 wsec_imr_reg;
3290 u32 wsec_imr_set;
3291 u32 mpdu_tx_imr_set;
3292 u32 mpdu_rx_imr_set;
3293 u32 sta_sch_imr_set;
3294 u32 txpktctl_imr_b0_reg;
3295 u32 txpktctl_imr_b0_clr;
3296 u32 txpktctl_imr_b0_set;
3297 u32 txpktctl_imr_b1_reg;
3298 u32 txpktctl_imr_b1_clr;
3299 u32 txpktctl_imr_b1_set;
3300 u32 wde_imr_clr;
3301 u32 wde_imr_set;
3302 u32 ple_imr_clr;
3303 u32 ple_imr_set;
3304 u32 host_disp_imr_clr;
3305 u32 host_disp_imr_set;
3306 u32 cpu_disp_imr_clr;
3307 u32 cpu_disp_imr_set;
3308 u32 other_disp_imr_clr;
3309 u32 other_disp_imr_set;
3310 u32 bbrpt_com_err_imr_reg;
3311 u32 bbrpt_chinfo_err_imr_reg;
3312 u32 bbrpt_err_imr_set;
3313 u32 bbrpt_dfs_err_imr_reg;
3314 u32 ptcl_imr_clr;
3315 u32 ptcl_imr_set;
3316 u32 cdma_imr_0_reg;
3317 u32 cdma_imr_0_clr;
3318 u32 cdma_imr_0_set;
3319 u32 cdma_imr_1_reg;
3320 u32 cdma_imr_1_clr;
3321 u32 cdma_imr_1_set;
3322 u32 phy_intf_imr_reg;
3323 u32 phy_intf_imr_clr;
3324 u32 phy_intf_imr_set;
3325 u32 rmac_imr_reg;
3326 u32 rmac_imr_clr;
3327 u32 rmac_imr_set;
3328 u32 tmac_imr_reg;
3329 u32 tmac_imr_clr;
3330 u32 tmac_imr_set;
3331 };
3332
3333 struct rtw89_xtal_info {
3334 u32 xcap_reg;
3335 u32 sc_xo_mask;
3336 u32 sc_xi_mask;
3337 };
3338
3339 struct rtw89_rrsr_cfgs {
3340 struct rtw89_reg3_def ref_rate;
3341 struct rtw89_reg3_def rsc;
3342 };
3343
3344 struct rtw89_dig_regs {
3345 u32 seg0_pd_reg;
3346 u32 pd_lower_bound_mask;
3347 u32 pd_spatial_reuse_en;
3348 struct rtw89_reg_def p0_lna_init;
3349 struct rtw89_reg_def p1_lna_init;
3350 struct rtw89_reg_def p0_tia_init;
3351 struct rtw89_reg_def p1_tia_init;
3352 struct rtw89_reg_def p0_rxb_init;
3353 struct rtw89_reg_def p1_rxb_init;
3354 struct rtw89_reg_def p0_p20_pagcugc_en;
3355 struct rtw89_reg_def p0_s20_pagcugc_en;
3356 struct rtw89_reg_def p1_p20_pagcugc_en;
3357 struct rtw89_reg_def p1_s20_pagcugc_en;
3358 };
3359
3360 struct rtw89_phy_ul_tb_info {
3361 bool dyn_tb_tri_en;
3362 u8 def_if_bandedge;
3363 };
3364
3365 struct rtw89_antdiv_stats {
3366 struct ewma_rssi cck_rssi_avg;
3367 struct ewma_rssi ofdm_rssi_avg;
3368 struct ewma_rssi non_legacy_rssi_avg;
3369 u16 pkt_cnt_cck;
3370 u16 pkt_cnt_ofdm;
3371 u16 pkt_cnt_non_legacy;
3372 u32 evm;
3373 };
3374
3375 struct rtw89_antdiv_info {
3376 struct rtw89_antdiv_stats target_stats;
3377 struct rtw89_antdiv_stats main_stats;
3378 struct rtw89_antdiv_stats aux_stats;
3379 u8 training_count;
3380 u8 rssi_pre;
3381 bool get_stats;
3382 };
3383
3384 struct rtw89_chip_info {
3385 enum rtw89_core_chip_id chip_id;
3386 enum rtw89_chip_gen chip_gen;
3387 const struct rtw89_chip_ops *ops;
3388 const char *fw_basename;
3389 u8 fw_format_max;
3390 bool try_ce_fw;
3391 u32 needed_fw_elms;
3392 u32 fifo_size;
3393 bool small_fifo_size;
3394 u32 dle_scc_rsvd_size;
3395 u16 max_amsdu_limit;
3396 bool dis_2g_40m_ul_ofdma;
3397 u32 rsvd_ple_ofst;
3398 const struct rtw89_hfc_param_ini *hfc_param_ini;
3399 const struct rtw89_dle_mem *dle_mem;
3400 u8 wde_qempty_acq_num;
3401 u8 wde_qempty_mgq_sel;
3402 u32 rf_base_addr[2];
3403 u8 support_chanctx_num;
3404 u8 support_bands;
3405 bool support_bw160;
3406 bool support_unii4;
3407 bool support_ul_tb_ctrl;
3408 bool hw_sec_hdr;
3409 u8 rf_path_num;
3410 u8 tx_nss;
3411 u8 rx_nss;
3412 u8 acam_num;
3413 u8 bcam_num;
3414 u8 scam_num;
3415 u8 bacam_num;
3416 u8 bacam_dynamic_num;
3417 enum rtw89_bacam_ver bacam_ver;
3418
3419 u8 sec_ctrl_efuse_size;
3420 u32 physical_efuse_size;
3421 u32 logical_efuse_size;
3422 u32 limit_efuse_size;
3423 u32 dav_phy_efuse_size;
3424 u32 dav_log_efuse_size;
3425 u32 phycap_addr;
3426 u32 phycap_size;
3427
3428 const struct rtw89_pwr_cfg * const *pwr_on_seq;
3429 const struct rtw89_pwr_cfg * const *pwr_off_seq;
3430 const struct rtw89_phy_table *bb_table;
3431 const struct rtw89_phy_table *bb_gain_table;
3432 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
3433 const struct rtw89_phy_table *nctl_table;
3434 const struct rtw89_rfk_tbl *nctl_post_table;
3435 const struct rtw89_txpwr_table *byr_table;
3436 const struct rtw89_phy_dig_gain_table *dig_table;
3437 const struct rtw89_dig_regs *dig_regs;
3438 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
3439
3440 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
3441 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
3442 const struct rtw89_rfe_parms *dflt_parms;
3443
3444 u8 txpwr_factor_rf;
3445 u8 txpwr_factor_mac;
3446
3447 u32 para_ver;
3448 u32 wlcx_desired;
3449 u8 btcx_desired;
3450 u8 scbd;
3451 u8 mailbox;
3452
3453 u8 afh_guard_ch;
3454 const u8 *wl_rssi_thres;
3455 const u8 *bt_rssi_thres;
3456 u8 rssi_tol;
3457
3458 u8 mon_reg_num;
3459 const struct rtw89_btc_fbtc_mreg *mon_reg;
3460 u8 rf_para_ulink_num;
3461 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
3462 u8 rf_para_dlink_num;
3463 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
3464 u8 ps_mode_supported;
3465 u8 low_power_hci_modes;
3466
3467 u32 h2c_cctl_func_id;
3468 u32 hci_func_en_addr;
3469 u32 h2c_desc_size;
3470 u32 txwd_body_size;
3471 u32 h2c_ctrl_reg;
3472 const u32 *h2c_regs;
3473 struct rtw89_reg_def h2c_counter_reg;
3474 u32 c2h_ctrl_reg;
3475 const u32 *c2h_regs;
3476 struct rtw89_reg_def c2h_counter_reg;
3477 const struct rtw89_page_regs *page_regs;
3478 bool cfo_src_fd;
3479 bool cfo_hw_comp;
3480 const struct rtw89_reg_def *dcfo_comp;
3481 u8 dcfo_comp_sft;
3482 const struct rtw89_imr_info *imr_info;
3483 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
3484 u32 bss_clr_map_reg;
3485 u32 dma_ch_mask;
3486 u32 edcca_lvl_reg;
3487 const struct wiphy_wowlan_support *wowlan_stub;
3488 const struct rtw89_xtal_info *xtal_info;
3489 };
3490
3491 union rtw89_bus_info {
3492 const struct rtw89_pci_info *pci;
3493 };
3494
3495 struct rtw89_driver_info {
3496 const struct rtw89_chip_info *chip;
3497 union rtw89_bus_info bus;
3498 };
3499
3500 enum rtw89_hcifc_mode {
3501 RTW89_HCIFC_POH = 0,
3502 RTW89_HCIFC_STF = 1,
3503 RTW89_HCIFC_SDIO = 2,
3504
3505 /* keep last */
3506 RTW89_HCIFC_MODE_INVALID,
3507 };
3508
3509 struct rtw89_dle_info {
3510 enum rtw89_qta_mode qta_mode;
3511 u16 ple_pg_size;
3512 u16 c0_rx_qta;
3513 u16 c1_rx_qta;
3514 };
3515
3516 enum rtw89_host_rpr_mode {
3517 RTW89_RPR_MODE_POH = 0,
3518 RTW89_RPR_MODE_STF
3519 };
3520
3521 #define RTW89_COMPLETION_BUF_SIZE 24
3522 #define RTW89_WAIT_COND_IDLE UINT_MAX
3523
3524 struct rtw89_completion_data {
3525 bool err;
3526 u8 buf[RTW89_COMPLETION_BUF_SIZE];
3527 };
3528
3529 struct rtw89_wait_info {
3530 atomic_t cond;
3531 struct completion completion;
3532 struct rtw89_completion_data data;
3533 };
3534
3535 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
3536
rtw89_init_wait(struct rtw89_wait_info * wait)3537 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
3538 {
3539 init_completion(&wait->completion);
3540 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
3541 }
3542
3543 struct rtw89_mac_info {
3544 struct rtw89_dle_info dle_info;
3545 struct rtw89_hfc_param hfc_param;
3546 enum rtw89_qta_mode qta_mode;
3547 u8 rpwm_seq_num;
3548 u8 cpwm_seq_num;
3549
3550 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
3551 struct rtw89_wait_info fw_ofld_wait;
3552 };
3553
3554 enum rtw89_fw_type {
3555 RTW89_FW_NORMAL = 1,
3556 RTW89_FW_WOWLAN = 3,
3557 RTW89_FW_NORMAL_CE = 5,
3558 RTW89_FW_BBMCU0 = 64,
3559 RTW89_FW_BBMCU1 = 65,
3560 RTW89_FW_LOGFMT = 255,
3561 };
3562
3563 enum rtw89_fw_feature {
3564 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
3565 RTW89_FW_FEATURE_SCAN_OFFLOAD,
3566 RTW89_FW_FEATURE_TX_WAKE,
3567 RTW89_FW_FEATURE_CRASH_TRIGGER,
3568 RTW89_FW_FEATURE_NO_PACKET_DROP,
3569 RTW89_FW_FEATURE_NO_DEEP_PS,
3570 RTW89_FW_FEATURE_NO_LPS_PG,
3571 RTW89_FW_FEATURE_BEACON_FILTER,
3572 };
3573
3574 struct rtw89_fw_suit {
3575 enum rtw89_fw_type type;
3576 const u8 *data;
3577 u32 size;
3578 u8 major_ver;
3579 u8 minor_ver;
3580 u8 sub_ver;
3581 u8 sub_idex;
3582 u16 build_year;
3583 u16 build_mon;
3584 u16 build_date;
3585 u16 build_hour;
3586 u16 build_min;
3587 u8 cmd_ver;
3588 u8 hdr_ver;
3589 u32 commitid;
3590 };
3591
3592 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
3593 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
3594 #define RTW89_FW_SUIT_VER_CODE(s) \
3595 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
3596
3597 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
3598 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
3599 (mfw_hdr)->ver.minor, \
3600 (mfw_hdr)->ver.sub, \
3601 (mfw_hdr)->ver.idx)
3602
3603 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
3604 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
3605 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
3606 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
3607 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
3608
3609 struct rtw89_fw_req_info {
3610 const struct firmware *firmware;
3611 struct completion completion;
3612 };
3613
3614 struct rtw89_fw_log {
3615 struct rtw89_fw_suit suit;
3616 bool enable;
3617 u32 last_fmt_id;
3618 u32 fmt_count;
3619 const __le32 *fmt_ids;
3620 const char *(*fmts)[];
3621 };
3622
3623 struct rtw89_fw_elm_info {
3624 struct rtw89_phy_table *bb_tbl;
3625 struct rtw89_phy_table *bb_gain;
3626 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
3627 struct rtw89_phy_table *rf_nctl;
3628 };
3629
3630 struct rtw89_fw_info {
3631 struct rtw89_fw_req_info req;
3632 int fw_format;
3633 u8 h2c_seq;
3634 u8 rec_seq;
3635 u8 h2c_counter;
3636 u8 c2h_counter;
3637 struct rtw89_fw_suit normal;
3638 struct rtw89_fw_suit wowlan;
3639 struct rtw89_fw_suit bbmcu0;
3640 struct rtw89_fw_suit bbmcu1;
3641 struct rtw89_fw_log log;
3642 u32 feature_map;
3643 struct rtw89_fw_elm_info elm_info;
3644 };
3645
3646 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
3647 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
3648
3649 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
3650 ((_fw)->feature_map |= BIT(_fw_feature))
3651
3652 struct rtw89_cam_info {
3653 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
3654 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
3655 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
3656 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
3657 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
3658 };
3659
3660 enum rtw89_sar_sources {
3661 RTW89_SAR_SOURCE_NONE,
3662 RTW89_SAR_SOURCE_COMMON,
3663
3664 RTW89_SAR_SOURCE_NR,
3665 };
3666
3667 enum rtw89_sar_subband {
3668 RTW89_SAR_2GHZ_SUBBAND,
3669 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
3670 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
3671 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
3672 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
3673 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
3674 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
3675 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
3676 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
3677 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
3678
3679 RTW89_SAR_SUBBAND_NR,
3680 };
3681
3682 struct rtw89_sar_cfg_common {
3683 bool set[RTW89_SAR_SUBBAND_NR];
3684 s32 cfg[RTW89_SAR_SUBBAND_NR];
3685 };
3686
3687 struct rtw89_sar_info {
3688 /* used to decide how to acces SAR cfg union */
3689 enum rtw89_sar_sources src;
3690
3691 /* reserved for different knids of SAR cfg struct.
3692 * supposed that a single cfg struct cannot handle various SAR sources.
3693 */
3694 union {
3695 struct rtw89_sar_cfg_common cfg_common;
3696 };
3697 };
3698
3699 struct rtw89_chanctx_cfg {
3700 enum rtw89_sub_entity_idx idx;
3701 };
3702
3703 enum rtw89_entity_mode {
3704 RTW89_ENTITY_MODE_SCC,
3705 };
3706
3707 struct rtw89_sub_entity {
3708 struct cfg80211_chan_def chandef;
3709 struct rtw89_chan chan;
3710 struct rtw89_chan_rcd rcd;
3711 struct rtw89_chanctx_cfg *cfg;
3712 };
3713
3714 struct rtw89_hal {
3715 u32 rx_fltr;
3716 u8 cv;
3717 u8 acv;
3718 u32 antenna_tx;
3719 u32 antenna_rx;
3720 u8 tx_nss;
3721 u8 rx_nss;
3722 bool tx_path_diversity;
3723 bool ant_diversity;
3724 bool ant_diversity_fixed;
3725 bool support_cckpd;
3726 bool support_igi;
3727 atomic_t roc_entity_idx;
3728
3729 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
3730 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
3731 struct cfg80211_chan_def roc_chandef;
3732
3733 bool entity_active;
3734 enum rtw89_entity_mode entity_mode;
3735
3736 u32 edcca_bak;
3737 };
3738
3739 #define RTW89_MAX_MAC_ID_NUM 128
3740 #define RTW89_MAX_PKT_OFLD_NUM 255
3741
3742 enum rtw89_flags {
3743 RTW89_FLAG_POWERON,
3744 RTW89_FLAG_FW_RDY,
3745 RTW89_FLAG_RUNNING,
3746 RTW89_FLAG_BFEE_MON,
3747 RTW89_FLAG_BFEE_EN,
3748 RTW89_FLAG_BFEE_TIMER_KEEP,
3749 RTW89_FLAG_NAPI_RUNNING,
3750 RTW89_FLAG_LEISURE_PS,
3751 RTW89_FLAG_LOW_POWER_MODE,
3752 RTW89_FLAG_INACTIVE_PS,
3753 RTW89_FLAG_CRASH_SIMULATING,
3754 RTW89_FLAG_SER_HANDLING,
3755 RTW89_FLAG_WOWLAN,
3756 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
3757 RTW89_FLAG_CHANGING_INTERFACE,
3758
3759 NUM_OF_RTW89_FLAGS,
3760 };
3761
3762 enum rtw89_pkt_drop_sel {
3763 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
3764 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
3765 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
3766 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
3767 RTW89_PKT_DROP_SEL_MACID_ALL,
3768 RTW89_PKT_DROP_SEL_MG0_ONCE,
3769 RTW89_PKT_DROP_SEL_HIQ_ONCE,
3770 RTW89_PKT_DROP_SEL_HIQ_PORT,
3771 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
3772 RTW89_PKT_DROP_SEL_BAND,
3773 RTW89_PKT_DROP_SEL_BAND_ONCE,
3774 RTW89_PKT_DROP_SEL_REL_MACID,
3775 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
3776 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
3777 };
3778
3779 struct rtw89_pkt_drop_params {
3780 enum rtw89_pkt_drop_sel sel;
3781 enum rtw89_mac_idx mac_band;
3782 u8 macid;
3783 u8 port;
3784 u8 mbssid;
3785 bool tf_trs;
3786 u32 macid_band_sel[4];
3787 };
3788
3789 struct rtw89_pkt_stat {
3790 u16 beacon_nr;
3791 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
3792 };
3793
3794 DECLARE_EWMA(thermal, 4, 4);
3795
3796 struct rtw89_phy_stat {
3797 struct ewma_thermal avg_thermal[RF_PATH_MAX];
3798 struct rtw89_pkt_stat cur_pkt_stat;
3799 struct rtw89_pkt_stat last_pkt_stat;
3800 };
3801
3802 #define RTW89_DACK_PATH_NR 2
3803 #define RTW89_DACK_IDX_NR 2
3804 #define RTW89_DACK_MSBK_NR 16
3805 struct rtw89_dack_info {
3806 bool dack_done;
3807 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
3808 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3809 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3810 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3811 u32 dack_cnt;
3812 bool addck_timeout[RTW89_DACK_PATH_NR];
3813 bool dadck_timeout[RTW89_DACK_PATH_NR];
3814 bool msbk_timeout[RTW89_DACK_PATH_NR];
3815 };
3816
3817 #define RTW89_IQK_CHS_NR 2
3818 #define RTW89_IQK_PATH_NR 4
3819
3820 struct rtw89_rfk_mcc_info {
3821 u8 ch[RTW89_IQK_CHS_NR];
3822 u8 band[RTW89_IQK_CHS_NR];
3823 u8 table_idx;
3824 };
3825
3826 struct rtw89_lck_info {
3827 u8 thermal[RF_PATH_MAX];
3828 };
3829
3830 struct rtw89_rx_dck_info {
3831 u8 thermal[RF_PATH_MAX];
3832 };
3833
3834 struct rtw89_iqk_info {
3835 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3836 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3837 bool lok_fail[RTW89_IQK_PATH_NR];
3838 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3839 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3840 u32 iqk_fail_cnt;
3841 bool is_iqk_init;
3842 u32 iqk_channel[RTW89_IQK_CHS_NR];
3843 u8 iqk_band[RTW89_IQK_PATH_NR];
3844 u8 iqk_ch[RTW89_IQK_PATH_NR];
3845 u8 iqk_bw[RTW89_IQK_PATH_NR];
3846 u8 iqk_times;
3847 u8 version;
3848 u32 nb_txcfir[RTW89_IQK_PATH_NR];
3849 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
3850 u32 bp_txkresult[RTW89_IQK_PATH_NR];
3851 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
3852 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
3853 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
3854 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
3855 bool is_nbiqk;
3856 bool iqk_fft_en;
3857 bool iqk_xym_en;
3858 bool iqk_sram_en;
3859 bool iqk_cfir_en;
3860 u32 syn1to2;
3861 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3862 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
3863 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3864 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3865 };
3866
3867 #define RTW89_DPK_RF_PATH 2
3868 #define RTW89_DPK_AVG_THERMAL_NUM 8
3869 #define RTW89_DPK_BKUP_NUM 2
3870 struct rtw89_dpk_bkup_para {
3871 enum rtw89_band band;
3872 enum rtw89_bandwidth bw;
3873 u8 ch;
3874 bool path_ok;
3875 u8 mdpd_en;
3876 u8 txagc_dpk;
3877 u8 ther_dpk;
3878 u8 gs;
3879 u16 pwsf;
3880 };
3881
3882 struct rtw89_dpk_info {
3883 bool is_dpk_enable;
3884 bool is_dpk_reload_en;
3885 u8 dpk_gs[RTW89_PHY_MAX];
3886 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3887 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3888 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3889 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3890 u8 cur_idx[RTW89_DPK_RF_PATH];
3891 u8 cur_k_set;
3892 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3893 };
3894
3895 struct rtw89_fem_info {
3896 bool elna_2g;
3897 bool elna_5g;
3898 bool epa_2g;
3899 bool epa_5g;
3900 bool epa_6g;
3901 };
3902
3903 struct rtw89_phy_ch_info {
3904 u8 rssi_min;
3905 u16 rssi_min_macid;
3906 u8 pre_rssi_min;
3907 u8 rssi_max;
3908 u16 rssi_max_macid;
3909 u8 rxsc_160;
3910 u8 rxsc_80;
3911 u8 rxsc_40;
3912 u8 rxsc_20;
3913 u8 rxsc_l;
3914 u8 is_noisy;
3915 };
3916
3917 struct rtw89_agc_gaincode_set {
3918 u8 lna_idx;
3919 u8 tia_idx;
3920 u8 rxb_idx;
3921 };
3922
3923 #define IGI_RSSI_TH_NUM 5
3924 #define FA_TH_NUM 4
3925 #define LNA_GAIN_NUM 7
3926 #define TIA_GAIN_NUM 2
3927 struct rtw89_dig_info {
3928 struct rtw89_agc_gaincode_set cur_gaincode;
3929 bool force_gaincode_idx_en;
3930 struct rtw89_agc_gaincode_set force_gaincode;
3931 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
3932 u16 fa_th[FA_TH_NUM];
3933 u8 igi_rssi;
3934 u8 igi_fa_rssi;
3935 u8 fa_rssi_ofst;
3936 u8 dyn_igi_max;
3937 u8 dyn_igi_min;
3938 bool dyn_pd_th_en;
3939 u8 dyn_pd_th_max;
3940 u8 pd_low_th_ofst;
3941 u8 ib_pbk;
3942 s8 ib_pkpwr;
3943 s8 lna_gain_a[LNA_GAIN_NUM];
3944 s8 lna_gain_g[LNA_GAIN_NUM];
3945 s8 *lna_gain;
3946 s8 tia_gain_a[TIA_GAIN_NUM];
3947 s8 tia_gain_g[TIA_GAIN_NUM];
3948 s8 *tia_gain;
3949 bool is_linked_pre;
3950 bool bypass_dig;
3951 };
3952
3953 enum rtw89_multi_cfo_mode {
3954 RTW89_PKT_BASED_AVG_MODE = 0,
3955 RTW89_ENTRY_BASED_AVG_MODE = 1,
3956 RTW89_TP_BASED_AVG_MODE = 2,
3957 };
3958
3959 enum rtw89_phy_cfo_status {
3960 RTW89_PHY_DCFO_STATE_NORMAL = 0,
3961 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
3962 RTW89_PHY_DCFO_STATE_HOLD = 2,
3963 RTW89_PHY_DCFO_STATE_MAX
3964 };
3965
3966 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
3967 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
3968 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
3969 };
3970
3971 struct rtw89_cfo_tracking_info {
3972 u16 cfo_timer_ms;
3973 bool cfo_trig_by_timer_en;
3974 enum rtw89_phy_cfo_status phy_cfo_status;
3975 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
3976 u8 phy_cfo_trk_cnt;
3977 bool is_adjust;
3978 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
3979 bool apply_compensation;
3980 u8 crystal_cap;
3981 u8 crystal_cap_default;
3982 u8 def_x_cap;
3983 s8 x_cap_ofst;
3984 u32 sta_cfo_tolerance;
3985 s32 cfo_tail[CFO_TRACK_MAX_USER];
3986 u16 cfo_cnt[CFO_TRACK_MAX_USER];
3987 s32 cfo_avg_pre;
3988 s32 cfo_avg[CFO_TRACK_MAX_USER];
3989 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
3990 s32 dcfo_avg;
3991 s32 dcfo_avg_pre;
3992 u32 packet_count;
3993 u32 packet_count_pre;
3994 s32 residual_cfo_acc;
3995 u8 phy_cfotrk_state;
3996 u8 phy_cfotrk_cnt;
3997 bool divergence_lock_en;
3998 u8 x_cap_lb;
3999 u8 x_cap_ub;
4000 u8 lock_cnt;
4001 };
4002
4003 enum rtw89_tssi_alimk_band {
4004 TSSI_ALIMK_2G = 0,
4005 TSSI_ALIMK_5GL,
4006 TSSI_ALIMK_5GM,
4007 TSSI_ALIMK_5GH,
4008 TSSI_ALIMK_MAX
4009 };
4010
4011 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4012 #define TSSI_TRIM_CH_GROUP_NUM 8
4013 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4014
4015 #define TSSI_CCK_CH_GROUP_NUM 6
4016 #define TSSI_MCS_2G_CH_GROUP_NUM 5
4017 #define TSSI_MCS_5G_CH_GROUP_NUM 14
4018 #define TSSI_MCS_6G_CH_GROUP_NUM 32
4019 #define TSSI_MCS_CH_GROUP_NUM \
4020 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
4021 #define TSSI_MAX_CH_NUM 67
4022 #define TSSI_ALIMK_VALUE_NUM 8
4023
4024 struct rtw89_tssi_info {
4025 u8 thermal[RF_PATH_MAX];
4026 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
4027 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
4028 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
4029 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
4030 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
4031 s8 extra_ofst[RF_PATH_MAX];
4032 bool tssi_tracking_check[RF_PATH_MAX];
4033 u8 default_txagc_offset[RF_PATH_MAX];
4034 u32 base_thermal[RF_PATH_MAX];
4035 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
4036 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
4037 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
4038 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
4039 u32 tssi_alimk_time;
4040 };
4041
4042 struct rtw89_power_trim_info {
4043 bool pg_thermal_trim;
4044 bool pg_pa_bias_trim;
4045 u8 thermal_trim[RF_PATH_MAX];
4046 u8 pa_bias_trim[RF_PATH_MAX];
4047 };
4048
4049 struct rtw89_regd {
4050 char alpha2[3];
4051 u8 txpwr_regd[RTW89_BAND_NUM];
4052 };
4053
4054 struct rtw89_regulatory_info {
4055 const struct rtw89_regd *regd;
4056 enum rtw89_reg_6ghz_power reg_6ghz_power;
4057 };
4058
4059 enum rtw89_ifs_clm_application {
4060 RTW89_IFS_CLM_INIT = 0,
4061 RTW89_IFS_CLM_BACKGROUND = 1,
4062 RTW89_IFS_CLM_ACS = 2,
4063 RTW89_IFS_CLM_DIG = 3,
4064 RTW89_IFS_CLM_TDMA_DIG = 4,
4065 RTW89_IFS_CLM_DBG = 5,
4066 RTW89_IFS_CLM_DBG_MANUAL = 6
4067 };
4068
4069 enum rtw89_env_racing_lv {
4070 RTW89_RAC_RELEASE = 0,
4071 RTW89_RAC_LV_1 = 1,
4072 RTW89_RAC_LV_2 = 2,
4073 RTW89_RAC_LV_3 = 3,
4074 RTW89_RAC_LV_4 = 4,
4075 RTW89_RAC_MAX_NUM = 5
4076 };
4077
4078 struct rtw89_ccx_para_info {
4079 enum rtw89_env_racing_lv rac_lv;
4080 u16 mntr_time;
4081 u8 nhm_manual_th_ofst;
4082 u8 nhm_manual_th0;
4083 enum rtw89_ifs_clm_application ifs_clm_app;
4084 u32 ifs_clm_manual_th_times;
4085 u32 ifs_clm_manual_th0;
4086 u8 fahm_manual_th_ofst;
4087 u8 fahm_manual_th0;
4088 u8 fahm_numer_opt;
4089 u8 fahm_denom_opt;
4090 };
4091
4092 enum rtw89_ccx_edcca_opt_sc_idx {
4093 RTW89_CCX_EDCCA_SEG0_P0 = 0,
4094 RTW89_CCX_EDCCA_SEG0_S1 = 1,
4095 RTW89_CCX_EDCCA_SEG0_S2 = 2,
4096 RTW89_CCX_EDCCA_SEG0_S3 = 3,
4097 RTW89_CCX_EDCCA_SEG1_P0 = 4,
4098 RTW89_CCX_EDCCA_SEG1_S1 = 5,
4099 RTW89_CCX_EDCCA_SEG1_S2 = 6,
4100 RTW89_CCX_EDCCA_SEG1_S3 = 7
4101 };
4102
4103 enum rtw89_ccx_edcca_opt_bw_idx {
4104 RTW89_CCX_EDCCA_BW20_0 = 0,
4105 RTW89_CCX_EDCCA_BW20_1 = 1,
4106 RTW89_CCX_EDCCA_BW20_2 = 2,
4107 RTW89_CCX_EDCCA_BW20_3 = 3,
4108 RTW89_CCX_EDCCA_BW20_4 = 4,
4109 RTW89_CCX_EDCCA_BW20_5 = 5,
4110 RTW89_CCX_EDCCA_BW20_6 = 6,
4111 RTW89_CCX_EDCCA_BW20_7 = 7
4112 };
4113
4114 #define RTW89_NHM_TH_NUM 11
4115 #define RTW89_FAHM_TH_NUM 11
4116 #define RTW89_NHM_RPT_NUM 12
4117 #define RTW89_FAHM_RPT_NUM 12
4118 #define RTW89_IFS_CLM_NUM 4
4119 struct rtw89_env_monitor_info {
4120 u8 ccx_watchdog_result;
4121 bool ccx_ongoing;
4122 u8 ccx_rac_lv;
4123 bool ccx_manual_ctrl;
4124 u16 ifs_clm_mntr_time;
4125 enum rtw89_ifs_clm_application ifs_clm_app;
4126 u16 ccx_period;
4127 u8 ccx_unit_idx;
4128 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
4129 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
4130 u16 ifs_clm_tx;
4131 u16 ifs_clm_edcca_excl_cca;
4132 u16 ifs_clm_ofdmfa;
4133 u16 ifs_clm_ofdmcca_excl_fa;
4134 u16 ifs_clm_cckfa;
4135 u16 ifs_clm_cckcca_excl_fa;
4136 u16 ifs_clm_total_ifs;
4137 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
4138 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
4139 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
4140 u8 ifs_clm_tx_ratio;
4141 u8 ifs_clm_edcca_excl_cca_ratio;
4142 u8 ifs_clm_cck_fa_ratio;
4143 u8 ifs_clm_ofdm_fa_ratio;
4144 u8 ifs_clm_cck_cca_excl_fa_ratio;
4145 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
4146 u16 ifs_clm_cck_fa_permil;
4147 u16 ifs_clm_ofdm_fa_permil;
4148 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
4149 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
4150 };
4151
4152 enum rtw89_ser_rcvy_step {
4153 RTW89_SER_DRV_STOP_TX,
4154 RTW89_SER_DRV_STOP_RX,
4155 RTW89_SER_DRV_STOP_RUN,
4156 RTW89_SER_HAL_STOP_DMA,
4157 RTW89_SER_SUPPRESS_LOG,
4158 RTW89_NUM_OF_SER_FLAGS
4159 };
4160
4161 struct rtw89_ser {
4162 u8 state;
4163 u8 alarm_event;
4164 bool prehandle_l1;
4165
4166 struct work_struct ser_hdl_work;
4167 struct delayed_work ser_alarm_work;
4168 const struct state_ent *st_tbl;
4169 const struct event_ent *ev_tbl;
4170 struct list_head msg_q;
4171 spinlock_t msg_q_lock; /* lock when read/write ser msg */
4172 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
4173 };
4174
4175 enum rtw89_mac_ax_ps_mode {
4176 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
4177 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
4178 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
4179 RTW89_MAC_AX_PS_MODE_MAX = 3,
4180 };
4181
4182 enum rtw89_last_rpwm_mode {
4183 RTW89_LAST_RPWM_PS = 0x0,
4184 RTW89_LAST_RPWM_ACTIVE = 0x6,
4185 };
4186
4187 struct rtw89_lps_parm {
4188 u8 macid;
4189 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
4190 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
4191 };
4192
4193 struct rtw89_ppdu_sts_info {
4194 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
4195 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
4196 };
4197
4198 struct rtw89_early_h2c {
4199 struct list_head list;
4200 u8 *h2c;
4201 u16 h2c_len;
4202 };
4203
4204 struct rtw89_hw_scan_info {
4205 struct ieee80211_vif *scanning_vif;
4206 struct list_head pkt_list[NUM_NL80211_BANDS];
4207 struct rtw89_chan op_chan;
4208 u32 last_chan_idx;
4209 };
4210
4211 enum rtw89_phy_bb_gain_band {
4212 RTW89_BB_GAIN_BAND_2G = 0,
4213 RTW89_BB_GAIN_BAND_5G_L = 1,
4214 RTW89_BB_GAIN_BAND_5G_M = 2,
4215 RTW89_BB_GAIN_BAND_5G_H = 3,
4216 RTW89_BB_GAIN_BAND_6G_L = 4,
4217 RTW89_BB_GAIN_BAND_6G_M = 5,
4218 RTW89_BB_GAIN_BAND_6G_H = 6,
4219 RTW89_BB_GAIN_BAND_6G_UH = 7,
4220
4221 RTW89_BB_GAIN_BAND_NR,
4222 };
4223
4224 enum rtw89_phy_bb_rxsc_num {
4225 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
4226 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
4227 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
4228 };
4229
4230 struct rtw89_phy_bb_gain_info {
4231 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4232 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
4233 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4234 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4235 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4236 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
4237 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
4238 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4239 [RTW89_BB_RXSC_NUM_40];
4240 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4241 [RTW89_BB_RXSC_NUM_80];
4242 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4243 [RTW89_BB_RXSC_NUM_160];
4244 };
4245
4246 struct rtw89_phy_efuse_gain {
4247 bool offset_valid;
4248 bool comp_valid;
4249 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
4250 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
4251 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
4252 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
4253 };
4254
4255 #define RTW89_MAX_PATTERN_NUM 18
4256 #define RTW89_MAX_PATTERN_MASK_SIZE 4
4257 #define RTW89_MAX_PATTERN_SIZE 128
4258
4259 struct rtw89_wow_cam_info {
4260 bool r_w;
4261 u8 idx;
4262 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
4263 u16 crc;
4264 bool negative_pattern_match;
4265 bool skip_mac_hdr;
4266 bool uc;
4267 bool mc;
4268 bool bc;
4269 bool valid;
4270 };
4271
4272 struct rtw89_wow_param {
4273 struct ieee80211_vif *wow_vif;
4274 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
4275 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
4276 u8 pattern_cnt;
4277 };
4278
4279 struct rtw89_mcc_info {
4280 struct rtw89_wait_info wait;
4281 };
4282
4283 struct rtw89_dev {
4284 struct ieee80211_hw *hw;
4285 struct device *dev;
4286 const struct ieee80211_ops *ops;
4287
4288 bool dbcc_en;
4289 struct rtw89_hw_scan_info scan_info;
4290 const struct rtw89_chip_info *chip;
4291 const struct rtw89_pci_info *pci_info;
4292 const struct rtw89_rfe_parms *rfe_parms;
4293 struct rtw89_hal hal;
4294 struct rtw89_mcc_info mcc;
4295 struct rtw89_mac_info mac;
4296 struct rtw89_fw_info fw;
4297 struct rtw89_hci_info hci;
4298 struct rtw89_efuse efuse;
4299 struct rtw89_traffic_stats stats;
4300
4301 /* ensures exclusive access from mac80211 callbacks */
4302 struct mutex mutex;
4303 struct list_head rtwvifs_list;
4304 /* used to protect rf read write */
4305 struct mutex rf_mutex;
4306 struct workqueue_struct *txq_wq;
4307 struct work_struct txq_work;
4308 struct delayed_work txq_reinvoke_work;
4309 /* used to protect ba_list and forbid_ba_list */
4310 spinlock_t ba_lock;
4311 /* txqs to setup ba session */
4312 struct list_head ba_list;
4313 /* txqs to forbid ba session */
4314 struct list_head forbid_ba_list;
4315 struct work_struct ba_work;
4316 /* used to protect rpwm */
4317 spinlock_t rpwm_lock;
4318
4319 struct rtw89_cam_info cam_info;
4320
4321 struct sk_buff_head c2h_queue;
4322 struct work_struct c2h_work;
4323 struct work_struct ips_work;
4324 struct work_struct load_firmware_work;
4325 struct work_struct cancel_6ghz_probe_work;
4326
4327 struct list_head early_h2c_list;
4328
4329 struct rtw89_ser ser;
4330
4331 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
4332 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
4333 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
4334 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
4335
4336 struct rtw89_phy_stat phystat;
4337 struct rtw89_dack_info dack;
4338 struct rtw89_iqk_info iqk;
4339 struct rtw89_dpk_info dpk;
4340 struct rtw89_rfk_mcc_info rfk_mcc;
4341 struct rtw89_lck_info lck;
4342 struct rtw89_rx_dck_info rx_dck;
4343 bool is_tssi_mode[RF_PATH_MAX];
4344 bool is_bt_iqk_timeout;
4345
4346 struct rtw89_fem_info fem;
4347 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM];
4348 struct rtw89_tssi_info tssi;
4349 struct rtw89_power_trim_info pwr_trim;
4350
4351 struct rtw89_cfo_tracking_info cfo_tracking;
4352 struct rtw89_env_monitor_info env_monitor;
4353 struct rtw89_dig_info dig;
4354 struct rtw89_phy_ch_info ch_info;
4355 struct rtw89_phy_bb_gain_info bb_gain;
4356 struct rtw89_phy_efuse_gain efuse_gain;
4357 struct rtw89_phy_ul_tb_info ul_tb_info;
4358 struct rtw89_antdiv_info antdiv;
4359
4360 struct delayed_work track_work;
4361 struct delayed_work coex_act1_work;
4362 struct delayed_work coex_bt_devinfo_work;
4363 struct delayed_work coex_rfk_chk_work;
4364 struct delayed_work cfo_track_work;
4365 struct delayed_work forbid_ba_work;
4366 struct delayed_work roc_work;
4367 struct delayed_work antdiv_work;
4368 struct rtw89_ppdu_sts_info ppdu_sts;
4369 u8 total_sta_assoc;
4370 bool scanning;
4371
4372 struct rtw89_regulatory_info regulatory;
4373 struct rtw89_sar_info sar;
4374
4375 struct rtw89_btc btc;
4376 enum rtw89_ps_mode ps_mode;
4377 bool lps_enabled;
4378
4379 struct rtw89_wow_param wow;
4380
4381 /* napi structure */
4382 struct net_device netdev;
4383 struct napi_struct napi;
4384 int napi_budget_countdown;
4385
4386 /* HCI related data, keep last */
4387 u8 priv[] __aligned(sizeof(void *));
4388 };
4389
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)4390 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
4391 struct rtw89_core_tx_request *tx_req)
4392 {
4393 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
4394 }
4395
rtw89_hci_reset(struct rtw89_dev * rtwdev)4396 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
4397 {
4398 rtwdev->hci.ops->reset(rtwdev);
4399 }
4400
rtw89_hci_start(struct rtw89_dev * rtwdev)4401 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
4402 {
4403 return rtwdev->hci.ops->start(rtwdev);
4404 }
4405
rtw89_hci_stop(struct rtw89_dev * rtwdev)4406 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
4407 {
4408 rtwdev->hci.ops->stop(rtwdev);
4409 }
4410
rtw89_hci_deinit(struct rtw89_dev * rtwdev)4411 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
4412 {
4413 return rtwdev->hci.ops->deinit(rtwdev);
4414 }
4415
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)4416 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
4417 {
4418 rtwdev->hci.ops->pause(rtwdev, pause);
4419 }
4420
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)4421 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
4422 {
4423 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
4424 }
4425
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)4426 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
4427 {
4428 rtwdev->hci.ops->recalc_int_mit(rtwdev);
4429 }
4430
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)4431 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
4432 {
4433 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
4434 }
4435
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)4436 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
4437 {
4438 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
4439 }
4440
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)4441 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
4442 bool drop)
4443 {
4444 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4445 return;
4446
4447 if (rtwdev->hci.ops->flush_queues)
4448 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
4449 }
4450
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)4451 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
4452 {
4453 if (rtwdev->hci.ops->recovery_start)
4454 rtwdev->hci.ops->recovery_start(rtwdev);
4455 }
4456
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)4457 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
4458 {
4459 if (rtwdev->hci.ops->recovery_complete)
4460 rtwdev->hci.ops->recovery_complete(rtwdev);
4461 }
4462
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)4463 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
4464 {
4465 if (rtwdev->hci.ops->enable_intr)
4466 rtwdev->hci.ops->enable_intr(rtwdev);
4467 }
4468
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)4469 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
4470 {
4471 if (rtwdev->hci.ops->disable_intr)
4472 rtwdev->hci.ops->disable_intr(rtwdev);
4473 }
4474
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)4475 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
4476 {
4477 if (rtwdev->hci.ops->ctrl_txdma_ch)
4478 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
4479 }
4480
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)4481 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
4482 {
4483 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
4484 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
4485 }
4486
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)4487 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
4488 {
4489 if (rtwdev->hci.ops->ctrl_trxhci)
4490 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
4491 }
4492
rtw89_hci_poll_txdma_ch(struct rtw89_dev * rtwdev)4493 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
4494 {
4495 int ret = 0;
4496
4497 if (rtwdev->hci.ops->poll_txdma_ch)
4498 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
4499 return ret;
4500 }
4501
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)4502 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
4503 {
4504 if (rtwdev->hci.ops->clr_idx_all)
4505 rtwdev->hci.ops->clr_idx_all(rtwdev);
4506 }
4507
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)4508 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
4509 {
4510 int ret = 0;
4511
4512 if (rtwdev->hci.ops->rst_bdram)
4513 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
4514 return ret;
4515 }
4516
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)4517 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
4518 {
4519 if (rtwdev->hci.ops->clear)
4520 rtwdev->hci.ops->clear(rtwdev, pdev);
4521 }
4522
4523 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)4524 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
4525 {
4526 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
4527
4528 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
4529 }
4530
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)4531 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
4532 {
4533 return rtwdev->hci.ops->read8(rtwdev, addr);
4534 }
4535
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)4536 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
4537 {
4538 return rtwdev->hci.ops->read16(rtwdev, addr);
4539 }
4540
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)4541 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
4542 {
4543 return rtwdev->hci.ops->read32(rtwdev, addr);
4544 }
4545
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)4546 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
4547 {
4548 rtwdev->hci.ops->write8(rtwdev, addr, data);
4549 }
4550
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)4551 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
4552 {
4553 rtwdev->hci.ops->write16(rtwdev, addr, data);
4554 }
4555
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)4556 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
4557 {
4558 rtwdev->hci.ops->write32(rtwdev, addr, data);
4559 }
4560
4561 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)4562 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4563 {
4564 u8 val;
4565
4566 val = rtw89_read8(rtwdev, addr);
4567 rtw89_write8(rtwdev, addr, val | bit);
4568 }
4569
4570 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)4571 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4572 {
4573 u16 val;
4574
4575 val = rtw89_read16(rtwdev, addr);
4576 rtw89_write16(rtwdev, addr, val | bit);
4577 }
4578
4579 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)4580 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4581 {
4582 u32 val;
4583
4584 val = rtw89_read32(rtwdev, addr);
4585 rtw89_write32(rtwdev, addr, val | bit);
4586 }
4587
4588 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)4589 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
4590 {
4591 u8 val;
4592
4593 val = rtw89_read8(rtwdev, addr);
4594 rtw89_write8(rtwdev, addr, val & ~bit);
4595 }
4596
4597 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)4598 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
4599 {
4600 u16 val;
4601
4602 val = rtw89_read16(rtwdev, addr);
4603 rtw89_write16(rtwdev, addr, val & ~bit);
4604 }
4605
4606 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)4607 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
4608 {
4609 u32 val;
4610
4611 val = rtw89_read32(rtwdev, addr);
4612 rtw89_write32(rtwdev, addr, val & ~bit);
4613 }
4614
4615 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4616 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4617 {
4618 u32 shift = __ffs(mask);
4619 u32 orig;
4620 u32 ret;
4621
4622 orig = rtw89_read32(rtwdev, addr);
4623 ret = (orig & mask) >> shift;
4624
4625 return ret;
4626 }
4627
4628 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4629 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4630 {
4631 u32 shift = __ffs(mask);
4632 u32 orig;
4633 u32 ret;
4634
4635 orig = rtw89_read16(rtwdev, addr);
4636 ret = (orig & mask) >> shift;
4637
4638 return ret;
4639 }
4640
4641 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)4642 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
4643 {
4644 u32 shift = __ffs(mask);
4645 u32 orig;
4646 u32 ret;
4647
4648 orig = rtw89_read8(rtwdev, addr);
4649 ret = (orig & mask) >> shift;
4650
4651 return ret;
4652 }
4653
4654 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)4655 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
4656 {
4657 u32 shift = __ffs(mask);
4658 u32 orig;
4659 u32 set;
4660
4661 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
4662
4663 orig = rtw89_read32(rtwdev, addr);
4664 set = (orig & ~mask) | ((data << shift) & mask);
4665 rtw89_write32(rtwdev, addr, set);
4666 }
4667
4668 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)4669 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
4670 {
4671 u32 shift;
4672 u16 orig, set;
4673
4674 mask &= 0xffff;
4675 shift = __ffs(mask);
4676
4677 orig = rtw89_read16(rtwdev, addr);
4678 set = (orig & ~mask) | ((data << shift) & mask);
4679 rtw89_write16(rtwdev, addr, set);
4680 }
4681
4682 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)4683 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
4684 {
4685 u32 shift;
4686 u8 orig, set;
4687
4688 mask &= 0xff;
4689 shift = __ffs(mask);
4690
4691 orig = rtw89_read8(rtwdev, addr);
4692 set = (orig & ~mask) | ((data << shift) & mask);
4693 rtw89_write8(rtwdev, addr, set);
4694 }
4695
4696 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)4697 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4698 u32 addr, u32 mask)
4699 {
4700 u32 val;
4701
4702 mutex_lock(&rtwdev->rf_mutex);
4703 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
4704 mutex_unlock(&rtwdev->rf_mutex);
4705
4706 return val;
4707 }
4708
4709 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)4710 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
4711 u32 addr, u32 mask, u32 data)
4712 {
4713 mutex_lock(&rtwdev->rf_mutex);
4714 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
4715 mutex_unlock(&rtwdev->rf_mutex);
4716 }
4717
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)4718 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
4719 {
4720 void *p = rtwtxq;
4721
4722 return container_of(p, struct ieee80211_txq, drv_priv);
4723 }
4724
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)4725 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
4726 struct ieee80211_txq *txq)
4727 {
4728 struct rtw89_txq *rtwtxq;
4729
4730 if (!txq)
4731 return;
4732
4733 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4734 INIT_LIST_HEAD(&rtwtxq->list);
4735 }
4736
rtwvif_to_vif(struct rtw89_vif * rtwvif)4737 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
4738 {
4739 void *p = rtwvif;
4740
4741 return container_of(p, struct ieee80211_vif, drv_priv);
4742 }
4743
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)4744 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
4745 {
4746 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
4747 }
4748
vif_to_rtwvif_safe(struct ieee80211_vif * vif)4749 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
4750 {
4751 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
4752 }
4753
rtwsta_to_sta(struct rtw89_sta * rtwsta)4754 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
4755 {
4756 void *p = rtwsta;
4757
4758 return container_of(p, struct ieee80211_sta, drv_priv);
4759 }
4760
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)4761 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
4762 {
4763 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
4764 }
4765
sta_to_rtwsta_safe(struct ieee80211_sta * sta)4766 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
4767 {
4768 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
4769 }
4770
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)4771 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
4772 {
4773 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
4774 return RATE_INFO_BW_160;
4775 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
4776 return RATE_INFO_BW_80;
4777 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
4778 return RATE_INFO_BW_40;
4779 else
4780 return RATE_INFO_BW_20;
4781 }
4782
4783 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)4784 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
4785 {
4786 switch (hw_band) {
4787 default:
4788 case RTW89_BAND_2G:
4789 return NL80211_BAND_2GHZ;
4790 case RTW89_BAND_5G:
4791 return NL80211_BAND_5GHZ;
4792 case RTW89_BAND_6G:
4793 return NL80211_BAND_6GHZ;
4794 }
4795 }
4796
4797 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)4798 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
4799 {
4800 switch (nl_band) {
4801 default:
4802 case NL80211_BAND_2GHZ:
4803 return RTW89_BAND_2G;
4804 case NL80211_BAND_5GHZ:
4805 return RTW89_BAND_5G;
4806 case NL80211_BAND_6GHZ:
4807 return RTW89_BAND_6G;
4808 }
4809 }
4810
4811 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)4812 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
4813 {
4814 switch (width) {
4815 default:
4816 WARN(1, "Not support bandwidth %d\n", width);
4817 fallthrough;
4818 case NL80211_CHAN_WIDTH_20_NOHT:
4819 case NL80211_CHAN_WIDTH_20:
4820 return RTW89_CHANNEL_WIDTH_20;
4821 case NL80211_CHAN_WIDTH_40:
4822 return RTW89_CHANNEL_WIDTH_40;
4823 case NL80211_CHAN_WIDTH_80:
4824 return RTW89_CHANNEL_WIDTH_80;
4825 case NL80211_CHAN_WIDTH_160:
4826 return RTW89_CHANNEL_WIDTH_160;
4827 }
4828 }
4829
4830 static inline
rtw89_get_addr_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4831 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
4832 struct rtw89_sta *rtwsta)
4833 {
4834 if (rtwsta) {
4835 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4836
4837 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
4838 return &rtwsta->addr_cam;
4839 }
4840 return &rtwvif->addr_cam;
4841 }
4842
4843 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4844 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
4845 struct rtw89_sta *rtwsta)
4846 {
4847 if (rtwsta) {
4848 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4849
4850 if (sta->tdls)
4851 return &rtwsta->bssid_cam;
4852 }
4853 return &rtwvif->bssid_cam;
4854 }
4855
4856 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)4857 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
4858 struct rtw89_channel_help_params *p,
4859 const struct rtw89_chan *chan,
4860 enum rtw89_mac_idx mac_idx,
4861 enum rtw89_phy_idx phy_idx)
4862 {
4863 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
4864 mac_idx, phy_idx);
4865 }
4866
4867 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)4868 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
4869 struct rtw89_channel_help_params *p,
4870 const struct rtw89_chan *chan,
4871 enum rtw89_mac_idx mac_idx,
4872 enum rtw89_phy_idx phy_idx)
4873 {
4874 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
4875 mac_idx, phy_idx);
4876 }
4877
4878 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4879 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
4880 enum rtw89_sub_entity_idx idx)
4881 {
4882 struct rtw89_hal *hal = &rtwdev->hal;
4883 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
4884
4885 if (roc_idx == idx)
4886 return &hal->roc_chandef;
4887
4888 return &hal->sub[idx].chandef;
4889 }
4890
4891 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4892 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
4893 enum rtw89_sub_entity_idx idx)
4894 {
4895 struct rtw89_hal *hal = &rtwdev->hal;
4896
4897 return &hal->sub[idx].chan;
4898 }
4899
4900 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_sub_entity_idx idx)4901 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
4902 enum rtw89_sub_entity_idx idx)
4903 {
4904 struct rtw89_hal *hal = &rtwdev->hal;
4905
4906 return &hal->sub[idx].rcd;
4907 }
4908
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)4909 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
4910 {
4911 const struct rtw89_chip_info *chip = rtwdev->chip;
4912
4913 if (chip->ops->fem_setup)
4914 chip->ops->fem_setup(rtwdev);
4915 }
4916
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)4917 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
4918 {
4919 const struct rtw89_chip_info *chip = rtwdev->chip;
4920
4921 if (chip->ops->rfe_gpio)
4922 chip->ops->rfe_gpio(rtwdev);
4923 }
4924
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)4925 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
4926 {
4927 const struct rtw89_chip_info *chip = rtwdev->chip;
4928
4929 if (chip->ops->bb_sethw)
4930 chip->ops->bb_sethw(rtwdev);
4931 }
4932
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)4933 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
4934 {
4935 const struct rtw89_chip_info *chip = rtwdev->chip;
4936
4937 if (chip->ops->rfk_init)
4938 chip->ops->rfk_init(rtwdev);
4939 }
4940
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev)4941 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
4942 {
4943 const struct rtw89_chip_info *chip = rtwdev->chip;
4944
4945 if (chip->ops->rfk_channel)
4946 chip->ops->rfk_channel(rtwdev);
4947 }
4948
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)4949 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
4950 enum rtw89_phy_idx phy_idx)
4951 {
4952 const struct rtw89_chip_info *chip = rtwdev->chip;
4953
4954 if (chip->ops->rfk_band_changed)
4955 chip->ops->rfk_band_changed(rtwdev, phy_idx);
4956 }
4957
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,bool start)4958 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
4959 {
4960 const struct rtw89_chip_info *chip = rtwdev->chip;
4961
4962 if (chip->ops->rfk_scan)
4963 chip->ops->rfk_scan(rtwdev, start);
4964 }
4965
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)4966 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
4967 {
4968 const struct rtw89_chip_info *chip = rtwdev->chip;
4969
4970 if (chip->ops->rfk_track)
4971 chip->ops->rfk_track(rtwdev);
4972 }
4973
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)4974 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
4975 {
4976 const struct rtw89_chip_info *chip = rtwdev->chip;
4977
4978 if (chip->ops->set_txpwr_ctrl)
4979 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
4980 }
4981
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)4982 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
4983 {
4984 const struct rtw89_chip_info *chip = rtwdev->chip;
4985
4986 if (chip->ops->power_trim)
4987 chip->ops->power_trim(rtwdev);
4988 }
4989
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)4990 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
4991 enum rtw89_phy_idx phy_idx)
4992 {
4993 const struct rtw89_chip_info *chip = rtwdev->chip;
4994
4995 if (chip->ops->init_txpwr_unit)
4996 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
4997 }
4998
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)4999 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
5000 enum rtw89_rf_path rf_path)
5001 {
5002 const struct rtw89_chip_info *chip = rtwdev->chip;
5003
5004 if (!chip->ops->get_thermal)
5005 return 0x10;
5006
5007 return chip->ops->get_thermal(rtwdev, rf_path);
5008 }
5009
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)5010 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
5011 struct rtw89_rx_phy_ppdu *phy_ppdu,
5012 struct ieee80211_rx_status *status)
5013 {
5014 const struct rtw89_chip_info *chip = rtwdev->chip;
5015
5016 if (chip->ops->query_ppdu)
5017 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
5018 }
5019
rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)5020 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
5021 bool bt_en)
5022 {
5023 const struct rtw89_chip_info *chip = rtwdev->chip;
5024
5025 if (chip->ops->bb_ctrl_btc_preagc)
5026 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
5027 }
5028
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)5029 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
5030 {
5031 const struct rtw89_chip_info *chip = rtwdev->chip;
5032
5033 if (chip->ops->cfg_txrx_path)
5034 chip->ops->cfg_txrx_path(rtwdev);
5035 }
5036
5037 static inline
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)5038 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5039 struct ieee80211_vif *vif)
5040 {
5041 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5042 const struct rtw89_chip_info *chip = rtwdev->chip;
5043
5044 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
5045 return;
5046
5047 if (chip->ops->set_txpwr_ul_tb_offset)
5048 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
5049 }
5050
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)5051 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
5052 const struct rtw89_txpwr_table *tbl)
5053 {
5054 tbl->load(rtwdev, tbl);
5055 }
5056
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)5057 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
5058 {
5059 const struct rtw89_regd *regd = rtwdev->regulatory.regd;
5060
5061 return regd->txpwr_regd[band];
5062 }
5063
rtw89_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)5064 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
5065 {
5066 const struct rtw89_chip_info *chip = rtwdev->chip;
5067
5068 if (chip->ops->ctrl_btg)
5069 chip->ops->ctrl_btg(rtwdev, btg);
5070 }
5071
5072 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)5073 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
5074 struct rtw89_rx_desc_info *desc_info,
5075 u8 *data, u32 data_offset)
5076 {
5077 const struct rtw89_chip_info *chip = rtwdev->chip;
5078
5079 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
5080 }
5081
5082 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)5083 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
5084 struct rtw89_tx_desc_info *desc_info,
5085 void *txdesc)
5086 {
5087 const struct rtw89_chip_info *chip = rtwdev->chip;
5088
5089 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
5090 }
5091
5092 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)5093 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
5094 struct rtw89_tx_desc_info *desc_info,
5095 void *txdesc)
5096 {
5097 const struct rtw89_chip_info *chip = rtwdev->chip;
5098
5099 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
5100 }
5101
5102 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)5103 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5104 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
5105 {
5106 const struct rtw89_chip_info *chip = rtwdev->chip;
5107
5108 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
5109 }
5110
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)5111 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5112 {
5113 const struct rtw89_chip_info *chip = rtwdev->chip;
5114
5115 chip->ops->cfg_ctrl_path(rtwdev, wl);
5116 }
5117
5118 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)5119 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
5120 u32 *tx_en, enum rtw89_sch_tx_sel sel)
5121 {
5122 const struct rtw89_chip_info *chip = rtwdev->chip;
5123
5124 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
5125 }
5126
5127 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)5128 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
5129 {
5130 const struct rtw89_chip_info *chip = rtwdev->chip;
5131
5132 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
5133 }
5134
5135 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5136 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
5137 struct rtw89_vif *rtwvif,
5138 struct rtw89_sta *rtwsta)
5139 {
5140 const struct rtw89_chip_info *chip = rtwdev->chip;
5141
5142 if (!chip->ops->h2c_dctl_sec_cam)
5143 return 0;
5144 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
5145 }
5146
get_hdr_bssid(struct ieee80211_hdr * hdr)5147 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
5148 {
5149 __le16 fc = hdr->frame_control;
5150
5151 if (ieee80211_has_tods(fc))
5152 return hdr->addr1;
5153 else if (ieee80211_has_fromds(fc))
5154 return hdr->addr2;
5155 else
5156 return hdr->addr3;
5157 }
5158
rtw89_sta_has_beamformer_cap(struct ieee80211_sta * sta)5159 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
5160 {
5161 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
5162 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
5163 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
5164 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
5165 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
5166 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
5167 return true;
5168 return false;
5169 }
5170
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)5171 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
5172 #if defined(__linux__)
5173 enum rtw89_fw_type type)
5174 #elif defined(__FreeBSD__)
5175 const enum rtw89_fw_type type)
5176 #endif
5177 {
5178 struct rtw89_fw_info *fw_info = &rtwdev->fw;
5179
5180 switch (type) {
5181 case RTW89_FW_WOWLAN:
5182 return &fw_info->wowlan;
5183 case RTW89_FW_LOGFMT:
5184 return &fw_info->log.suit;
5185 case RTW89_FW_BBMCU0:
5186 return &fw_info->bbmcu0;
5187 case RTW89_FW_BBMCU1:
5188 return &fw_info->bbmcu1;
5189 default:
5190 break;
5191 }
5192
5193 return &fw_info->normal;
5194 }
5195
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)5196 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
5197 unsigned int length)
5198 {
5199 struct sk_buff *skb;
5200
5201 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
5202 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
5203 if (!skb)
5204 return NULL;
5205
5206 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
5207 return skb;
5208 }
5209
5210 return dev_alloc_skb(length);
5211 }
5212
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,bool tx_done)5213 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
5214 struct rtw89_tx_skb_data *skb_data,
5215 bool tx_done)
5216 {
5217 struct rtw89_tx_wait_info *wait;
5218
5219 rcu_read_lock();
5220
5221 wait = rcu_dereference(skb_data->wait);
5222 if (!wait)
5223 goto out;
5224
5225 wait->tx_done = tx_done;
5226 complete(&wait->completion);
5227
5228 out:
5229 rcu_read_unlock();
5230 }
5231
5232 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5233 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
5234 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
5235 struct sk_buff *skb, bool fwdl);
5236 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
5237 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5238 int qsel, unsigned int timeout);
5239 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
5240 struct rtw89_tx_desc_info *desc_info,
5241 void *txdesc);
5242 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
5243 struct rtw89_tx_desc_info *desc_info,
5244 void *txdesc);
5245 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
5246 struct rtw89_tx_desc_info *desc_info,
5247 void *txdesc);
5248 void rtw89_core_rx(struct rtw89_dev *rtwdev,
5249 struct rtw89_rx_desc_info *desc_info,
5250 struct sk_buff *skb);
5251 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
5252 struct rtw89_rx_desc_info *desc_info,
5253 u8 *data, u32 data_offset);
5254 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
5255 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
5256 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
5257 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
5258 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
5259 struct ieee80211_vif *vif,
5260 struct ieee80211_sta *sta);
5261 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
5262 struct ieee80211_vif *vif,
5263 struct ieee80211_sta *sta);
5264 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
5265 struct ieee80211_vif *vif,
5266 struct ieee80211_sta *sta);
5267 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
5268 struct ieee80211_vif *vif,
5269 struct ieee80211_sta *sta);
5270 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
5271 struct ieee80211_vif *vif,
5272 struct ieee80211_sta *sta);
5273 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5274 struct ieee80211_sta *sta,
5275 struct cfg80211_tid_config *tid_config);
5276 int rtw89_core_init(struct rtw89_dev *rtwdev);
5277 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
5278 int rtw89_core_register(struct rtw89_dev *rtwdev);
5279 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
5280 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5281 u32 bus_data_size,
5282 const struct rtw89_chip_info *chip);
5283 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
5284 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
5285 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
5286 void rtw89_set_channel(struct rtw89_dev *rtwdev);
5287 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5288 struct rtw89_chan *chan);
5289 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
5290 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
5291 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
5292 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
5293 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5294 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
5295 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5296 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
5297 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
5298 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
5299 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
5300 int rtw89_regd_init(struct rtw89_dev *rtwdev,
5301 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
5302 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
5303 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
5304 struct rtw89_traffic_stats *stats);
5305 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
5306 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5307 const struct rtw89_completion_data *data);
5308 int rtw89_core_start(struct rtw89_dev *rtwdev);
5309 void rtw89_core_stop(struct rtw89_dev *rtwdev);
5310 void rtw89_core_update_beacon_work(struct work_struct *work);
5311 void rtw89_roc_work(struct work_struct *work);
5312 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5313 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5314 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5315 const u8 *mac_addr, bool hw_scan);
5316 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
5317 struct ieee80211_vif *vif, bool hw_scan);
5318 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
5319 struct rtw89_vif *rtwvif, bool active);
5320
5321 #if defined(__linux__)
5322 #define rtw89_static_assert(_x) static_assert(_x)
5323 #elif defined(__FreeBSD__)
5324 #define rtw89_static_assert(_x) _Static_assert(_x, "bad array size")
5325 #endif
5326
5327 #endif
5328