1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "real.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "flags.h"
38 #include "recog.h"
39 #include "expr.h"
40 #include "function.h"
41 #include "optabs.h"
42 #include "toplev.h"
43 #include "c-pragma.h"
44 #include "tm_p.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
67 #endif
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
70
71 /* CPU_TYPE, says what cpu we're compiling for. */
72 int cpu_type;
73
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
76
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
79
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
82
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
85
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
88
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
92
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
94
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
96
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
101
102 /* See below where shifts are handled for explanation of this enum. */
103
104 enum shift_alg
105 {
106 SHIFT_INLINE,
107 SHIFT_ROT_AND,
108 SHIFT_SPECIAL,
109 SHIFT_LOOP
110 };
111
112 /* Symbols of the various shifts which can be used as indices. */
113
114 enum shift_type
115 {
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
117 };
118
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
124
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
129
130 static enum shift_alg shift_alg_qi[3][3][8] = {
131 {
132 /* TARGET_H8300 */
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
137 },
138 {
139 /* TARGET_H8300H */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
144 },
145 {
146 /* TARGET_H8300S */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
151 }
152 };
153
154 static enum shift_alg shift_alg_hi[3][3][16] = {
155 {
156 /* TARGET_H8300 */
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
165 },
166 {
167 /* TARGET_H8300H */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
176 },
177 {
178 /* TARGET_H8300S */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
187 }
188 };
189
190 static enum shift_alg shift_alg_si[3][3][32] = {
191 {
192 /* TARGET_H8300 */
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
209 },
210 {
211 /* TARGET_H8300H */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
228 },
229 {
230 /* TARGET_H8300S */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
247 }
248 };
249
250 #undef INL
251 #undef ROT
252 #undef LOP
253 #undef SPC
254
255 enum h8_cpu
256 {
257 H8_300,
258 H8_300H,
259 H8_S
260 };
261
262 /* Initialize various cpu specific globals at start up. */
263
264 void
h8300_init_once(void)265 h8300_init_once (void)
266 {
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
270
271 if (TARGET_H8300)
272 {
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
275 }
276 else
277 {
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
281 }
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
285
286 if (!TARGET_H8300S && TARGET_MAC)
287 {
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
290 }
291
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
293 {
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
296 }
297
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
301 SHIFT_LOOP. */
302 if (optimize_size)
303 {
304 /* H8/300 */
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
309
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
312
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
315
316 /* H8/300H */
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
319
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
322
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
327
328 /* H8S */
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
330 }
331 }
332
333 static const char *
byte_reg(rtx x,int b)334 byte_reg (rtx x, int b)
335 {
336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
339 };
340
341 if (!REG_P (x))
342 abort ();
343
344 return names_small[REGNO (x) * 2 + b];
345 }
346
347 /* REGNO must be saved/restored across calls if this macro is true. */
348
349 #define WORD_REG_USED(regno) \
350 (regno < SP_REG \
351 /* No need to save registers if this function will not return. */ \
352 && ! TREE_THIS_VOLATILE (current_function_decl) \
353 && (h8300_saveall_function_p (current_function_decl) \
354 /* Save any call saved register that was used. */ \
355 || (regs_ever_live[regno] && !call_used_regs[regno]) \
356 /* Save the frame pointer if it was used. */ \
357 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
358 /* Save any register used in an interrupt handler. */ \
359 || (h8300_current_function_interrupt_function_p () \
360 && regs_ever_live[regno]) \
361 /* Save call clobbered registers in non-leaf interrupt \
362 handlers. */ \
363 || (h8300_current_function_interrupt_function_p () \
364 && call_used_regs[regno] \
365 && !current_function_is_leaf)))
366
367 /* Output assembly language to FILE for the operation OP with operand size
368 SIZE to adjust the stack pointer. */
369
370 static void
h8300_emit_stack_adjustment(int sign,unsigned int size)371 h8300_emit_stack_adjustment (int sign, unsigned int size)
372 {
373 /* H8/300 cannot add/subtract a large constant with a single
374 instruction. If a temporary register is available, load the
375 constant to it and then do the addition. */
376 if (TARGET_H8300
377 && size > 4
378 && !h8300_current_function_interrupt_function_p ()
379 && !(current_function_needs_context && sign < 0))
380 {
381 rtx new_sp;
382 rtx r3 = gen_rtx_REG (Pmode, 3);
383 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
384 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
385 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
386 }
387 else
388 {
389 /* The stack adjustment made here is further optimized by the
390 splitter. In case of H8/300, the splitter always splits the
391 addition emitted here to make the adjustment
392 interrupt-safe. */
393 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
394 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
395 }
396 }
397
398 /* Round up frame size SIZE. */
399
400 static int
round_frame_size(int size)401 round_frame_size (int size)
402 {
403 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
404 & -STACK_BOUNDARY / BITS_PER_UNIT);
405 }
406
407 /* Compute which registers to push/pop.
408 Return a bit vector of registers. */
409
410 static unsigned int
compute_saved_regs(void)411 compute_saved_regs (void)
412 {
413 unsigned int saved_regs = 0;
414 int regno;
415
416 /* Construct a bit vector of registers to be pushed/popped. */
417 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
418 {
419 if (WORD_REG_USED (regno))
420 saved_regs |= 1 << regno;
421 }
422
423 /* Don't push/pop the frame pointer as it is treated separately. */
424 if (frame_pointer_needed)
425 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
426
427 return saved_regs;
428 }
429
430 /* Emit an insn to push register RN. */
431
432 static void
push(int rn)433 push (int rn)
434 {
435 rtx reg = gen_rtx_REG (word_mode, rn);
436 rtx x;
437
438 if (TARGET_H8300)
439 x = gen_push_h8300 (reg);
440 else if (!TARGET_NORMAL_MODE)
441 x = gen_push_h8300hs_advanced (reg);
442 else
443 x = gen_push_h8300hs_normal (reg);
444 x = emit_insn (x);
445 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
446 }
447
448 /* Emit an insn to pop register RN. */
449
450 static void
pop(int rn)451 pop (int rn)
452 {
453 rtx reg = gen_rtx_REG (word_mode, rn);
454 rtx x;
455
456 if (TARGET_H8300)
457 x = gen_pop_h8300 (reg);
458 else if (!TARGET_NORMAL_MODE)
459 x = gen_pop_h8300hs_advanced (reg);
460 else
461 x = gen_pop_h8300hs_normal (reg);
462 x = emit_insn (x);
463 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
464 }
465
466 /* This is what the stack looks like after the prolog of
467 a function with a frame has been set up:
468
469 <args>
470 PC
471 FP <- fp
472 <locals>
473 <saved registers> <- sp
474
475 This is what the stack looks like after the prolog of
476 a function which doesn't have a frame:
477
478 <args>
479 PC
480 <locals>
481 <saved registers> <- sp
482 */
483
484 /* Generate RTL code for the function prologue. */
485
486 void
h8300_expand_prologue(void)487 h8300_expand_prologue (void)
488 {
489 int regno;
490 int saved_regs;
491 int n_regs;
492
493 /* If the current function has the OS_Task attribute set, then
494 we have a naked prologue. */
495 if (h8300_os_task_function_p (current_function_decl))
496 return;
497
498 if (h8300_monitor_function_p (current_function_decl))
499 /* My understanding of monitor functions is they act just like
500 interrupt functions, except the prologue must mask
501 interrupts. */
502 emit_insn (gen_monitor_prologue ());
503
504 if (frame_pointer_needed)
505 {
506 /* Push fp. */
507 push (FRAME_POINTER_REGNUM);
508 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
509 }
510
511 /* Leave room for locals. */
512 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
513
514 /* Push the rest of the registers in ascending order. */
515 saved_regs = compute_saved_regs ();
516 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
517 {
518 n_regs = 1;
519 if (saved_regs & (1 << regno))
520 {
521 if (TARGET_H8300S)
522 {
523 /* See how many registers we can push at the same time. */
524 if ((regno == 0 || regno == 4)
525 && ((saved_regs >> regno) & 0x0f) == 0x0f)
526 n_regs = 4;
527
528 else if ((regno == 0 || regno == 4)
529 && ((saved_regs >> regno) & 0x07) == 0x07)
530 n_regs = 3;
531
532 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
533 && ((saved_regs >> regno) & 0x03) == 0x03)
534 n_regs = 2;
535 }
536
537 switch (n_regs)
538 {
539 case 1:
540 push (regno);
541 break;
542 case 2:
543 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
544 gen_rtx_REG (SImode, regno + 1)));
545 break;
546 case 3:
547 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
548 gen_rtx_REG (SImode, regno + 1),
549 gen_rtx_REG (SImode, regno + 2)));
550 break;
551 case 4:
552 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
553 gen_rtx_REG (SImode, regno + 1),
554 gen_rtx_REG (SImode, regno + 2),
555 gen_rtx_REG (SImode, regno + 3)));
556 break;
557 default:
558 abort ();
559 }
560 }
561 }
562 }
563
564 int
h8300_can_use_return_insn_p(void)565 h8300_can_use_return_insn_p (void)
566 {
567 return (reload_completed
568 && !frame_pointer_needed
569 && get_frame_size () == 0
570 && compute_saved_regs () == 0);
571 }
572
573 /* Generate RTL code for the function epilogue. */
574
575 void
h8300_expand_epilogue(void)576 h8300_expand_epilogue (void)
577 {
578 int regno;
579 int saved_regs;
580 int n_regs;
581
582 if (h8300_os_task_function_p (current_function_decl))
583 /* OS_Task epilogues are nearly naked -- they just have an
584 rts instruction. */
585 return;
586
587 /* Pop the saved registers in descending order. */
588 saved_regs = compute_saved_regs ();
589 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
590 {
591 n_regs = 1;
592 if (saved_regs & (1 << regno))
593 {
594 if (TARGET_H8300S)
595 {
596 /* See how many registers we can pop at the same time. */
597 if ((regno == 7 || regno == 3)
598 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
599 n_regs = 4;
600
601 else if ((regno == 6 || regno == 2)
602 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
603 n_regs = 3;
604
605 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
606 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
607 n_regs = 2;
608 }
609
610 switch (n_regs)
611 {
612 case 1:
613 pop (regno);
614 break;
615 case 2:
616 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
617 gen_rtx_REG (SImode, regno)));
618 break;
619 case 3:
620 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
621 gen_rtx_REG (SImode, regno - 1),
622 gen_rtx_REG (SImode, regno)));
623 break;
624 case 4:
625 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
626 gen_rtx_REG (SImode, regno - 2),
627 gen_rtx_REG (SImode, regno - 1),
628 gen_rtx_REG (SImode, regno)));
629 break;
630 default:
631 abort ();
632 }
633 }
634 }
635
636 /* Deallocate locals. */
637 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
638
639 /* Pop frame pointer if we had one. */
640 if (frame_pointer_needed)
641 pop (FRAME_POINTER_REGNUM);
642 }
643
644 /* Return nonzero if the current function is an interrupt
645 function. */
646
647 int
h8300_current_function_interrupt_function_p(void)648 h8300_current_function_interrupt_function_p (void)
649 {
650 return (h8300_interrupt_function_p (current_function_decl)
651 || h8300_monitor_function_p (current_function_decl));
652 }
653
654 /* Output assembly code for the start of the file. */
655
656 static void
h8300_file_start(void)657 h8300_file_start (void)
658 {
659 default_file_start ();
660
661 if (TARGET_H8300H)
662 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
663 else if (TARGET_H8300S)
664 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
665 }
666
667 /* Output assembly language code for the end of file. */
668
669 static void
h8300_file_end(void)670 h8300_file_end (void)
671 {
672 fputs ("\t.end\n", asm_out_file);
673 }
674
675 /* Return true if OP is a valid source operand for an integer move
676 instruction. */
677
678 int
general_operand_src(rtx op,enum machine_mode mode)679 general_operand_src (rtx op, enum machine_mode mode)
680 {
681 if (GET_MODE (op) == mode
682 && GET_CODE (op) == MEM
683 && GET_CODE (XEXP (op, 0)) == POST_INC)
684 return 1;
685 return general_operand (op, mode);
686 }
687
688 /* Return true if OP is a valid destination operand for an integer move
689 instruction. */
690
691 int
general_operand_dst(rtx op,enum machine_mode mode)692 general_operand_dst (rtx op, enum machine_mode mode)
693 {
694 if (GET_MODE (op) == mode
695 && GET_CODE (op) == MEM
696 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
697 return 1;
698 return general_operand (op, mode);
699 }
700
701 /* Return true if OP is a constant that contains only one 1 in its
702 binary representation. */
703
704 int
single_one_operand(rtx operand,enum machine_mode mode ATTRIBUTE_UNUSED)705 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
706 {
707 if (GET_CODE (operand) == CONST_INT)
708 {
709 /* We really need to do this masking because 0x80 in QImode is
710 represented as -128 for example. */
711 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
712 return 1;
713 }
714
715 return 0;
716 }
717
718 /* Return true if OP is a constant that contains only one 0 in its
719 binary representation. */
720
721 int
single_zero_operand(rtx operand,enum machine_mode mode ATTRIBUTE_UNUSED)722 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
723 {
724 if (GET_CODE (operand) == CONST_INT)
725 {
726 /* We really need to do this masking because 0x80 in QImode is
727 represented as -128 for example. */
728 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
729 return 1;
730 }
731
732 return 0;
733 }
734
735 /* Return true if OP is a valid call operand. */
736
737 int
call_insn_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)738 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
739 {
740 if (GET_CODE (op) == MEM)
741 {
742 rtx inside = XEXP (op, 0);
743 if (register_operand (inside, Pmode))
744 return 1;
745 if (CONSTANT_ADDRESS_P (inside))
746 return 1;
747 }
748 return 0;
749 }
750
751 /* Return 1 if an addition/subtraction of a constant integer can be
752 transformed into two consecutive adds/subs that are faster than the
753 straightforward way. Otherwise, return 0. */
754
755 int
two_insn_adds_subs_operand(rtx op,enum machine_mode mode)756 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
757 {
758 if (GET_CODE (op) == CONST_INT)
759 {
760 HOST_WIDE_INT value = INTVAL (op);
761
762 /* Force VALUE to be positive so that we do not have to consider
763 the negative case. */
764 if (value < 0)
765 value = -value;
766 if (TARGET_H8300H || TARGET_H8300S)
767 {
768 /* A constant addition/subtraction takes 2 states in QImode,
769 4 states in HImode, and 6 states in SImode. Thus, the
770 only case we can win is when SImode is used, in which
771 case, two adds/subs are used, taking 4 states. */
772 if (mode == SImode
773 && (value == 2 + 1
774 || value == 4 + 1
775 || value == 4 + 2
776 || value == 4 + 4))
777 return 1;
778 }
779 else
780 {
781 /* We do not profit directly by splitting addition or
782 subtraction of 3 and 4. However, since these are
783 implemented as a sequence of adds or subs, they do not
784 clobber (cc0) unlike a sequence of add.b and add.x. */
785 if (mode == HImode
786 && (value == 2 + 1
787 || value == 2 + 2))
788 return 1;
789 }
790 }
791
792 return 0;
793 }
794
795 /* Split an add of a small constant into two adds/subs insns.
796
797 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
798 instead of adds/subs. */
799
800 void
split_adds_subs(enum machine_mode mode,rtx * operands)801 split_adds_subs (enum machine_mode mode, rtx *operands)
802 {
803 HOST_WIDE_INT val = INTVAL (operands[1]);
804 rtx reg = operands[0];
805 HOST_WIDE_INT sign = 1;
806 HOST_WIDE_INT amount;
807 rtx (*gen_add) (rtx, rtx, rtx);
808
809 /* Force VAL to be positive so that we do not have to consider the
810 sign. */
811 if (val < 0)
812 {
813 val = -val;
814 sign = -1;
815 }
816
817 switch (mode)
818 {
819 case HImode:
820 gen_add = gen_addhi3;
821 break;
822
823 case SImode:
824 gen_add = gen_addsi3;
825 break;
826
827 default:
828 abort ();
829 }
830
831 /* Try different amounts in descending order. */
832 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
833 amount > 0;
834 amount /= 2)
835 {
836 for (; val >= amount; val -= amount)
837 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
838 }
839
840 return;
841 }
842
843 /* Return true if OP is a valid call operand, and OP represents
844 an operand for a small call (4 bytes instead of 6 bytes). */
845
846 int
small_call_insn_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)847 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
848 {
849 if (GET_CODE (op) == MEM)
850 {
851 rtx inside = XEXP (op, 0);
852
853 /* Register indirect is a small call. */
854 if (register_operand (inside, Pmode))
855 return 1;
856
857 /* A call through the function vector is a small call too. */
858 if (GET_CODE (inside) == SYMBOL_REF
859 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
860 return 1;
861 }
862 /* Otherwise it's a large call. */
863 return 0;
864 }
865
866 /* Return true if OP is a valid jump operand. */
867
868 int
jump_address_operand(rtx op,enum machine_mode mode)869 jump_address_operand (rtx op, enum machine_mode mode)
870 {
871 if (GET_CODE (op) == REG)
872 return mode == Pmode;
873
874 if (GET_CODE (op) == MEM)
875 {
876 rtx inside = XEXP (op, 0);
877 if (register_operand (inside, Pmode))
878 return 1;
879 if (CONSTANT_ADDRESS_P (inside))
880 return 1;
881 }
882 return 0;
883 }
884
885 /* Recognize valid operands for bit-field instructions. */
886
887 extern int rtx_equal_function_value_matters;
888
889 int
bit_operand(rtx op,enum machine_mode mode)890 bit_operand (rtx op, enum machine_mode mode)
891 {
892 /* We can accept any general operand, except that MEM operands must
893 be limited to those that use addresses valid for the 'U' constraint. */
894 if (!general_operand (op, mode))
895 return 0;
896
897 /* Accept any mem during RTL generation. Otherwise, the code that does
898 insv and extzv will think that we can not handle memory. However,
899 to avoid reload problems, we only accept 'U' MEM operands after RTL
900 generation. This means that any named pattern which uses this predicate
901 must force its operands to match 'U' before emitting RTL. */
902
903 if (GET_CODE (op) == REG)
904 return 1;
905 if (GET_CODE (op) == SUBREG)
906 return 1;
907 return (GET_CODE (op) == MEM
908 && EXTRA_CONSTRAINT (op, 'U'));
909 }
910
911 int
bit_memory_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)912 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
913 {
914 return (GET_CODE (op) == MEM
915 && EXTRA_CONSTRAINT (op, 'U'));
916 }
917
918 /* Handle machine specific pragmas for compatibility with existing
919 compilers for the H8/300.
920
921 pragma saveall generates prologue/epilogue code which saves and
922 restores all the registers on function entry.
923
924 pragma interrupt saves and restores all registers, and exits with
925 an rte instruction rather than an rts. A pointer to a function
926 with this attribute may be safely used in an interrupt vector. */
927
928 void
h8300_pr_interrupt(struct cpp_reader * pfile ATTRIBUTE_UNUSED)929 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
930 {
931 pragma_interrupt = 1;
932 }
933
934 void
h8300_pr_saveall(struct cpp_reader * pfile ATTRIBUTE_UNUSED)935 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
936 {
937 pragma_saveall = 1;
938 }
939
940 /* If the next function argument with MODE and TYPE is to be passed in
941 a register, return a reg RTX for the hard register in which to pass
942 the argument. CUM represents the state after the last argument.
943 If the argument is to be pushed, NULL_RTX is returned. */
944
945 rtx
function_arg(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)946 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
947 tree type, int named)
948 {
949 static const char *const hand_list[] = {
950 "__main",
951 "__cmpsi2",
952 "__divhi3",
953 "__modhi3",
954 "__udivhi3",
955 "__umodhi3",
956 "__divsi3",
957 "__modsi3",
958 "__udivsi3",
959 "__umodsi3",
960 "__mulhi3",
961 "__mulsi3",
962 "__reg_memcpy",
963 "__reg_memset",
964 "__ucmpsi2",
965 0,
966 };
967
968 rtx result = NULL_RTX;
969 const char *fname;
970 int regpass = 0;
971
972 /* Never pass unnamed arguments in registers. */
973 if (!named)
974 return NULL_RTX;
975
976 /* Pass 3 regs worth of data in regs when user asked on the command line. */
977 if (TARGET_QUICKCALL)
978 regpass = 3;
979
980 /* If calling hand written assembler, use 4 regs of args. */
981 if (cum->libcall)
982 {
983 const char * const *p;
984
985 fname = XSTR (cum->libcall, 0);
986
987 /* See if this libcall is one of the hand coded ones. */
988 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
989 ;
990
991 if (*p)
992 regpass = 4;
993 }
994
995 if (regpass)
996 {
997 int size;
998
999 if (mode == BLKmode)
1000 size = int_size_in_bytes (type);
1001 else
1002 size = GET_MODE_SIZE (mode);
1003
1004 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1005 && cum->nbytes / UNITS_PER_WORD <= 3)
1006 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1007 }
1008
1009 return result;
1010 }
1011
1012 static int
h8300_and_costs(rtx x)1013 h8300_and_costs (rtx x)
1014 {
1015 rtx operands[4];
1016
1017 if (GET_MODE (x) == QImode)
1018 return 1;
1019
1020 if (GET_MODE (x) != HImode
1021 && GET_MODE (x) != SImode)
1022 return 100;
1023
1024 operands[0] = NULL;
1025 operands[1] = NULL;
1026 operands[2] = XEXP (x, 1);
1027 operands[3] = x;
1028 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1029 }
1030
1031 static int
h8300_shift_costs(rtx x)1032 h8300_shift_costs (rtx x)
1033 {
1034 rtx operands[4];
1035
1036 if (GET_MODE (x) != QImode
1037 && GET_MODE (x) != HImode
1038 && GET_MODE (x) != SImode)
1039 return 100;
1040
1041 operands[0] = NULL;
1042 operands[1] = NULL;
1043 operands[2] = XEXP (x, 1);
1044 operands[3] = x;
1045 return compute_a_shift_length (NULL, operands) / 2;
1046 }
1047
1048 static bool
h8300_rtx_costs(rtx x,int code,int outer_code,int * total)1049 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1050 {
1051 switch (code)
1052 {
1053 case CONST_INT:
1054 {
1055 HOST_WIDE_INT n = INTVAL (x);
1056
1057 if (-4 <= n || n <= 4)
1058 {
1059 switch ((int) n)
1060 {
1061 case 0:
1062 *total = 0;
1063 return true;
1064 case 1:
1065 case 2:
1066 case -1:
1067 case -2:
1068 *total = 0 + (outer_code == SET);
1069 return true;
1070 case 4:
1071 case -4:
1072 if (TARGET_H8300H || TARGET_H8300S)
1073 *total = 0 + (outer_code == SET);
1074 else
1075 *total = 1;
1076 return true;
1077 }
1078 }
1079 *total = 1;
1080 return true;
1081 }
1082
1083 case CONST:
1084 case LABEL_REF:
1085 case SYMBOL_REF:
1086 *total = 3;
1087 return true;
1088
1089 case CONST_DOUBLE:
1090 *total = 20;
1091 return true;
1092
1093 case AND:
1094 *total = COSTS_N_INSNS (h8300_and_costs (x));
1095 return true;
1096
1097 /* We say that MOD and DIV are so expensive because otherwise we'll
1098 generate some really horrible code for division of a power of two. */
1099 case MOD:
1100 case DIV:
1101 *total = 60;
1102 return true;
1103
1104 case MULT:
1105 *total = 20;
1106 return true;
1107
1108 case ASHIFT:
1109 case ASHIFTRT:
1110 case LSHIFTRT:
1111 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1112 return true;
1113
1114 case ROTATE:
1115 case ROTATERT:
1116 if (GET_MODE (x) == HImode)
1117 *total = 2;
1118 else
1119 *total = 8;
1120 return true;
1121
1122 default:
1123 *total = 4;
1124 return true;
1125 }
1126 }
1127
1128 /* Documentation for the machine specific operand escapes:
1129
1130 'E' like s but negative.
1131 'F' like t but negative.
1132 'G' constant just the negative
1133 'R' print operand as a byte:8 address if appropriate, else fall back to
1134 'X' handling.
1135 'S' print operand as a long word
1136 'T' print operand as a word
1137 'V' find the set bit, and print its number.
1138 'W' find the clear bit, and print its number.
1139 'X' print operand as a byte
1140 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1141 If this operand isn't a register, fall back to 'R' handling.
1142 'Z' print int & 7.
1143 'c' print the opcode corresponding to rtl
1144 'e' first word of 32 bit value - if reg, then least reg. if mem
1145 then least. if const then most sig word
1146 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1147 then +2. if const then least sig word
1148 'j' print operand as condition code.
1149 'k' print operand as reverse condition code.
1150 's' print as low byte of 16 bit value
1151 't' print as high byte of 16 bit value
1152 'w' print as low byte of 32 bit value
1153 'x' print as 2nd byte of 32 bit value
1154 'y' print as 3rd byte of 32 bit value
1155 'z' print as msb of 32 bit value
1156 */
1157
1158 /* Return assembly language string which identifies a comparison type. */
1159
1160 static const char *
cond_string(enum rtx_code code)1161 cond_string (enum rtx_code code)
1162 {
1163 switch (code)
1164 {
1165 case NE:
1166 return "ne";
1167 case EQ:
1168 return "eq";
1169 case GE:
1170 return "ge";
1171 case GT:
1172 return "gt";
1173 case LE:
1174 return "le";
1175 case LT:
1176 return "lt";
1177 case GEU:
1178 return "hs";
1179 case GTU:
1180 return "hi";
1181 case LEU:
1182 return "ls";
1183 case LTU:
1184 return "lo";
1185 default:
1186 abort ();
1187 }
1188 }
1189
1190 /* Print operand X using operand code CODE to assembly language output file
1191 FILE. */
1192
1193 void
print_operand(FILE * file,rtx x,int code)1194 print_operand (FILE *file, rtx x, int code)
1195 {
1196 /* This is used for communication between codes V,W,Z and Y. */
1197 static int bitint;
1198
1199 switch (code)
1200 {
1201 case 'E':
1202 switch (GET_CODE (x))
1203 {
1204 case REG:
1205 fprintf (file, "%sl", names_big[REGNO (x)]);
1206 break;
1207 case CONST_INT:
1208 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1209 break;
1210 default:
1211 abort ();
1212 }
1213 break;
1214 case 'F':
1215 switch (GET_CODE (x))
1216 {
1217 case REG:
1218 fprintf (file, "%sh", names_big[REGNO (x)]);
1219 break;
1220 case CONST_INT:
1221 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1222 break;
1223 default:
1224 abort ();
1225 }
1226 break;
1227 case 'G':
1228 if (GET_CODE (x) != CONST_INT)
1229 abort ();
1230 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1231 break;
1232 case 'S':
1233 if (GET_CODE (x) == REG)
1234 fprintf (file, "%s", names_extended[REGNO (x)]);
1235 else
1236 goto def;
1237 break;
1238 case 'T':
1239 if (GET_CODE (x) == REG)
1240 fprintf (file, "%s", names_big[REGNO (x)]);
1241 else
1242 goto def;
1243 break;
1244 case 'V':
1245 bitint = exact_log2 (INTVAL (x) & 0xff);
1246 if (bitint == -1)
1247 abort ();
1248 fprintf (file, "#%d", bitint);
1249 break;
1250 case 'W':
1251 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1252 if (bitint == -1)
1253 abort ();
1254 fprintf (file, "#%d", bitint);
1255 break;
1256 case 'R':
1257 case 'X':
1258 if (GET_CODE (x) == REG)
1259 fprintf (file, "%s", byte_reg (x, 0));
1260 else
1261 goto def;
1262 break;
1263 case 'Y':
1264 if (bitint == -1)
1265 abort ();
1266 if (GET_CODE (x) == REG)
1267 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1268 else
1269 print_operand (file, x, 'R');
1270 bitint = -1;
1271 break;
1272 case 'Z':
1273 bitint = INTVAL (x);
1274 fprintf (file, "#%d", bitint & 7);
1275 break;
1276 case 'c':
1277 switch (GET_CODE (x))
1278 {
1279 case IOR:
1280 fprintf (file, "or");
1281 break;
1282 case XOR:
1283 fprintf (file, "xor");
1284 break;
1285 case AND:
1286 fprintf (file, "and");
1287 break;
1288 default:
1289 break;
1290 }
1291 break;
1292 case 'e':
1293 switch (GET_CODE (x))
1294 {
1295 case REG:
1296 if (TARGET_H8300)
1297 fprintf (file, "%s", names_big[REGNO (x)]);
1298 else
1299 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1300 break;
1301 case MEM:
1302 print_operand (file, x, 0);
1303 break;
1304 case CONST_INT:
1305 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1306 break;
1307 case CONST_DOUBLE:
1308 {
1309 long val;
1310 REAL_VALUE_TYPE rv;
1311 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1312 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1313 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1314 break;
1315 }
1316 default:
1317 abort ();
1318 break;
1319 }
1320 break;
1321 case 'f':
1322 switch (GET_CODE (x))
1323 {
1324 case REG:
1325 if (TARGET_H8300)
1326 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1327 else
1328 fprintf (file, "%s", names_big[REGNO (x)]);
1329 break;
1330 case MEM:
1331 x = adjust_address (x, HImode, 2);
1332 print_operand (file, x, 0);
1333 break;
1334 case CONST_INT:
1335 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1336 break;
1337 case CONST_DOUBLE:
1338 {
1339 long val;
1340 REAL_VALUE_TYPE rv;
1341 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1342 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1343 fprintf (file, "#%ld", (val & 0xffff));
1344 break;
1345 }
1346 default:
1347 abort ();
1348 }
1349 break;
1350 case 'j':
1351 fputs (cond_string (GET_CODE (x)), file);
1352 break;
1353 case 'k':
1354 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1355 break;
1356 case 's':
1357 if (GET_CODE (x) == CONST_INT)
1358 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1359 else
1360 fprintf (file, "%s", byte_reg (x, 0));
1361 break;
1362 case 't':
1363 if (GET_CODE (x) == CONST_INT)
1364 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1365 else
1366 fprintf (file, "%s", byte_reg (x, 1));
1367 break;
1368 case 'w':
1369 if (GET_CODE (x) == CONST_INT)
1370 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1371 else
1372 fprintf (file, "%s",
1373 byte_reg (x, TARGET_H8300 ? 2 : 0));
1374 break;
1375 case 'x':
1376 if (GET_CODE (x) == CONST_INT)
1377 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1378 else
1379 fprintf (file, "%s",
1380 byte_reg (x, TARGET_H8300 ? 3 : 1));
1381 break;
1382 case 'y':
1383 if (GET_CODE (x) == CONST_INT)
1384 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1385 else
1386 fprintf (file, "%s", byte_reg (x, 0));
1387 break;
1388 case 'z':
1389 if (GET_CODE (x) == CONST_INT)
1390 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1391 else
1392 fprintf (file, "%s", byte_reg (x, 1));
1393 break;
1394
1395 default:
1396 def:
1397 switch (GET_CODE (x))
1398 {
1399 case REG:
1400 switch (GET_MODE (x))
1401 {
1402 case QImode:
1403 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1404 fprintf (file, "%s", byte_reg (x, 0));
1405 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1406 fprintf (file, "%s", names_big[REGNO (x)]);
1407 #endif
1408 break;
1409 case HImode:
1410 fprintf (file, "%s", names_big[REGNO (x)]);
1411 break;
1412 case SImode:
1413 case SFmode:
1414 fprintf (file, "%s", names_extended[REGNO (x)]);
1415 break;
1416 default:
1417 abort ();
1418 }
1419 break;
1420
1421 case MEM:
1422 {
1423 rtx addr = XEXP (x, 0);
1424
1425 fprintf (file, "@");
1426 output_address (addr);
1427
1428 /* We fall back from smaller addressing to larger
1429 addressing in various ways depending on CODE. */
1430 switch (code)
1431 {
1432 case 'R':
1433 /* Used for mov.b and bit operations. */
1434 if (h8300_eightbit_constant_address_p (addr))
1435 {
1436 fprintf (file, ":8");
1437 break;
1438 }
1439
1440 /* Fall through. We should not get here if we are
1441 processing bit operations on H8/300 or H8/300H
1442 because 'U' constraint does not allow bit
1443 operations on the tiny area on these machines. */
1444
1445 case 'T':
1446 case 'S':
1447 /* Used for mov.w and mov.l. */
1448 if (h8300_tiny_constant_address_p (addr))
1449 fprintf (file, ":16");
1450 break;
1451 default:
1452 break;
1453 }
1454 }
1455 break;
1456
1457 case CONST_INT:
1458 case SYMBOL_REF:
1459 case CONST:
1460 case LABEL_REF:
1461 fprintf (file, "#");
1462 print_operand_address (file, x);
1463 break;
1464 case CONST_DOUBLE:
1465 {
1466 long val;
1467 REAL_VALUE_TYPE rv;
1468 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1469 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1470 fprintf (file, "#%ld", val);
1471 break;
1472 }
1473 default:
1474 break;
1475 }
1476 }
1477 }
1478
1479 /* Output assembly language output for the address ADDR to FILE. */
1480
1481 void
print_operand_address(FILE * file,rtx addr)1482 print_operand_address (FILE *file, rtx addr)
1483 {
1484 switch (GET_CODE (addr))
1485 {
1486 case REG:
1487 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1488 break;
1489
1490 case PRE_DEC:
1491 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1492 break;
1493
1494 case POST_INC:
1495 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1496 break;
1497
1498 case PLUS:
1499 fprintf (file, "(");
1500 if (GET_CODE (XEXP (addr, 0)) == REG)
1501 {
1502 /* reg,foo */
1503 print_operand_address (file, XEXP (addr, 1));
1504 fprintf (file, ",");
1505 print_operand_address (file, XEXP (addr, 0));
1506 }
1507 else
1508 {
1509 /* foo+k */
1510 print_operand_address (file, XEXP (addr, 0));
1511 fprintf (file, "+");
1512 print_operand_address (file, XEXP (addr, 1));
1513 }
1514 fprintf (file, ")");
1515 break;
1516
1517 case CONST_INT:
1518 {
1519 /* Since the H8/300 only has 16 bit pointers, negative values are also
1520 those >= 32768. This happens for example with pointer minus a
1521 constant. We don't want to turn (char *p - 2) into
1522 (char *p + 65534) because loop unrolling can build upon this
1523 (IE: char *p + 131068). */
1524 int n = INTVAL (addr);
1525 if (TARGET_H8300)
1526 n = (int) (short) n;
1527 fprintf (file, "%d", n);
1528 break;
1529 }
1530
1531 default:
1532 output_addr_const (file, addr);
1533 break;
1534 }
1535 }
1536
1537 /* Output all insn addresses and their sizes into the assembly language
1538 output file. This is helpful for debugging whether the length attributes
1539 in the md file are correct. This is not meant to be a user selectable
1540 option. */
1541
1542 void
final_prescan_insn(rtx insn,rtx * operand ATTRIBUTE_UNUSED,int num_operands ATTRIBUTE_UNUSED)1543 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1544 int num_operands ATTRIBUTE_UNUSED)
1545 {
1546 /* This holds the last insn address. */
1547 static int last_insn_address = 0;
1548
1549 const int uid = INSN_UID (insn);
1550
1551 if (TARGET_ADDRESSES)
1552 {
1553 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1554 INSN_ADDRESSES (uid) - last_insn_address);
1555 last_insn_address = INSN_ADDRESSES (uid);
1556 }
1557 }
1558
1559 /* Prepare for an SI sized move. */
1560
1561 int
h8300_expand_movsi(rtx operands[])1562 h8300_expand_movsi (rtx operands[])
1563 {
1564 rtx src = operands[1];
1565 rtx dst = operands[0];
1566 if (!reload_in_progress && !reload_completed)
1567 {
1568 if (!register_operand (dst, GET_MODE (dst)))
1569 {
1570 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1571 emit_move_insn (tmp, src);
1572 operands[1] = tmp;
1573 }
1574 }
1575 return 0;
1576 }
1577
1578 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1579 Define the offset between two registers, one to be eliminated, and
1580 the other its replacement, at the start of a routine. */
1581
1582 int
h8300_initial_elimination_offset(int from,int to)1583 h8300_initial_elimination_offset (int from, int to)
1584 {
1585 int offset = 0;
1586 /* The number of bytes that the return address takes on the stack. */
1587 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1588
1589 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1590 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1591 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1592 offset = frame_pointer_needed * UNITS_PER_WORD;
1593 else
1594 {
1595 int regno;
1596
1597 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1598 if (WORD_REG_USED (regno))
1599 offset += UNITS_PER_WORD;
1600
1601 /* See the comments for get_frame_size. We need to round it up to
1602 STACK_BOUNDARY. */
1603
1604 offset += round_frame_size (get_frame_size ());
1605
1606 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1607 /* Skip saved PC. */
1608 offset += pc_size;
1609 }
1610
1611 return offset;
1612 }
1613
1614 rtx
h8300_return_addr_rtx(int count,rtx frame)1615 h8300_return_addr_rtx (int count, rtx frame)
1616 {
1617 rtx ret;
1618
1619 if (count == 0)
1620 ret = gen_rtx_MEM (Pmode,
1621 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1622 else if (flag_omit_frame_pointer)
1623 return (rtx) 0;
1624 else
1625 ret = gen_rtx_MEM (Pmode,
1626 memory_address (Pmode,
1627 plus_constant (frame, UNITS_PER_WORD)));
1628 set_mem_alias_set (ret, get_frame_alias_set ());
1629 return ret;
1630 }
1631
1632 /* Update the condition code from the insn. */
1633
1634 void
notice_update_cc(rtx body,rtx insn)1635 notice_update_cc (rtx body, rtx insn)
1636 {
1637 rtx set;
1638
1639 switch (get_attr_cc (insn))
1640 {
1641 case CC_NONE:
1642 /* Insn does not affect CC at all. */
1643 break;
1644
1645 case CC_NONE_0HIT:
1646 /* Insn does not change CC, but the 0'th operand has been changed. */
1647 if (cc_status.value1 != 0
1648 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1649 cc_status.value1 = 0;
1650 if (cc_status.value2 != 0
1651 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1652 cc_status.value2 = 0;
1653 break;
1654
1655 case CC_SET_ZN:
1656 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1657 The V flag is unusable. The C flag may or may not be known but
1658 that's ok because alter_cond will change tests to use EQ/NE. */
1659 CC_STATUS_INIT;
1660 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1661 set = single_set (insn);
1662 cc_status.value1 = SET_SRC (set);
1663 if (SET_DEST (set) != cc0_rtx)
1664 cc_status.value2 = SET_DEST (set);
1665 break;
1666
1667 case CC_SET_ZNV:
1668 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1669 The C flag may or may not be known but that's ok because
1670 alter_cond will change tests to use EQ/NE. */
1671 CC_STATUS_INIT;
1672 cc_status.flags |= CC_NO_CARRY;
1673 set = single_set (insn);
1674 cc_status.value1 = SET_SRC (set);
1675 if (SET_DEST (set) != cc0_rtx)
1676 {
1677 /* If the destination is STRICT_LOW_PART, strip off
1678 STRICT_LOW_PART. */
1679 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1680 cc_status.value2 = XEXP (SET_DEST (set), 0);
1681 else
1682 cc_status.value2 = SET_DEST (set);
1683 }
1684 break;
1685
1686 case CC_COMPARE:
1687 /* The insn is a compare instruction. */
1688 CC_STATUS_INIT;
1689 cc_status.value1 = SET_SRC (body);
1690 break;
1691
1692 case CC_CLOBBER:
1693 /* Insn doesn't leave CC in a usable state. */
1694 CC_STATUS_INIT;
1695 break;
1696 }
1697 }
1698
1699 /* Return nonzero if X is a stack pointer. */
1700
1701 int
stack_pointer_operand(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1702 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1703 {
1704 return x == stack_pointer_rtx;
1705 }
1706
1707 /* Return nonzero if X is a constant whose absolute value is greater
1708 than 2. */
1709
1710 int
const_int_gt_2_operand(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1711 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1712 {
1713 return (GET_CODE (x) == CONST_INT
1714 && abs (INTVAL (x)) > 2);
1715 }
1716
1717 /* Return nonzero if X is a constant whose absolute value is no
1718 smaller than 8. */
1719
1720 int
const_int_ge_8_operand(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1721 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1722 {
1723 return (GET_CODE (x) == CONST_INT
1724 && abs (INTVAL (x)) >= 8);
1725 }
1726
1727 /* Return nonzero if X is a constant expressible in QImode. */
1728
1729 int
const_int_qi_operand(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1730 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1731 {
1732 return (GET_CODE (x) == CONST_INT
1733 && (INTVAL (x) & 0xff) == INTVAL (x));
1734 }
1735
1736 /* Return nonzero if X is a constant expressible in HImode. */
1737
1738 int
const_int_hi_operand(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1739 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1740 {
1741 return (GET_CODE (x) == CONST_INT
1742 && (INTVAL (x) & 0xffff) == INTVAL (x));
1743 }
1744
1745 /* Return nonzero if X is a constant suitable for inc/dec. */
1746
1747 int
incdec_operand(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1748 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1749 {
1750 return (GET_CODE (x) == CONST_INT
1751 && (CONST_OK_FOR_M (INTVAL (x))
1752 || CONST_OK_FOR_O (INTVAL (x))));
1753 }
1754
1755 /* Return nonzero if X is either EQ or NE. */
1756
1757 int
eqne_operator(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1758 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1759 {
1760 enum rtx_code code = GET_CODE (x);
1761
1762 return (code == EQ || code == NE);
1763 }
1764
1765 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1766
1767 int
gtle_operator(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1768 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1769 {
1770 enum rtx_code code = GET_CODE (x);
1771
1772 return (code == GT || code == LE || code == GTU || code == LEU);
1773 }
1774
1775 /* Return nonzero if X is either GTU or LEU. */
1776
1777 int
gtuleu_operator(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1778 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1779 {
1780 enum rtx_code code = GET_CODE (x);
1781
1782 return (code == GTU || code == LEU);
1783 }
1784
1785 /* Return nonzero if X is either IOR or XOR. */
1786
1787 int
iorxor_operator(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1788 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1789 {
1790 enum rtx_code code = GET_CODE (x);
1791
1792 return (code == IOR || code == XOR);
1793 }
1794
1795 /* Recognize valid operators for bit instructions. */
1796
1797 int
bit_operator(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)1798 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1799 {
1800 enum rtx_code code = GET_CODE (x);
1801
1802 return (code == XOR
1803 || code == AND
1804 || code == IOR);
1805 }
1806
1807 /* Return the length of mov instruction. */
1808
1809 unsigned int
compute_mov_length(rtx * operands)1810 compute_mov_length (rtx *operands)
1811 {
1812 /* If the mov instruction involves a memory operand, we compute the
1813 length, assuming the largest addressing mode is used, and then
1814 adjust later in the function. Otherwise, we compute and return
1815 the exact length in one step. */
1816 enum machine_mode mode = GET_MODE (operands[0]);
1817 rtx dest = operands[0];
1818 rtx src = operands[1];
1819 rtx addr;
1820
1821 if (GET_CODE (src) == MEM)
1822 addr = XEXP (src, 0);
1823 else if (GET_CODE (dest) == MEM)
1824 addr = XEXP (dest, 0);
1825 else
1826 addr = NULL_RTX;
1827
1828 if (TARGET_H8300)
1829 {
1830 unsigned int base_length;
1831
1832 switch (mode)
1833 {
1834 case QImode:
1835 if (addr == NULL_RTX)
1836 return 2;
1837
1838 /* The eightbit addressing is available only in QImode, so
1839 go ahead and take care of it. */
1840 if (h8300_eightbit_constant_address_p (addr))
1841 return 2;
1842
1843 base_length = 4;
1844 break;
1845
1846 case HImode:
1847 if (addr == NULL_RTX)
1848 {
1849 if (REG_P (src))
1850 return 2;
1851
1852 if (src == const0_rtx)
1853 return 2;
1854
1855 return 4;
1856 }
1857
1858 base_length = 4;
1859 break;
1860
1861 case SImode:
1862 if (addr == NULL_RTX)
1863 {
1864 if (REG_P (src))
1865 return 4;
1866
1867 if (GET_CODE (src) == CONST_INT)
1868 {
1869 if (src == const0_rtx)
1870 return 4;
1871
1872 if ((INTVAL (src) & 0xffff) == 0)
1873 return 6;
1874
1875 if ((INTVAL (src) & 0xffff) == 0)
1876 return 6;
1877
1878 if ((INTVAL (src) & 0xffff)
1879 == ((INTVAL (src) >> 16) & 0xffff))
1880 return 6;
1881 }
1882 return 8;
1883 }
1884
1885 base_length = 8;
1886 break;
1887
1888 case SFmode:
1889 if (addr == NULL_RTX)
1890 {
1891 if (REG_P (src))
1892 return 4;
1893
1894 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1895 return 4;
1896
1897 return 8;
1898 }
1899
1900 base_length = 8;
1901 break;
1902
1903 default:
1904 abort ();
1905 }
1906
1907 /* Adjust the length based on the addressing mode used.
1908 Specifically, we subtract the difference between the actual
1909 length and the longest one, which is @(d:16,Rs). For SImode
1910 and SFmode, we double the adjustment because two mov.w are
1911 used to do the job. */
1912
1913 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1914 if (GET_CODE (addr) == PRE_DEC
1915 || GET_CODE (addr) == POST_INC)
1916 {
1917 if (mode == QImode || mode == HImode)
1918 return base_length - 2;
1919 else
1920 /* In SImode and SFmode, we use two mov.w instructions, so
1921 double the adjustment. */
1922 return base_length - 4;
1923 }
1924
1925 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1926 in SImode and SFmode, the second mov.w involves an address
1927 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1928 only 2 bytes. */
1929 if (GET_CODE (addr) == REG)
1930 return base_length - 2;
1931
1932 return base_length;
1933 }
1934 else
1935 {
1936 unsigned int base_length;
1937
1938 switch (mode)
1939 {
1940 case QImode:
1941 if (addr == NULL_RTX)
1942 return 2;
1943
1944 /* The eightbit addressing is available only in QImode, so
1945 go ahead and take care of it. */
1946 if (h8300_eightbit_constant_address_p (addr))
1947 return 2;
1948
1949 base_length = 8;
1950 break;
1951
1952 case HImode:
1953 if (addr == NULL_RTX)
1954 {
1955 if (REG_P (src))
1956 return 2;
1957
1958 if (src == const0_rtx)
1959 return 2;
1960
1961 return 4;
1962 }
1963
1964 base_length = 8;
1965 break;
1966
1967 case SImode:
1968 if (addr == NULL_RTX)
1969 {
1970 if (REG_P (src))
1971 {
1972 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
1973 return 4;
1974 else
1975 return 2;
1976 }
1977
1978 if (GET_CODE (src) == CONST_INT)
1979 {
1980 int val = INTVAL (src);
1981
1982 if (val == 0)
1983 return 2;
1984
1985 if (val == (val & 0x00ff) || val == (val & 0xff00))
1986 return 4;
1987
1988 switch (val & 0xffffffff)
1989 {
1990 case 0xffffffff:
1991 case 0xfffffffe:
1992 case 0xfffffffc:
1993 case 0x0000ffff:
1994 case 0x0000fffe:
1995 case 0xffff0000:
1996 case 0xfffe0000:
1997 case 0x00010000:
1998 case 0x00020000:
1999 return 4;
2000 }
2001 }
2002 return 6;
2003 }
2004
2005 base_length = 10;
2006 break;
2007
2008 case SFmode:
2009 if (addr == NULL_RTX)
2010 {
2011 if (REG_P (src))
2012 return 2;
2013
2014 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2015 return 2;
2016
2017 return 6;
2018 }
2019
2020 base_length = 10;
2021 break;
2022
2023 default:
2024 abort ();
2025 }
2026
2027 /* Adjust the length based on the addressing mode used.
2028 Specifically, we subtract the difference between the actual
2029 length and the longest one, which is @(d:24,ERs). */
2030
2031 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2032 if (GET_CODE (addr) == PRE_DEC
2033 || GET_CODE (addr) == POST_INC)
2034 return base_length - 6;
2035
2036 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2037 if (GET_CODE (addr) == REG)
2038 return base_length - 6;
2039
2040 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2041 longest. */
2042 if (GET_CODE (addr) == PLUS
2043 && GET_CODE (XEXP (addr, 0)) == REG
2044 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2045 && INTVAL (XEXP (addr, 1)) > -32768
2046 && INTVAL (XEXP (addr, 1)) < 32767)
2047 return base_length - 4;
2048
2049 /* @aa:16 is 4 bytes shorter than the longest. */
2050 if (h8300_tiny_constant_address_p (addr))
2051 return base_length - 4;
2052
2053 /* @aa:24 is 2 bytes shorter than the longest. */
2054 if (CONSTANT_P (addr))
2055 return base_length - 2;
2056
2057 return base_length;
2058 }
2059 }
2060
2061 const char *
output_plussi(rtx * operands)2062 output_plussi (rtx *operands)
2063 {
2064 enum machine_mode mode = GET_MODE (operands[0]);
2065
2066 if (mode != SImode)
2067 abort ();
2068
2069 if (TARGET_H8300)
2070 {
2071 if (GET_CODE (operands[2]) == REG)
2072 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2073
2074 if (GET_CODE (operands[2]) == CONST_INT)
2075 {
2076 HOST_WIDE_INT n = INTVAL (operands[2]);
2077
2078 if ((n & 0xffffff) == 0)
2079 return "add\t%z2,%z0";
2080 if ((n & 0xffff) == 0)
2081 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2082 if ((n & 0xff) == 0)
2083 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2084 }
2085
2086 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2087 }
2088 else
2089 {
2090 if (GET_CODE (operands[2]) == REG)
2091 return "add.l\t%S2,%S0";
2092
2093 if (GET_CODE (operands[2]) == CONST_INT)
2094 {
2095 HOST_WIDE_INT intval = INTVAL (operands[2]);
2096
2097 /* See if we can finish with 2 bytes. */
2098
2099 switch ((unsigned int) intval & 0xffffffff)
2100 {
2101 case 0x00000001:
2102 case 0x00000002:
2103 case 0x00000004:
2104 return "adds\t%2,%S0";
2105
2106 case 0xffffffff:
2107 case 0xfffffffe:
2108 case 0xfffffffc:
2109 return "subs\t%G2,%S0";
2110
2111 case 0x00010000:
2112 case 0x00020000:
2113 operands[2] = GEN_INT (intval >> 16);
2114 return "inc.w\t%2,%e0";
2115
2116 case 0xffff0000:
2117 case 0xfffe0000:
2118 operands[2] = GEN_INT (intval >> 16);
2119 return "dec.w\t%G2,%e0";
2120 }
2121
2122 /* See if we can finish with 4 bytes. */
2123 if ((intval & 0xffff) == 0)
2124 {
2125 operands[2] = GEN_INT (intval >> 16);
2126 return "add.w\t%2,%e0";
2127 }
2128 }
2129
2130 return "add.l\t%S2,%S0";
2131 }
2132 }
2133
2134 unsigned int
compute_plussi_length(rtx * operands)2135 compute_plussi_length (rtx *operands)
2136 {
2137 enum machine_mode mode = GET_MODE (operands[0]);
2138
2139 if (mode != SImode)
2140 abort ();
2141
2142 if (TARGET_H8300)
2143 {
2144 if (GET_CODE (operands[2]) == REG)
2145 return 6;
2146
2147 if (GET_CODE (operands[2]) == CONST_INT)
2148 {
2149 HOST_WIDE_INT n = INTVAL (operands[2]);
2150
2151 if ((n & 0xffffff) == 0)
2152 return 2;
2153 if ((n & 0xffff) == 0)
2154 return 4;
2155 if ((n & 0xff) == 0)
2156 return 6;
2157 }
2158
2159 return 8;
2160 }
2161 else
2162 {
2163 if (GET_CODE (operands[2]) == REG)
2164 return 2;
2165
2166 if (GET_CODE (operands[2]) == CONST_INT)
2167 {
2168 HOST_WIDE_INT intval = INTVAL (operands[2]);
2169
2170 /* See if we can finish with 2 bytes. */
2171
2172 switch ((unsigned int) intval & 0xffffffff)
2173 {
2174 case 0x00000001:
2175 case 0x00000002:
2176 case 0x00000004:
2177 return 2;
2178
2179 case 0xffffffff:
2180 case 0xfffffffe:
2181 case 0xfffffffc:
2182 return 2;
2183
2184 case 0x00010000:
2185 case 0x00020000:
2186 return 2;
2187
2188 case 0xffff0000:
2189 case 0xfffe0000:
2190 return 2;
2191 }
2192
2193 /* See if we can finish with 4 bytes. */
2194 if ((intval & 0xffff) == 0)
2195 return 4;
2196 }
2197
2198 return 6;
2199 }
2200 }
2201
2202 int
compute_plussi_cc(rtx * operands)2203 compute_plussi_cc (rtx *operands)
2204 {
2205 enum machine_mode mode = GET_MODE (operands[0]);
2206
2207 if (mode != SImode)
2208 abort ();
2209
2210 if (TARGET_H8300)
2211 {
2212 return CC_CLOBBER;
2213 }
2214 else
2215 {
2216 if (GET_CODE (operands[2]) == REG)
2217 return CC_SET_ZN;
2218
2219 if (GET_CODE (operands[2]) == CONST_INT)
2220 {
2221 HOST_WIDE_INT intval = INTVAL (operands[2]);
2222
2223 /* See if we can finish with 2 bytes. */
2224
2225 switch ((unsigned int) intval & 0xffffffff)
2226 {
2227 case 0x00000001:
2228 case 0x00000002:
2229 case 0x00000004:
2230 return CC_NONE_0HIT;
2231
2232 case 0xffffffff:
2233 case 0xfffffffe:
2234 case 0xfffffffc:
2235 return CC_NONE_0HIT;
2236
2237 case 0x00010000:
2238 case 0x00020000:
2239 return CC_CLOBBER;
2240
2241 case 0xffff0000:
2242 case 0xfffe0000:
2243 return CC_CLOBBER;
2244 }
2245
2246 /* See if we can finish with 4 bytes. */
2247 if ((intval & 0xffff) == 0)
2248 return CC_CLOBBER;
2249 }
2250
2251 return CC_SET_ZN;
2252 }
2253 }
2254
2255 const char *
output_logical_op(enum machine_mode mode,rtx * operands)2256 output_logical_op (enum machine_mode mode, rtx *operands)
2257 {
2258 /* Figure out the logical op that we need to perform. */
2259 enum rtx_code code = GET_CODE (operands[3]);
2260 /* Pretend that every byte is affected if both operands are registers. */
2261 const unsigned HOST_WIDE_INT intval =
2262 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2263 ? INTVAL (operands[2]) : 0x55555555);
2264 /* The determinant of the algorithm. If we perform an AND, 0
2265 affects a bit. Otherwise, 1 affects a bit. */
2266 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2267 /* Break up DET into pieces. */
2268 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2269 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2270 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2271 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2272 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2273 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2274 int lower_half_easy_p = 0;
2275 int upper_half_easy_p = 0;
2276 /* The name of an insn. */
2277 const char *opname;
2278 char insn_buf[100];
2279
2280 switch (code)
2281 {
2282 case AND:
2283 opname = "and";
2284 break;
2285 case IOR:
2286 opname = "or";
2287 break;
2288 case XOR:
2289 opname = "xor";
2290 break;
2291 default:
2292 abort ();
2293 }
2294
2295 switch (mode)
2296 {
2297 case HImode:
2298 /* First, see if we can finish with one insn. */
2299 if ((TARGET_H8300H || TARGET_H8300S)
2300 && b0 != 0
2301 && b1 != 0)
2302 {
2303 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2304 output_asm_insn (insn_buf, operands);
2305 }
2306 else
2307 {
2308 /* Take care of the lower byte. */
2309 if (b0 != 0)
2310 {
2311 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2312 output_asm_insn (insn_buf, operands);
2313 }
2314 /* Take care of the upper byte. */
2315 if (b1 != 0)
2316 {
2317 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2318 output_asm_insn (insn_buf, operands);
2319 }
2320 }
2321 break;
2322 case SImode:
2323 if (TARGET_H8300H || TARGET_H8300S)
2324 {
2325 /* Determine if the lower half can be taken care of in no more
2326 than two bytes. */
2327 lower_half_easy_p = (b0 == 0
2328 || b1 == 0
2329 || (code != IOR && w0 == 0xffff));
2330
2331 /* Determine if the upper half can be taken care of in no more
2332 than two bytes. */
2333 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2334 || (code == AND && w1 == 0xff00));
2335 }
2336
2337 /* Check if doing everything with one insn is no worse than
2338 using multiple insns. */
2339 if ((TARGET_H8300H || TARGET_H8300S)
2340 && w0 != 0 && w1 != 0
2341 && !(lower_half_easy_p && upper_half_easy_p)
2342 && !(code == IOR && w1 == 0xffff
2343 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2344 {
2345 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2346 output_asm_insn (insn_buf, operands);
2347 }
2348 else
2349 {
2350 /* Take care of the lower and upper words individually. For
2351 each word, we try different methods in the order of
2352
2353 1) the special insn (in case of AND or XOR),
2354 2) the word-wise insn, and
2355 3) The byte-wise insn. */
2356 if (w0 == 0xffff
2357 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2358 output_asm_insn ((code == AND)
2359 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2360 operands);
2361 else if ((TARGET_H8300H || TARGET_H8300S)
2362 && (b0 != 0)
2363 && (b1 != 0))
2364 {
2365 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2366 output_asm_insn (insn_buf, operands);
2367 }
2368 else
2369 {
2370 if (b0 != 0)
2371 {
2372 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2373 output_asm_insn (insn_buf, operands);
2374 }
2375 if (b1 != 0)
2376 {
2377 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2378 output_asm_insn (insn_buf, operands);
2379 }
2380 }
2381
2382 if ((w1 == 0xffff)
2383 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2384 output_asm_insn ((code == AND)
2385 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2386 operands);
2387 else if ((TARGET_H8300H || TARGET_H8300S)
2388 && code == IOR
2389 && w1 == 0xffff
2390 && (w0 & 0x8000) != 0)
2391 {
2392 output_asm_insn ("exts.l\t%S0", operands);
2393 }
2394 else if ((TARGET_H8300H || TARGET_H8300S)
2395 && code == AND
2396 && w1 == 0xff00)
2397 {
2398 output_asm_insn ("extu.w\t%e0", operands);
2399 }
2400 else if (TARGET_H8300H || TARGET_H8300S)
2401 {
2402 if (w1 != 0)
2403 {
2404 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2405 output_asm_insn (insn_buf, operands);
2406 }
2407 }
2408 else
2409 {
2410 if (b2 != 0)
2411 {
2412 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2413 output_asm_insn (insn_buf, operands);
2414 }
2415 if (b3 != 0)
2416 {
2417 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2418 output_asm_insn (insn_buf, operands);
2419 }
2420 }
2421 }
2422 break;
2423 default:
2424 abort ();
2425 }
2426 return "";
2427 }
2428
2429 unsigned int
compute_logical_op_length(enum machine_mode mode,rtx * operands)2430 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2431 {
2432 /* Figure out the logical op that we need to perform. */
2433 enum rtx_code code = GET_CODE (operands[3]);
2434 /* Pretend that every byte is affected if both operands are registers. */
2435 const unsigned HOST_WIDE_INT intval =
2436 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2437 ? INTVAL (operands[2]) : 0x55555555);
2438 /* The determinant of the algorithm. If we perform an AND, 0
2439 affects a bit. Otherwise, 1 affects a bit. */
2440 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2441 /* Break up DET into pieces. */
2442 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2443 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2444 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2445 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2446 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2447 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2448 int lower_half_easy_p = 0;
2449 int upper_half_easy_p = 0;
2450 /* Insn length. */
2451 unsigned int length = 0;
2452
2453 switch (mode)
2454 {
2455 case HImode:
2456 /* First, see if we can finish with one insn. */
2457 if ((TARGET_H8300H || TARGET_H8300S)
2458 && b0 != 0
2459 && b1 != 0)
2460 {
2461 if (REG_P (operands[2]))
2462 length += 2;
2463 else
2464 length += 4;
2465 }
2466 else
2467 {
2468 /* Take care of the lower byte. */
2469 if (b0 != 0)
2470 length += 2;
2471
2472 /* Take care of the upper byte. */
2473 if (b1 != 0)
2474 length += 2;
2475 }
2476 break;
2477 case SImode:
2478 if (TARGET_H8300H || TARGET_H8300S)
2479 {
2480 /* Determine if the lower half can be taken care of in no more
2481 than two bytes. */
2482 lower_half_easy_p = (b0 == 0
2483 || b1 == 0
2484 || (code != IOR && w0 == 0xffff));
2485
2486 /* Determine if the upper half can be taken care of in no more
2487 than two bytes. */
2488 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2489 || (code == AND && w1 == 0xff00));
2490 }
2491
2492 /* Check if doing everything with one insn is no worse than
2493 using multiple insns. */
2494 if ((TARGET_H8300H || TARGET_H8300S)
2495 && w0 != 0 && w1 != 0
2496 && !(lower_half_easy_p && upper_half_easy_p)
2497 && !(code == IOR && w1 == 0xffff
2498 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2499 {
2500 if (REG_P (operands[2]))
2501 length += 4;
2502 else
2503 length += 6;
2504 }
2505 else
2506 {
2507 /* Take care of the lower and upper words individually. For
2508 each word, we try different methods in the order of
2509
2510 1) the special insn (in case of AND or XOR),
2511 2) the word-wise insn, and
2512 3) The byte-wise insn. */
2513 if (w0 == 0xffff
2514 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2515 {
2516 length += 2;
2517 }
2518 else if ((TARGET_H8300H || TARGET_H8300S)
2519 && (b0 != 0)
2520 && (b1 != 0))
2521 {
2522 length += 4;
2523 }
2524 else
2525 {
2526 if (b0 != 0)
2527 length += 2;
2528
2529 if (b1 != 0)
2530 length += 2;
2531 }
2532
2533 if (w1 == 0xffff
2534 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2535 {
2536 length += 2;
2537 }
2538 else if ((TARGET_H8300H || TARGET_H8300S)
2539 && code == IOR
2540 && w1 == 0xffff
2541 && (w0 & 0x8000) != 0)
2542 {
2543 length += 2;
2544 }
2545 else if ((TARGET_H8300H || TARGET_H8300S)
2546 && code == AND
2547 && w1 == 0xff00)
2548 {
2549 length += 2;
2550 }
2551 else if (TARGET_H8300H || TARGET_H8300S)
2552 {
2553 if (w1 != 0)
2554 length += 4;
2555 }
2556 else
2557 {
2558 if (b2 != 0)
2559 length += 2;
2560
2561 if (b3 != 0)
2562 length += 2;
2563 }
2564 }
2565 break;
2566 default:
2567 abort ();
2568 }
2569 return length;
2570 }
2571
2572 int
compute_logical_op_cc(enum machine_mode mode,rtx * operands)2573 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2574 {
2575 /* Figure out the logical op that we need to perform. */
2576 enum rtx_code code = GET_CODE (operands[3]);
2577 /* Pretend that every byte is affected if both operands are registers. */
2578 const unsigned HOST_WIDE_INT intval =
2579 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2580 ? INTVAL (operands[2]) : 0x55555555);
2581 /* The determinant of the algorithm. If we perform an AND, 0
2582 affects a bit. Otherwise, 1 affects a bit. */
2583 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2584 /* Break up DET into pieces. */
2585 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2586 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2587 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2588 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2589 int lower_half_easy_p = 0;
2590 int upper_half_easy_p = 0;
2591 /* Condition code. */
2592 enum attr_cc cc = CC_CLOBBER;
2593
2594 switch (mode)
2595 {
2596 case HImode:
2597 /* First, see if we can finish with one insn. */
2598 if ((TARGET_H8300H || TARGET_H8300S)
2599 && b0 != 0
2600 && b1 != 0)
2601 {
2602 cc = CC_SET_ZNV;
2603 }
2604 break;
2605 case SImode:
2606 if (TARGET_H8300H || TARGET_H8300S)
2607 {
2608 /* Determine if the lower half can be taken care of in no more
2609 than two bytes. */
2610 lower_half_easy_p = (b0 == 0
2611 || b1 == 0
2612 || (code != IOR && w0 == 0xffff));
2613
2614 /* Determine if the upper half can be taken care of in no more
2615 than two bytes. */
2616 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2617 || (code == AND && w1 == 0xff00));
2618 }
2619
2620 /* Check if doing everything with one insn is no worse than
2621 using multiple insns. */
2622 if ((TARGET_H8300H || TARGET_H8300S)
2623 && w0 != 0 && w1 != 0
2624 && !(lower_half_easy_p && upper_half_easy_p)
2625 && !(code == IOR && w1 == 0xffff
2626 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2627 {
2628 cc = CC_SET_ZNV;
2629 }
2630 else
2631 {
2632 if ((TARGET_H8300H || TARGET_H8300S)
2633 && code == IOR
2634 && w1 == 0xffff
2635 && (w0 & 0x8000) != 0)
2636 {
2637 cc = CC_SET_ZNV;
2638 }
2639 }
2640 break;
2641 default:
2642 abort ();
2643 }
2644 return cc;
2645 }
2646
2647 /* Shifts.
2648
2649 We devote a fair bit of code to getting efficient shifts since we
2650 can only shift one bit at a time on the H8/300 and H8/300H and only
2651 one or two bits at a time on the H8S.
2652
2653 All shift code falls into one of the following ways of
2654 implementation:
2655
2656 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2657 when a straight line shift is about the same size or smaller than
2658 a loop.
2659
2660 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2661 off the bits we don't need. This is used when only a few of the
2662 bits in the original value will survive in the shifted value.
2663
2664 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2665 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2666 shifts can be added if the shift count is slightly more than 8 or
2667 16. This case also includes other oddballs that are not worth
2668 explaining here.
2669
2670 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2671
2672 For each shift count, we try to use code that has no trade-off
2673 between code size and speed whenever possible.
2674
2675 If the trade-off is unavoidable, we try to be reasonable.
2676 Specifically, the fastest version is one instruction longer than
2677 the shortest version, we take the fastest version. We also provide
2678 the use a way to switch back to the shortest version with -Os.
2679
2680 For the details of the shift algorithms for various shift counts,
2681 refer to shift_alg_[qhs]i. */
2682
2683 int
nshift_operator(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED)2684 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2685 {
2686 switch (GET_CODE (x))
2687 {
2688 case ASHIFTRT:
2689 case LSHIFTRT:
2690 case ASHIFT:
2691 return 1;
2692
2693 default:
2694 return 0;
2695 }
2696 }
2697
2698 /* Emit code to do shifts. */
2699
2700 void
expand_a_shift(enum machine_mode mode,int code,rtx operands[])2701 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2702 {
2703 emit_move_insn (operands[0], operands[1]);
2704
2705 /* Need a loop to get all the bits we want - we generate the
2706 code at emit time, but need to allocate a scratch reg now. */
2707
2708 emit_insn (gen_rtx_PARALLEL
2709 (VOIDmode,
2710 gen_rtvec (2,
2711 gen_rtx_SET (VOIDmode, operands[0],
2712 gen_rtx (code, mode, operands[0],
2713 operands[2])),
2714 gen_rtx_CLOBBER (VOIDmode,
2715 gen_rtx_SCRATCH (QImode)))));
2716 }
2717
2718 /* Symbols of the various modes which can be used as indices. */
2719
2720 enum shift_mode
2721 {
2722 QIshift, HIshift, SIshift
2723 };
2724
2725 /* For single bit shift insns, record assembler and what bits of the
2726 condition code are valid afterwards (represented as various CC_FOO
2727 bits, 0 means CC isn't left in a usable state). */
2728
2729 struct shift_insn
2730 {
2731 const char *const assembler;
2732 const int cc_valid;
2733 };
2734
2735 /* Assembler instruction shift table.
2736
2737 These tables are used to look up the basic shifts.
2738 They are indexed by cpu, shift_type, and mode. */
2739
2740 static const struct shift_insn shift_one[2][3][3] =
2741 {
2742 /* H8/300 */
2743 {
2744 /* SHIFT_ASHIFT */
2745 {
2746 { "shll\t%X0", CC_SET_ZNV },
2747 { "add.w\t%T0,%T0", CC_SET_ZN },
2748 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2749 },
2750 /* SHIFT_LSHIFTRT */
2751 {
2752 { "shlr\t%X0", CC_SET_ZNV },
2753 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2754 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2755 },
2756 /* SHIFT_ASHIFTRT */
2757 {
2758 { "shar\t%X0", CC_SET_ZNV },
2759 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2760 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2761 }
2762 },
2763 /* H8/300H */
2764 {
2765 /* SHIFT_ASHIFT */
2766 {
2767 { "shll.b\t%X0", CC_SET_ZNV },
2768 { "shll.w\t%T0", CC_SET_ZNV },
2769 { "shll.l\t%S0", CC_SET_ZNV }
2770 },
2771 /* SHIFT_LSHIFTRT */
2772 {
2773 { "shlr.b\t%X0", CC_SET_ZNV },
2774 { "shlr.w\t%T0", CC_SET_ZNV },
2775 { "shlr.l\t%S0", CC_SET_ZNV }
2776 },
2777 /* SHIFT_ASHIFTRT */
2778 {
2779 { "shar.b\t%X0", CC_SET_ZNV },
2780 { "shar.w\t%T0", CC_SET_ZNV },
2781 { "shar.l\t%S0", CC_SET_ZNV }
2782 }
2783 }
2784 };
2785
2786 static const struct shift_insn shift_two[3][3] =
2787 {
2788 /* SHIFT_ASHIFT */
2789 {
2790 { "shll.b\t#2,%X0", CC_SET_ZNV },
2791 { "shll.w\t#2,%T0", CC_SET_ZNV },
2792 { "shll.l\t#2,%S0", CC_SET_ZNV }
2793 },
2794 /* SHIFT_LSHIFTRT */
2795 {
2796 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2797 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2798 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2799 },
2800 /* SHIFT_ASHIFTRT */
2801 {
2802 { "shar.b\t#2,%X0", CC_SET_ZNV },
2803 { "shar.w\t#2,%T0", CC_SET_ZNV },
2804 { "shar.l\t#2,%S0", CC_SET_ZNV }
2805 }
2806 };
2807
2808 /* Rotates are organized by which shift they'll be used in implementing.
2809 There's no need to record whether the cc is valid afterwards because
2810 it is the AND insn that will decide this. */
2811
2812 static const char *const rotate_one[2][3][3] =
2813 {
2814 /* H8/300 */
2815 {
2816 /* SHIFT_ASHIFT */
2817 {
2818 "rotr\t%X0",
2819 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2820 0
2821 },
2822 /* SHIFT_LSHIFTRT */
2823 {
2824 "rotl\t%X0",
2825 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2826 0
2827 },
2828 /* SHIFT_ASHIFTRT */
2829 {
2830 "rotl\t%X0",
2831 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2832 0
2833 }
2834 },
2835 /* H8/300H */
2836 {
2837 /* SHIFT_ASHIFT */
2838 {
2839 "rotr.b\t%X0",
2840 "rotr.w\t%T0",
2841 "rotr.l\t%S0"
2842 },
2843 /* SHIFT_LSHIFTRT */
2844 {
2845 "rotl.b\t%X0",
2846 "rotl.w\t%T0",
2847 "rotl.l\t%S0"
2848 },
2849 /* SHIFT_ASHIFTRT */
2850 {
2851 "rotl.b\t%X0",
2852 "rotl.w\t%T0",
2853 "rotl.l\t%S0"
2854 }
2855 }
2856 };
2857
2858 static const char *const rotate_two[3][3] =
2859 {
2860 /* SHIFT_ASHIFT */
2861 {
2862 "rotr.b\t#2,%X0",
2863 "rotr.w\t#2,%T0",
2864 "rotr.l\t#2,%S0"
2865 },
2866 /* SHIFT_LSHIFTRT */
2867 {
2868 "rotl.b\t#2,%X0",
2869 "rotl.w\t#2,%T0",
2870 "rotl.l\t#2,%S0"
2871 },
2872 /* SHIFT_ASHIFTRT */
2873 {
2874 "rotl.b\t#2,%X0",
2875 "rotl.w\t#2,%T0",
2876 "rotl.l\t#2,%S0"
2877 }
2878 };
2879
2880 struct shift_info {
2881 /* Shift algorithm. */
2882 enum shift_alg alg;
2883
2884 /* The number of bits to be shifted by shift1 and shift2. Valid
2885 when ALG is SHIFT_SPECIAL. */
2886 unsigned int remainder;
2887
2888 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2889 const char *special;
2890
2891 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2892 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2893 const char *shift1;
2894
2895 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2896 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2897 const char *shift2;
2898
2899 /* CC status for SHIFT_INLINE. */
2900 int cc_inline;
2901
2902 /* CC status for SHIFT_SPECIAL. */
2903 int cc_special;
2904 };
2905
2906 static void get_shift_alg (enum shift_type,
2907 enum shift_mode, unsigned int,
2908 struct shift_info *);
2909
2910 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2911 best algorithm for doing the shift. The assembler code is stored
2912 in the pointers in INFO. We achieve the maximum efficiency in most
2913 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2914 SImode in particular have a lot of room to optimize.
2915
2916 We first determine the strategy of the shift algorithm by a table
2917 lookup. If that tells us to use a hand crafted assembly code, we
2918 go into the big switch statement to find what that is. Otherwise,
2919 we resort to a generic way, such as inlining. In either case, the
2920 result is returned through INFO. */
2921
2922 static void
get_shift_alg(enum shift_type shift_type,enum shift_mode shift_mode,unsigned int count,struct shift_info * info)2923 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2924 unsigned int count, struct shift_info *info)
2925 {
2926 enum h8_cpu cpu;
2927
2928 /* Find the target CPU. */
2929 if (TARGET_H8300)
2930 cpu = H8_300;
2931 else if (TARGET_H8300H)
2932 cpu = H8_300H;
2933 else
2934 cpu = H8_S;
2935
2936 /* Find the shift algorithm. */
2937 info->alg = SHIFT_LOOP;
2938 switch (shift_mode)
2939 {
2940 case QIshift:
2941 if (count < GET_MODE_BITSIZE (QImode))
2942 info->alg = shift_alg_qi[cpu][shift_type][count];
2943 break;
2944
2945 case HIshift:
2946 if (count < GET_MODE_BITSIZE (HImode))
2947 info->alg = shift_alg_hi[cpu][shift_type][count];
2948 break;
2949
2950 case SIshift:
2951 if (count < GET_MODE_BITSIZE (SImode))
2952 info->alg = shift_alg_si[cpu][shift_type][count];
2953 break;
2954
2955 default:
2956 abort ();
2957 }
2958
2959 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2960 switch (info->alg)
2961 {
2962 case SHIFT_INLINE:
2963 info->remainder = count;
2964 /* Fall through. */
2965
2966 case SHIFT_LOOP:
2967 /* It is up to the caller to know that looping clobbers cc. */
2968 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2969 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2970 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2971 goto end;
2972
2973 case SHIFT_ROT_AND:
2974 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2975 info->shift2 = rotate_two[shift_type][shift_mode];
2976 info->cc_inline = CC_CLOBBER;
2977 goto end;
2978
2979 case SHIFT_SPECIAL:
2980 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2981 info->remainder = 0;
2982 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2983 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2984 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2985 info->cc_special = CC_CLOBBER;
2986 break;
2987 }
2988
2989 /* Here we only deal with SHIFT_SPECIAL. */
2990 switch (shift_mode)
2991 {
2992 case QIshift:
2993 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2994 through the entire value. */
2995 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2996 {
2997 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2998 goto end;
2999 }
3000 abort ();
3001
3002 case HIshift:
3003 if (count == 7)
3004 {
3005 switch (shift_type)
3006 {
3007 case SHIFT_ASHIFT:
3008 if (TARGET_H8300)
3009 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3010 else
3011 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3012 goto end;
3013 case SHIFT_LSHIFTRT:
3014 if (TARGET_H8300)
3015 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3016 else
3017 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3018 goto end;
3019 case SHIFT_ASHIFTRT:
3020 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3021 goto end;
3022 }
3023 }
3024 else if ((8 <= count && count <= 13)
3025 || (TARGET_H8300S && count == 14))
3026 {
3027 info->remainder = count - 8;
3028
3029 switch (shift_type)
3030 {
3031 case SHIFT_ASHIFT:
3032 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3033 goto end;
3034 case SHIFT_LSHIFTRT:
3035 if (TARGET_H8300)
3036 {
3037 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3038 info->shift1 = "shlr.b\t%s0";
3039 info->cc_inline = CC_SET_ZNV;
3040 }
3041 else
3042 {
3043 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3044 info->cc_special = CC_SET_ZNV;
3045 }
3046 goto end;
3047 case SHIFT_ASHIFTRT:
3048 if (TARGET_H8300)
3049 {
3050 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3051 info->shift1 = "shar.b\t%s0";
3052 }
3053 else
3054 {
3055 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3056 info->cc_special = CC_SET_ZNV;
3057 }
3058 goto end;
3059 }
3060 }
3061 else if (count == 14)
3062 {
3063 switch (shift_type)
3064 {
3065 case SHIFT_ASHIFT:
3066 if (TARGET_H8300)
3067 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3068 goto end;
3069 case SHIFT_LSHIFTRT:
3070 if (TARGET_H8300)
3071 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3072 goto end;
3073 case SHIFT_ASHIFTRT:
3074 if (TARGET_H8300)
3075 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3076 else if (TARGET_H8300H)
3077 {
3078 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3079 info->cc_special = CC_SET_ZNV;
3080 }
3081 else /* TARGET_H8300S */
3082 abort ();
3083 goto end;
3084 }
3085 }
3086 else if (count == 15)
3087 {
3088 switch (shift_type)
3089 {
3090 case SHIFT_ASHIFT:
3091 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3092 goto end;
3093 case SHIFT_LSHIFTRT:
3094 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3095 goto end;
3096 case SHIFT_ASHIFTRT:
3097 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3098 goto end;
3099 }
3100 }
3101 abort ();
3102
3103 case SIshift:
3104 if (TARGET_H8300 && 8 <= count && count <= 9)
3105 {
3106 info->remainder = count - 8;
3107
3108 switch (shift_type)
3109 {
3110 case SHIFT_ASHIFT:
3111 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3112 goto end;
3113 case SHIFT_LSHIFTRT:
3114 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3115 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3116 goto end;
3117 case SHIFT_ASHIFTRT:
3118 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3119 goto end;
3120 }
3121 }
3122 else if (count == 8 && !TARGET_H8300)
3123 {
3124 switch (shift_type)
3125 {
3126 case SHIFT_ASHIFT:
3127 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3128 goto end;
3129 case SHIFT_LSHIFTRT:
3130 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3131 goto end;
3132 case SHIFT_ASHIFTRT:
3133 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3134 goto end;
3135 }
3136 }
3137 else if (count == 15 && TARGET_H8300)
3138 {
3139 switch (shift_type)
3140 {
3141 case SHIFT_ASHIFT:
3142 abort ();
3143 case SHIFT_LSHIFTRT:
3144 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3145 goto end;
3146 case SHIFT_ASHIFTRT:
3147 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3148 goto end;
3149 }
3150 }
3151 else if (count == 15 && !TARGET_H8300)
3152 {
3153 switch (shift_type)
3154 {
3155 case SHIFT_ASHIFT:
3156 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3157 info->cc_special = CC_SET_ZNV;
3158 goto end;
3159 case SHIFT_LSHIFTRT:
3160 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3161 info->cc_special = CC_SET_ZNV;
3162 goto end;
3163 case SHIFT_ASHIFTRT:
3164 abort ();
3165 }
3166 }
3167 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3168 || (TARGET_H8300H && 16 <= count && count <= 19)
3169 || (TARGET_H8300S && 16 <= count && count <= 21))
3170 {
3171 info->remainder = count - 16;
3172
3173 switch (shift_type)
3174 {
3175 case SHIFT_ASHIFT:
3176 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3177 if (TARGET_H8300)
3178 info->shift1 = "add.w\t%e0,%e0";
3179 goto end;
3180 case SHIFT_LSHIFTRT:
3181 if (TARGET_H8300)
3182 {
3183 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3184 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3185 }
3186 else
3187 {
3188 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3189 info->cc_special = CC_SET_ZNV;
3190 }
3191 goto end;
3192 case SHIFT_ASHIFTRT:
3193 if (TARGET_H8300)
3194 {
3195 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3196 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3197 }
3198 else
3199 {
3200 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3201 info->cc_special = CC_SET_ZNV;
3202 }
3203 goto end;
3204 }
3205 }
3206 else if (TARGET_H8300 && 24 <= count && count <= 28)
3207 {
3208 info->remainder = count - 24;
3209
3210 switch (shift_type)
3211 {
3212 case SHIFT_ASHIFT:
3213 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3214 info->shift1 = "shll.b\t%z0";
3215 info->cc_inline = CC_SET_ZNV;
3216 goto end;
3217 case SHIFT_LSHIFTRT:
3218 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3219 info->shift1 = "shlr.b\t%w0";
3220 info->cc_inline = CC_SET_ZNV;
3221 goto end;
3222 case SHIFT_ASHIFTRT:
3223 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3224 info->shift1 = "shar.b\t%w0";
3225 info->cc_inline = CC_SET_ZNV;
3226 goto end;
3227 }
3228 }
3229 else if ((TARGET_H8300H && count == 24)
3230 || (TARGET_H8300S && 24 <= count && count <= 25))
3231 {
3232 info->remainder = count - 24;
3233
3234 switch (shift_type)
3235 {
3236 case SHIFT_ASHIFT:
3237 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3238 goto end;
3239 case SHIFT_LSHIFTRT:
3240 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3241 info->cc_special = CC_SET_ZNV;
3242 goto end;
3243 case SHIFT_ASHIFTRT:
3244 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3245 info->cc_special = CC_SET_ZNV;
3246 goto end;
3247 }
3248 }
3249 else if (!TARGET_H8300 && count == 28)
3250 {
3251 switch (shift_type)
3252 {
3253 case SHIFT_ASHIFT:
3254 if (TARGET_H8300H)
3255 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3256 else
3257 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3258 goto end;
3259 case SHIFT_LSHIFTRT:
3260 if (TARGET_H8300H)
3261 {
3262 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3263 info->cc_special = CC_SET_ZNV;
3264 }
3265 else
3266 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3267 goto end;
3268 case SHIFT_ASHIFTRT:
3269 abort ();
3270 }
3271 }
3272 else if (!TARGET_H8300 && count == 29)
3273 {
3274 switch (shift_type)
3275 {
3276 case SHIFT_ASHIFT:
3277 if (TARGET_H8300H)
3278 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3279 else
3280 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3281 goto end;
3282 case SHIFT_LSHIFTRT:
3283 if (TARGET_H8300H)
3284 {
3285 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3286 info->cc_special = CC_SET_ZNV;
3287 }
3288 else
3289 {
3290 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3291 info->cc_special = CC_SET_ZNV;
3292 }
3293 goto end;
3294 case SHIFT_ASHIFTRT:
3295 abort ();
3296 }
3297 }
3298 else if (!TARGET_H8300 && count == 30)
3299 {
3300 switch (shift_type)
3301 {
3302 case SHIFT_ASHIFT:
3303 if (TARGET_H8300H)
3304 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3305 else
3306 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3307 goto end;
3308 case SHIFT_LSHIFTRT:
3309 if (TARGET_H8300H)
3310 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3311 else
3312 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3313 goto end;
3314 case SHIFT_ASHIFTRT:
3315 abort ();
3316 }
3317 }
3318 else if (count == 31)
3319 {
3320 if (TARGET_H8300)
3321 {
3322 switch (shift_type)
3323 {
3324 case SHIFT_ASHIFT:
3325 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3326 goto end;
3327 case SHIFT_LSHIFTRT:
3328 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3329 goto end;
3330 case SHIFT_ASHIFTRT:
3331 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3332 goto end;
3333 }
3334 }
3335 else
3336 {
3337 switch (shift_type)
3338 {
3339 case SHIFT_ASHIFT:
3340 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3341 info->cc_special = CC_SET_ZNV;
3342 goto end;
3343 case SHIFT_LSHIFTRT:
3344 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3345 info->cc_special = CC_SET_ZNV;
3346 goto end;
3347 case SHIFT_ASHIFTRT:
3348 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3349 info->cc_special = CC_SET_ZNV;
3350 goto end;
3351 }
3352 }
3353 }
3354 abort ();
3355
3356 default:
3357 abort ();
3358 }
3359
3360 end:
3361 if (!TARGET_H8300S)
3362 info->shift2 = NULL;
3363 }
3364
3365 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3366 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3367
3368 int
h8300_shift_needs_scratch_p(int count,enum machine_mode mode)3369 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3370 {
3371 enum h8_cpu cpu;
3372 int a, lr, ar;
3373
3374 if (GET_MODE_BITSIZE (mode) <= count)
3375 return 1;
3376
3377 /* Find out the target CPU. */
3378 if (TARGET_H8300)
3379 cpu = H8_300;
3380 else if (TARGET_H8300H)
3381 cpu = H8_300H;
3382 else
3383 cpu = H8_S;
3384
3385 /* Find the shift algorithm. */
3386 switch (mode)
3387 {
3388 case QImode:
3389 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3390 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3391 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3392 break;
3393
3394 case HImode:
3395 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3396 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3397 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3398 break;
3399
3400 case SImode:
3401 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3402 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3403 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3404 break;
3405
3406 default:
3407 abort ();
3408 }
3409
3410 /* On H8/300H, count == 8 uses a scratch register. */
3411 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3412 || (TARGET_H8300H && mode == SImode && count == 8));
3413 }
3414
3415 /* Emit the assembler code for doing shifts. */
3416
3417 const char *
output_a_shift(rtx * operands)3418 output_a_shift (rtx *operands)
3419 {
3420 static int loopend_lab;
3421 rtx shift = operands[3];
3422 enum machine_mode mode = GET_MODE (shift);
3423 enum rtx_code code = GET_CODE (shift);
3424 enum shift_type shift_type;
3425 enum shift_mode shift_mode;
3426 struct shift_info info;
3427
3428 loopend_lab++;
3429
3430 switch (mode)
3431 {
3432 case QImode:
3433 shift_mode = QIshift;
3434 break;
3435 case HImode:
3436 shift_mode = HIshift;
3437 break;
3438 case SImode:
3439 shift_mode = SIshift;
3440 break;
3441 default:
3442 abort ();
3443 }
3444
3445 switch (code)
3446 {
3447 case ASHIFTRT:
3448 shift_type = SHIFT_ASHIFTRT;
3449 break;
3450 case LSHIFTRT:
3451 shift_type = SHIFT_LSHIFTRT;
3452 break;
3453 case ASHIFT:
3454 shift_type = SHIFT_ASHIFT;
3455 break;
3456 default:
3457 abort ();
3458 }
3459
3460 if (GET_CODE (operands[2]) != CONST_INT)
3461 {
3462 /* This case must be taken care of by one of the two splitters
3463 that convert a variable shift into a loop. */
3464 abort ();
3465 }
3466 else
3467 {
3468 int n = INTVAL (operands[2]);
3469
3470 /* If the count is negative, make it 0. */
3471 if (n < 0)
3472 n = 0;
3473 /* If the count is too big, truncate it.
3474 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3475 do the intuitive thing. */
3476 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3477 n = GET_MODE_BITSIZE (mode);
3478
3479 get_shift_alg (shift_type, shift_mode, n, &info);
3480
3481 switch (info.alg)
3482 {
3483 case SHIFT_SPECIAL:
3484 output_asm_insn (info.special, operands);
3485 /* Fall through. */
3486
3487 case SHIFT_INLINE:
3488 n = info.remainder;
3489
3490 /* Emit two bit shifts first. */
3491 if (info.shift2 != NULL)
3492 {
3493 for (; n > 1; n -= 2)
3494 output_asm_insn (info.shift2, operands);
3495 }
3496
3497 /* Now emit one bit shifts for any residual. */
3498 for (; n > 0; n--)
3499 output_asm_insn (info.shift1, operands);
3500 return "";
3501
3502 case SHIFT_ROT_AND:
3503 {
3504 int m = GET_MODE_BITSIZE (mode) - n;
3505 const int mask = (shift_type == SHIFT_ASHIFT
3506 ? ((1 << m) - 1) << n
3507 : (1 << m) - 1);
3508 char insn_buf[200];
3509
3510 /* Not all possibilities of rotate are supported. They shouldn't
3511 be generated, but let's watch for 'em. */
3512 if (info.shift1 == 0)
3513 abort ();
3514
3515 /* Emit two bit rotates first. */
3516 if (info.shift2 != NULL)
3517 {
3518 for (; m > 1; m -= 2)
3519 output_asm_insn (info.shift2, operands);
3520 }
3521
3522 /* Now single bit rotates for any residual. */
3523 for (; m > 0; m--)
3524 output_asm_insn (info.shift1, operands);
3525
3526 /* Now mask off the high bits. */
3527 if (mode == QImode)
3528 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3529 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3530 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3531 else
3532 abort ();
3533
3534 output_asm_insn (insn_buf, operands);
3535 return "";
3536 }
3537
3538 case SHIFT_LOOP:
3539 /* A loop to shift by a "large" constant value.
3540 If we have shift-by-2 insns, use them. */
3541 if (info.shift2 != NULL)
3542 {
3543 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3544 names_big[REGNO (operands[4])]);
3545 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3546 output_asm_insn (info.shift2, operands);
3547 output_asm_insn ("add #0xff,%X4", operands);
3548 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3549 if (n % 2)
3550 output_asm_insn (info.shift1, operands);
3551 }
3552 else
3553 {
3554 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3555 names_big[REGNO (operands[4])]);
3556 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3557 output_asm_insn (info.shift1, operands);
3558 output_asm_insn ("add #0xff,%X4", operands);
3559 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3560 }
3561 return "";
3562
3563 default:
3564 abort ();
3565 }
3566 }
3567 }
3568
3569 static unsigned int
h8300_asm_insn_count(const char * template)3570 h8300_asm_insn_count (const char *template)
3571 {
3572 unsigned int count = 1;
3573
3574 for (; *template; template++)
3575 if (*template == '\n')
3576 count++;
3577
3578 return count;
3579 }
3580
3581 unsigned int
compute_a_shift_length(rtx insn ATTRIBUTE_UNUSED,rtx * operands)3582 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3583 {
3584 rtx shift = operands[3];
3585 enum machine_mode mode = GET_MODE (shift);
3586 enum rtx_code code = GET_CODE (shift);
3587 enum shift_type shift_type;
3588 enum shift_mode shift_mode;
3589 struct shift_info info;
3590 unsigned int wlength = 0;
3591
3592 switch (mode)
3593 {
3594 case QImode:
3595 shift_mode = QIshift;
3596 break;
3597 case HImode:
3598 shift_mode = HIshift;
3599 break;
3600 case SImode:
3601 shift_mode = SIshift;
3602 break;
3603 default:
3604 abort ();
3605 }
3606
3607 switch (code)
3608 {
3609 case ASHIFTRT:
3610 shift_type = SHIFT_ASHIFTRT;
3611 break;
3612 case LSHIFTRT:
3613 shift_type = SHIFT_LSHIFTRT;
3614 break;
3615 case ASHIFT:
3616 shift_type = SHIFT_ASHIFT;
3617 break;
3618 default:
3619 abort ();
3620 }
3621
3622 if (GET_CODE (operands[2]) != CONST_INT)
3623 {
3624 /* Get the assembler code to do one shift. */
3625 get_shift_alg (shift_type, shift_mode, 1, &info);
3626
3627 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3628 }
3629 else
3630 {
3631 int n = INTVAL (operands[2]);
3632
3633 /* If the count is negative, make it 0. */
3634 if (n < 0)
3635 n = 0;
3636 /* If the count is too big, truncate it.
3637 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3638 do the intuitive thing. */
3639 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3640 n = GET_MODE_BITSIZE (mode);
3641
3642 get_shift_alg (shift_type, shift_mode, n, &info);
3643
3644 switch (info.alg)
3645 {
3646 case SHIFT_SPECIAL:
3647 wlength += h8300_asm_insn_count (info.special);
3648
3649 /* Every assembly instruction used in SHIFT_SPECIAL case
3650 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3651 see xor.l, we just pretend that xor.l counts as two insns
3652 so that the insn length will be computed correctly. */
3653 if (strstr (info.special, "xor.l") != NULL)
3654 wlength++;
3655
3656 /* Fall through. */
3657
3658 case SHIFT_INLINE:
3659 n = info.remainder;
3660
3661 if (info.shift2 != NULL)
3662 {
3663 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3664 n = n % 2;
3665 }
3666
3667 wlength += h8300_asm_insn_count (info.shift1) * n;
3668
3669 return 2 * wlength;
3670
3671 case SHIFT_ROT_AND:
3672 {
3673 int m = GET_MODE_BITSIZE (mode) - n;
3674
3675 /* Not all possibilities of rotate are supported. They shouldn't
3676 be generated, but let's watch for 'em. */
3677 if (info.shift1 == 0)
3678 abort ();
3679
3680 if (info.shift2 != NULL)
3681 {
3682 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3683 m = m % 2;
3684 }
3685
3686 wlength += h8300_asm_insn_count (info.shift1) * m;
3687
3688 /* Now mask off the high bits. */
3689 switch (mode)
3690 {
3691 case QImode:
3692 wlength += 1;
3693 break;
3694 case HImode:
3695 wlength += 2;
3696 break;
3697 case SImode:
3698 if (TARGET_H8300)
3699 abort ();
3700 wlength += 3;
3701 break;
3702 default:
3703 abort ();
3704 }
3705 return 2 * wlength;
3706 }
3707
3708 case SHIFT_LOOP:
3709 /* A loop to shift by a "large" constant value.
3710 If we have shift-by-2 insns, use them. */
3711 if (info.shift2 != NULL)
3712 {
3713 wlength += 3 + h8300_asm_insn_count (info.shift2);
3714 if (n % 2)
3715 wlength += h8300_asm_insn_count (info.shift1);
3716 }
3717 else
3718 {
3719 wlength += 3 + h8300_asm_insn_count (info.shift1);
3720 }
3721 return 2 * wlength;
3722
3723 default:
3724 abort ();
3725 }
3726 }
3727 }
3728
3729 int
compute_a_shift_cc(rtx insn ATTRIBUTE_UNUSED,rtx * operands)3730 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3731 {
3732 rtx shift = operands[3];
3733 enum machine_mode mode = GET_MODE (shift);
3734 enum rtx_code code = GET_CODE (shift);
3735 enum shift_type shift_type;
3736 enum shift_mode shift_mode;
3737 struct shift_info info;
3738
3739 switch (mode)
3740 {
3741 case QImode:
3742 shift_mode = QIshift;
3743 break;
3744 case HImode:
3745 shift_mode = HIshift;
3746 break;
3747 case SImode:
3748 shift_mode = SIshift;
3749 break;
3750 default:
3751 abort ();
3752 }
3753
3754 switch (code)
3755 {
3756 case ASHIFTRT:
3757 shift_type = SHIFT_ASHIFTRT;
3758 break;
3759 case LSHIFTRT:
3760 shift_type = SHIFT_LSHIFTRT;
3761 break;
3762 case ASHIFT:
3763 shift_type = SHIFT_ASHIFT;
3764 break;
3765 default:
3766 abort ();
3767 }
3768
3769 if (GET_CODE (operands[2]) != CONST_INT)
3770 {
3771 /* This case must be taken care of by one of the two splitters
3772 that convert a variable shift into a loop. */
3773 abort ();
3774 }
3775 else
3776 {
3777 int n = INTVAL (operands[2]);
3778
3779 /* If the count is negative, make it 0. */
3780 if (n < 0)
3781 n = 0;
3782 /* If the count is too big, truncate it.
3783 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3784 do the intuitive thing. */
3785 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3786 n = GET_MODE_BITSIZE (mode);
3787
3788 get_shift_alg (shift_type, shift_mode, n, &info);
3789
3790 switch (info.alg)
3791 {
3792 case SHIFT_SPECIAL:
3793 if (info.remainder == 0)
3794 return info.cc_special;
3795
3796 /* Fall through. */
3797
3798 case SHIFT_INLINE:
3799 return info.cc_inline;
3800
3801 case SHIFT_ROT_AND:
3802 /* This case always ends with an and instruction. */
3803 return CC_SET_ZNV;
3804
3805 case SHIFT_LOOP:
3806 /* A loop to shift by a "large" constant value.
3807 If we have shift-by-2 insns, use them. */
3808 if (info.shift2 != NULL)
3809 {
3810 if (n % 2)
3811 return info.cc_inline;
3812 }
3813 return CC_CLOBBER;
3814
3815 default:
3816 abort ();
3817 }
3818 }
3819 }
3820
3821 /* A rotation by a non-constant will cause a loop to be generated, in
3822 which a rotation by one bit is used. A rotation by a constant,
3823 including the one in the loop, will be taken care of by
3824 output_a_rotate () at the insn emit time. */
3825
3826 int
expand_a_rotate(enum rtx_code code,rtx operands[])3827 expand_a_rotate (enum rtx_code code, rtx operands[])
3828 {
3829 rtx dst = operands[0];
3830 rtx src = operands[1];
3831 rtx rotate_amount = operands[2];
3832 enum machine_mode mode = GET_MODE (dst);
3833 rtx tmp;
3834
3835 /* We rotate in place. */
3836 emit_move_insn (dst, src);
3837
3838 if (GET_CODE (rotate_amount) != CONST_INT)
3839 {
3840 rtx counter = gen_reg_rtx (QImode);
3841 rtx start_label = gen_label_rtx ();
3842 rtx end_label = gen_label_rtx ();
3843
3844 /* If the rotate amount is less than or equal to 0,
3845 we go out of the loop. */
3846 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3847 QImode, 0, end_label);
3848
3849 /* Initialize the loop counter. */
3850 emit_move_insn (counter, rotate_amount);
3851
3852 emit_label (start_label);
3853
3854 /* Rotate by one bit. */
3855 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3856 emit_insn (gen_rtx_SET (mode, dst, tmp));
3857
3858 /* Decrement the counter by 1. */
3859 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3860 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3861
3862 /* If the loop counter is nonzero, we go back to the beginning
3863 of the loop. */
3864 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3865 start_label);
3866
3867 emit_label (end_label);
3868 }
3869 else
3870 {
3871 /* Rotate by AMOUNT bits. */
3872 tmp = gen_rtx (code, mode, dst, rotate_amount);
3873 emit_insn (gen_rtx_SET (mode, dst, tmp));
3874 }
3875
3876 return 1;
3877 }
3878
3879 /* Output rotate insns. */
3880
3881 const char *
output_a_rotate(enum rtx_code code,rtx * operands)3882 output_a_rotate (enum rtx_code code, rtx *operands)
3883 {
3884 rtx dst = operands[0];
3885 rtx rotate_amount = operands[2];
3886 enum shift_mode rotate_mode;
3887 enum shift_type rotate_type;
3888 const char *insn_buf;
3889 int bits;
3890 int amount;
3891 enum machine_mode mode = GET_MODE (dst);
3892
3893 if (GET_CODE (rotate_amount) != CONST_INT)
3894 abort ();
3895
3896 switch (mode)
3897 {
3898 case QImode:
3899 rotate_mode = QIshift;
3900 break;
3901 case HImode:
3902 rotate_mode = HIshift;
3903 break;
3904 case SImode:
3905 rotate_mode = SIshift;
3906 break;
3907 default:
3908 abort ();
3909 }
3910
3911 switch (code)
3912 {
3913 case ROTATERT:
3914 rotate_type = SHIFT_ASHIFT;
3915 break;
3916 case ROTATE:
3917 rotate_type = SHIFT_LSHIFTRT;
3918 break;
3919 default:
3920 abort ();
3921 }
3922
3923 amount = INTVAL (rotate_amount);
3924
3925 /* Clean up AMOUNT. */
3926 if (amount < 0)
3927 amount = 0;
3928 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3929 amount = GET_MODE_BITSIZE (mode);
3930
3931 /* Determine the faster direction. After this phase, amount will be
3932 at most a half of GET_MODE_BITSIZE (mode). */
3933 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3934 {
3935 /* Flip the direction. */
3936 amount = GET_MODE_BITSIZE (mode) - amount;
3937 rotate_type =
3938 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3939 }
3940
3941 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3942 boost up the rotation. */
3943 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3944 || (mode == HImode && TARGET_H8300H && amount >= 6)
3945 || (mode == HImode && TARGET_H8300S && amount == 8)
3946 || (mode == SImode && TARGET_H8300H && amount >= 10)
3947 || (mode == SImode && TARGET_H8300S && amount >= 13))
3948 {
3949 switch (mode)
3950 {
3951 case HImode:
3952 /* This code works on any family. */
3953 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3954 output_asm_insn (insn_buf, operands);
3955 break;
3956
3957 case SImode:
3958 /* This code works on the H8/300H and H8S. */
3959 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3960 output_asm_insn (insn_buf, operands);
3961 break;
3962
3963 default:
3964 abort ();
3965 }
3966
3967 /* Adjust AMOUNT and flip the direction. */
3968 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3969 rotate_type =
3970 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3971 }
3972
3973 /* Emit rotate insns. */
3974 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3975 {
3976 if (bits == 2)
3977 insn_buf = rotate_two[rotate_type][rotate_mode];
3978 else
3979 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3980
3981 for (; amount >= bits; amount -= bits)
3982 output_asm_insn (insn_buf, operands);
3983 }
3984
3985 return "";
3986 }
3987
3988 unsigned int
compute_a_rotate_length(rtx * operands)3989 compute_a_rotate_length (rtx *operands)
3990 {
3991 rtx src = operands[1];
3992 rtx amount_rtx = operands[2];
3993 enum machine_mode mode = GET_MODE (src);
3994 int amount;
3995 unsigned int length = 0;
3996
3997 if (GET_CODE (amount_rtx) != CONST_INT)
3998 abort ();
3999
4000 amount = INTVAL (amount_rtx);
4001
4002 /* Clean up AMOUNT. */
4003 if (amount < 0)
4004 amount = 0;
4005 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4006 amount = GET_MODE_BITSIZE (mode);
4007
4008 /* Determine the faster direction. After this phase, amount
4009 will be at most a half of GET_MODE_BITSIZE (mode). */
4010 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4011 /* Flip the direction. */
4012 amount = GET_MODE_BITSIZE (mode) - amount;
4013
4014 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4015 boost up the rotation. */
4016 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4017 || (mode == HImode && TARGET_H8300H && amount >= 6)
4018 || (mode == HImode && TARGET_H8300S && amount == 8)
4019 || (mode == SImode && TARGET_H8300H && amount >= 10)
4020 || (mode == SImode && TARGET_H8300S && amount >= 13))
4021 {
4022 /* Adjust AMOUNT and flip the direction. */
4023 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4024 length += 6;
4025 }
4026
4027 /* We use 2-bit rotations on the H8S. */
4028 if (TARGET_H8300S)
4029 amount = amount / 2 + amount % 2;
4030
4031 /* The H8/300 uses three insns to rotate one bit, taking 6
4032 length. */
4033 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4034
4035 return length;
4036 }
4037
4038 /* Fix the operands of a gen_xxx so that it could become a bit
4039 operating insn. */
4040
4041 int
fix_bit_operand(rtx * operands,int what,enum rtx_code type)4042 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4043 {
4044 /* The bit_operand predicate accepts any memory during RTL generation, but
4045 only 'U' memory afterwards, so if this is a MEM operand, we must force
4046 it to be valid for 'U' by reloading the address. */
4047
4048 if ((what == 0 && single_zero_operand (operands[2], QImode))
4049 || (what == 1 && single_one_operand (operands[2], QImode)))
4050 {
4051 /* OK to have a memory dest. */
4052 if (GET_CODE (operands[0]) == MEM
4053 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4054 {
4055 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4056 copy_to_mode_reg (Pmode,
4057 XEXP (operands[0], 0)));
4058 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4059 operands[0] = mem;
4060 }
4061
4062 if (GET_CODE (operands[1]) == MEM
4063 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4064 {
4065 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4066 copy_to_mode_reg (Pmode,
4067 XEXP (operands[1], 0)));
4068 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4069 operands[1] = mem;
4070 }
4071 return 0;
4072 }
4073
4074 /* Dest and src op must be register. */
4075
4076 operands[1] = force_reg (QImode, operands[1]);
4077 {
4078 rtx res = gen_reg_rtx (QImode);
4079 emit_insn (gen_rtx_SET (VOIDmode, res,
4080 gen_rtx (type, QImode, operands[1], operands[2])));
4081 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
4082 }
4083 return 1;
4084 }
4085
4086 /* Return nonzero if FUNC is an interrupt function as specified
4087 by the "interrupt" attribute. */
4088
4089 static int
h8300_interrupt_function_p(tree func)4090 h8300_interrupt_function_p (tree func)
4091 {
4092 tree a;
4093
4094 if (TREE_CODE (func) != FUNCTION_DECL)
4095 return 0;
4096
4097 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4098 return a != NULL_TREE;
4099 }
4100
4101 /* Return nonzero if FUNC is a saveall function as specified by the
4102 "saveall" attribute. */
4103
4104 static int
h8300_saveall_function_p(tree func)4105 h8300_saveall_function_p (tree func)
4106 {
4107 tree a;
4108
4109 if (TREE_CODE (func) != FUNCTION_DECL)
4110 return 0;
4111
4112 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4113 return a != NULL_TREE;
4114 }
4115
4116 /* Return nonzero if FUNC is an OS_Task function as specified
4117 by the "OS_Task" attribute. */
4118
4119 static int
h8300_os_task_function_p(tree func)4120 h8300_os_task_function_p (tree func)
4121 {
4122 tree a;
4123
4124 if (TREE_CODE (func) != FUNCTION_DECL)
4125 return 0;
4126
4127 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4128 return a != NULL_TREE;
4129 }
4130
4131 /* Return nonzero if FUNC is a monitor function as specified
4132 by the "monitor" attribute. */
4133
4134 static int
h8300_monitor_function_p(tree func)4135 h8300_monitor_function_p (tree func)
4136 {
4137 tree a;
4138
4139 if (TREE_CODE (func) != FUNCTION_DECL)
4140 return 0;
4141
4142 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4143 return a != NULL_TREE;
4144 }
4145
4146 /* Return nonzero if FUNC is a function that should be called
4147 through the function vector. */
4148
4149 int
h8300_funcvec_function_p(tree func)4150 h8300_funcvec_function_p (tree func)
4151 {
4152 tree a;
4153
4154 if (TREE_CODE (func) != FUNCTION_DECL)
4155 return 0;
4156
4157 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4158 return a != NULL_TREE;
4159 }
4160
4161 /* Return nonzero if DECL is a variable that's in the eight bit
4162 data area. */
4163
4164 int
h8300_eightbit_data_p(tree decl)4165 h8300_eightbit_data_p (tree decl)
4166 {
4167 tree a;
4168
4169 if (TREE_CODE (decl) != VAR_DECL)
4170 return 0;
4171
4172 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4173 return a != NULL_TREE;
4174 }
4175
4176 /* Return nonzero if DECL is a variable that's in the tiny
4177 data area. */
4178
4179 int
h8300_tiny_data_p(tree decl)4180 h8300_tiny_data_p (tree decl)
4181 {
4182 tree a;
4183
4184 if (TREE_CODE (decl) != VAR_DECL)
4185 return 0;
4186
4187 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4188 return a != NULL_TREE;
4189 }
4190
4191 /* Generate an 'interrupt_handler' attribute for decls. We convert
4192 all the pragmas to corresponding attributes. */
4193
4194 static void
h8300_insert_attributes(tree node,tree * attributes)4195 h8300_insert_attributes (tree node, tree *attributes)
4196 {
4197 if (TREE_CODE (node) == FUNCTION_DECL)
4198 {
4199 if (pragma_interrupt)
4200 {
4201 pragma_interrupt = 0;
4202
4203 /* Add an 'interrupt_handler' attribute. */
4204 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4205 NULL, *attributes);
4206 }
4207
4208 if (pragma_saveall)
4209 {
4210 pragma_saveall = 0;
4211
4212 /* Add an 'saveall' attribute. */
4213 *attributes = tree_cons (get_identifier ("saveall"),
4214 NULL, *attributes);
4215 }
4216 }
4217 }
4218
4219 /* Supported attributes:
4220
4221 interrupt_handler: output a prologue and epilogue suitable for an
4222 interrupt handler.
4223
4224 saveall: output a prologue and epilogue that saves and restores
4225 all registers except the stack pointer.
4226
4227 function_vector: This function should be called through the
4228 function vector.
4229
4230 eightbit_data: This variable lives in the 8-bit data area and can
4231 be referenced with 8-bit absolute memory addresses.
4232
4233 tiny_data: This variable lives in the tiny data area and can be
4234 referenced with 16-bit absolute memory references. */
4235
4236 const struct attribute_spec h8300_attribute_table[] =
4237 {
4238 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4239 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4240 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4241 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4242 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4243 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4244 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4245 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4246 { NULL, 0, 0, false, false, false, NULL }
4247 };
4248
4249
4250 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4251 struct attribute_spec.handler. */
4252 static tree
h8300_handle_fndecl_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)4253 h8300_handle_fndecl_attribute (tree *node, tree name,
4254 tree args ATTRIBUTE_UNUSED,
4255 int flags ATTRIBUTE_UNUSED,
4256 bool *no_add_attrs)
4257 {
4258 if (TREE_CODE (*node) != FUNCTION_DECL)
4259 {
4260 warning ("`%s' attribute only applies to functions",
4261 IDENTIFIER_POINTER (name));
4262 *no_add_attrs = true;
4263 }
4264
4265 return NULL_TREE;
4266 }
4267
4268 /* Handle an "eightbit_data" attribute; arguments as in
4269 struct attribute_spec.handler. */
4270 static tree
h8300_handle_eightbit_data_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)4271 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4272 tree args ATTRIBUTE_UNUSED,
4273 int flags ATTRIBUTE_UNUSED,
4274 bool *no_add_attrs)
4275 {
4276 tree decl = *node;
4277
4278 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4279 {
4280 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4281 }
4282 else
4283 {
4284 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4285 *no_add_attrs = true;
4286 }
4287
4288 return NULL_TREE;
4289 }
4290
4291 /* Handle an "tiny_data" attribute; arguments as in
4292 struct attribute_spec.handler. */
4293 static tree
h8300_handle_tiny_data_attribute(tree * node,tree name,tree args ATTRIBUTE_UNUSED,int flags ATTRIBUTE_UNUSED,bool * no_add_attrs)4294 h8300_handle_tiny_data_attribute (tree *node, tree name,
4295 tree args ATTRIBUTE_UNUSED,
4296 int flags ATTRIBUTE_UNUSED,
4297 bool *no_add_attrs)
4298 {
4299 tree decl = *node;
4300
4301 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4302 {
4303 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4304 }
4305 else
4306 {
4307 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4308 *no_add_attrs = true;
4309 }
4310
4311 return NULL_TREE;
4312 }
4313
4314 /* Mark function vectors, and various small data objects. */
4315
4316 static void
h8300_encode_section_info(tree decl,rtx rtl,int first)4317 h8300_encode_section_info (tree decl, rtx rtl, int first)
4318 {
4319 int extra_flags = 0;
4320
4321 default_encode_section_info (decl, rtl, first);
4322
4323 if (TREE_CODE (decl) == FUNCTION_DECL
4324 && h8300_funcvec_function_p (decl))
4325 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4326 else if (TREE_CODE (decl) == VAR_DECL
4327 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4328 {
4329 if (h8300_eightbit_data_p (decl))
4330 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4331 else if (first && h8300_tiny_data_p (decl))
4332 extra_flags = SYMBOL_FLAG_TINY_DATA;
4333 }
4334
4335 if (extra_flags)
4336 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4337 }
4338
4339 const char *
output_simode_bld(int bild,rtx operands[])4340 output_simode_bld (int bild, rtx operands[])
4341 {
4342 if (TARGET_H8300)
4343 {
4344 /* Clear the destination register. */
4345 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4346
4347 /* Now output the bit load or bit inverse load, and store it in
4348 the destination. */
4349 if (bild)
4350 output_asm_insn ("bild\t%Z2,%Y1", operands);
4351 else
4352 output_asm_insn ("bld\t%Z2,%Y1", operands);
4353
4354 output_asm_insn ("bst\t#0,%w0", operands);
4355 }
4356 else
4357 {
4358 /* Determine if we can clear the destination first. */
4359 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4360 && REGNO (operands[0]) != REGNO (operands[1]));
4361
4362 if (clear_first)
4363 output_asm_insn ("sub.l\t%S0,%S0", operands);
4364
4365 /* Output the bit load or bit inverse load. */
4366 if (bild)
4367 output_asm_insn ("bild\t%Z2,%Y1", operands);
4368 else
4369 output_asm_insn ("bld\t%Z2,%Y1", operands);
4370
4371 if (!clear_first)
4372 output_asm_insn ("xor.l\t%S0,%S0", operands);
4373
4374 /* Perform the bit store. */
4375 output_asm_insn ("rotxl.l\t%S0", operands);
4376 }
4377
4378 /* All done. */
4379 return "";
4380 }
4381
4382 #ifndef OBJECT_FORMAT_ELF
4383 static void
h8300_asm_named_section(const char * name,unsigned int flags ATTRIBUTE_UNUSED)4384 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4385 {
4386 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4387 fprintf (asm_out_file, "\t.section %s\n", name);
4388 }
4389 #endif /* ! OBJECT_FORMAT_ELF */
4390
4391 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4392 which is a special case of the 'R' operand. */
4393
4394 int
h8300_eightbit_constant_address_p(rtx x)4395 h8300_eightbit_constant_address_p (rtx x)
4396 {
4397 /* The ranges of the 8-bit area. */
4398 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4399 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4400 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4401 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4402 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4403 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4404
4405 unsigned HOST_WIDE_INT addr;
4406
4407 /* We accept symbols declared with eightbit_data. */
4408 if (GET_CODE (x) == SYMBOL_REF)
4409 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4410
4411 if (GET_CODE (x) != CONST_INT)
4412 return 0;
4413
4414 addr = INTVAL (x);
4415
4416 return (0
4417 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4418 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4419 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4420 }
4421
4422 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4423 on H8/300H and H8S. */
4424
4425 int
h8300_tiny_constant_address_p(rtx x)4426 h8300_tiny_constant_address_p (rtx x)
4427 {
4428 /* The ranges of the 16-bit area. */
4429 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4430 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4431 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4432 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4433 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4434 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4435 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4436 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4437
4438 unsigned HOST_WIDE_INT addr;
4439
4440 /* We accept symbols declared with tiny_data. */
4441 if (GET_CODE (x) == SYMBOL_REF)
4442 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4443
4444 if (GET_CODE (x) != CONST_INT)
4445 return 0;
4446
4447 addr = INTVAL (x);
4448
4449 return (0
4450 || TARGET_NORMAL_MODE
4451 || (TARGET_H8300H
4452 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4453 || (TARGET_H8300S
4454 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4455 }
4456
4457 int
byte_accesses_mergeable_p(rtx addr1,rtx addr2)4458 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4459 {
4460 HOST_WIDE_INT offset1, offset2;
4461 rtx reg1, reg2;
4462
4463 if (REG_P (addr1))
4464 {
4465 reg1 = addr1;
4466 offset1 = 0;
4467 }
4468 else if (GET_CODE (addr1) == PLUS
4469 && REG_P (XEXP (addr1, 0))
4470 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4471 {
4472 reg1 = XEXP (addr1, 0);
4473 offset1 = INTVAL (XEXP (addr1, 1));
4474 }
4475 else
4476 return 0;
4477
4478 if (REG_P (addr2))
4479 {
4480 reg2 = addr2;
4481 offset2 = 0;
4482 }
4483 else if (GET_CODE (addr2) == PLUS
4484 && REG_P (XEXP (addr2, 0))
4485 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4486 {
4487 reg2 = XEXP (addr2, 0);
4488 offset2 = INTVAL (XEXP (addr2, 1));
4489 }
4490 else
4491 return 0;
4492
4493 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4494 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4495 && offset1 % 2 == 0
4496 && offset1 + 1 == offset2)
4497 return 1;
4498
4499 return 0;
4500 }
4501
4502 /* Return nonzero if we have the same comparison insn as I3 two insns
4503 before I3. I3 is assumed to be a comparison insn. */
4504
4505 int
same_cmp_preceding_p(rtx i3)4506 same_cmp_preceding_p (rtx i3)
4507 {
4508 rtx i1, i2;
4509
4510 /* Make sure we have a sequence of three insns. */
4511 i2 = prev_nonnote_insn (i3);
4512 if (i2 == NULL_RTX)
4513 return 0;
4514 i1 = prev_nonnote_insn (i2);
4515 if (i1 == NULL_RTX)
4516 return 0;
4517
4518 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4519 && any_condjump_p (i2) && onlyjump_p (i2));
4520 }
4521
4522 /* Return nonzero if we have the same comparison insn as I1 two insns
4523 after I1. I1 is assumed to be a comparison insn. */
4524
4525 int
same_cmp_following_p(rtx i1)4526 same_cmp_following_p (rtx i1)
4527 {
4528 rtx i2, i3;
4529
4530 /* Make sure we have a sequence of three insns. */
4531 i2 = next_nonnote_insn (i1);
4532 if (i2 == NULL_RTX)
4533 return 0;
4534 i3 = next_nonnote_insn (i2);
4535 if (i3 == NULL_RTX)
4536 return 0;
4537
4538 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4539 && any_condjump_p (i2) && onlyjump_p (i2));
4540 }
4541
4542 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4543
4544 int
h8300_hard_regno_rename_ok(unsigned int old_reg ATTRIBUTE_UNUSED,unsigned int new_reg)4545 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4546 unsigned int new_reg)
4547 {
4548 /* Interrupt functions can only use registers that have already been
4549 saved by the prologue, even if they would normally be
4550 call-clobbered. */
4551
4552 if (h8300_current_function_interrupt_function_p ()
4553 && !regs_ever_live[new_reg])
4554 return 0;
4555
4556 return 1;
4557 }
4558
4559 /* Perform target dependent optabs initialization. */
4560 static void
h8300_init_libfuncs(void)4561 h8300_init_libfuncs (void)
4562 {
4563 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4564 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4565 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4566 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4567 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4568 }
4569
4570 static bool
h8300_return_in_memory(tree type,tree fntype ATTRIBUTE_UNUSED)4571 h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4572 {
4573 return (TYPE_MODE (type) == BLKmode
4574 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4575 }
4576
4577 /* Initialize the GCC target structure. */
4578 #undef TARGET_ATTRIBUTE_TABLE
4579 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4580
4581 #undef TARGET_ASM_ALIGNED_HI_OP
4582 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4583
4584 #undef TARGET_ASM_FILE_START
4585 #define TARGET_ASM_FILE_START h8300_file_start
4586 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4587 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4588
4589 #undef TARGET_ASM_FILE_END
4590 #define TARGET_ASM_FILE_END h8300_file_end
4591
4592 #undef TARGET_ENCODE_SECTION_INFO
4593 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4594
4595 #undef TARGET_INSERT_ATTRIBUTES
4596 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4597
4598 #undef TARGET_RTX_COSTS
4599 #define TARGET_RTX_COSTS h8300_rtx_costs
4600
4601 #undef TARGET_INIT_LIBFUNCS
4602 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4603
4604 #undef TARGET_STRUCT_VALUE_RTX
4605 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
4606 #undef TARGET_RETURN_IN_MEMORY
4607 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4608
4609 struct gcc_target targetm = TARGET_INITIALIZER;
4610