xref: /openbsd/sys/dev/usb/if_urereg.h (revision dcec61dc)
1 /*	$OpenBSD: if_urereg.h,v 1.13 2023/08/15 08:27:30 miod Exp $	*/
2 /*-
3  * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  */
29 
30 #define	URE_CONFIG_IDX		0	/* config number 1 */
31 #define	URE_IFACE_IDX		0
32 
33 #define	URE_CTL_READ		0x01
34 #define	URE_CTL_WRITE		0x02
35 
36 #define	URE_TIMEOUT		1000
37 #define	URE_PHY_TIMEOUT		2000
38 
39 #define	URE_BYTE_EN_DWORD	0xff
40 #define	URE_BYTE_EN_WORD	0x33
41 #define	URE_BYTE_EN_BYTE	0x11
42 #define	URE_BYTE_EN_SIX_BYTES	0x3f
43 
44 #define URE_FRAMELEN(mtu)	\
45 	(mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN)
46 #define URE_JUMBO_FRAMELEN	(9 * 1024)
47 #define URE_JUMBO_MTU						\
48 	(URE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN -	\
49 	 ETHER_VLAN_ENCAP_LEN)
50 
51 #define	URE_PLA_IDR		0xc000
52 #define	URE_PLA_RCR		0xc010
53 #define	URE_PLA_RCR1		0xc012
54 #define	URE_PLA_RMS		0xc016
55 #define	URE_PLA_RXFIFO_CTRL0	0xc0a0
56 #define	URE_PLA_RXFIFO_FULL	0xc0a2
57 #define	URE_PLA_RXFIFO_CTRL1	0xc0a4
58 #define	URE_PLA_RX_FIFO_FULL	0xc0a6
59 #define	URE_PLA_RXFIFO_CTRL2	0xc0a8
60 #define	URE_PLA_RX_FIFO_EMPTY	0xc0aa
61 #define	URE_PLA_DMY_REG0	0xc0b0
62 #define	URE_PLA_FMC		0xc0b4
63 #define	URE_PLA_CFG_WOL		0xc0b6
64 #define	URE_PLA_TEREDO_CFG	0xc0bc
65 #define	URE_PLA_MAR		0xcd00
66 #define	URE_PLA_BACKUP		0xd000
67 #define	URE_PLA_BDC_CR		0xd1a0
68 #define	URE_PLA_TEREDO_TIMER	0xd2cc
69 #define	URE_PLA_REALWOW_TIMER	0xd2e8
70 #define	URE_PLA_SUSPEND_FLAG	0xd38a
71 #define	URE_PLA_INDICATE_FALG	0xd38c
72 #define	URE_PLA_EXTRA_STATUS	0xd398
73 #define	URE_PLA_GPHY_CTRL	0xd3ae
74 #define	URE_PLA_POL_GPIO_CTRL	0xdc6a
75 #define	URE_PLA_LEDSEL		0xdd90
76 #define	URE_PLA_LED_FEATURE	0xdd92
77 #define	URE_PLA_PHYAR		0xde00
78 #define	URE_PLA_BOOT_CTRL	0xe004
79 #define	URE_PLA_LWAKE_CTRL_REG	0xe007
80 #define	URE_PLA_GPHY_INTR_IMR	0xe022
81 #define	URE_PLA_EEE_CR		0xe040
82 #define	URE_PLA_EEEP_CR		0xe080
83 #define	URE_PLA_MAC_PWR_CTRL	0xe0c0
84 #define	URE_PLA_MAC_PWR_CTRL2	0xe0ca
85 #define	URE_PLA_MAC_PWR_CTRL3	0xe0cc
86 #define	URE_PLA_MAC_PWR_CTRL4	0xe0ce
87 #define	URE_PLA_WDT6_CTRL	0xe428
88 #define	URE_PLA_TCR0		0xe610
89 #define	URE_PLA_TCR1		0xe612
90 #define	URE_PLA_MTPS		0xe615
91 #define	URE_PLA_TXFIFO_CTRL	0xe618
92 #define	URE_PLA_TXFIFO_FULL	0xe61a
93 #define	URE_PLA_RSTTALLY	0xe800
94 #define	URE_PLA_CR		0xe813
95 #define	URE_PLA_CRWECR		0xe81c
96 #define	URE_PLA_CONFIG34	0xe820
97 #define	URE_PLA_CONFIG5		0xe822
98 #define	URE_PLA_PHY_PWR		0xe84c
99 #define	URE_PLA_OOB_CTRL	0xe84f
100 #define	URE_PLA_CPCR		0xe854
101 #define	URE_PLA_MISC_0		0xe858
102 #define	URE_PLA_MISC_1		0xe85a
103 #define	URE_PLA_OCP_GPHY_BASE	0xe86c
104 #define	URE_PLA_TELLYCNT	0xe890
105 #define	URE_PLA_SFF_STS_7	0xe8de
106 #define	URE_PLA_PHYSTATUS	0xe908
107 #define	URE_PLA_CONFIG6		0xe90a
108 #define	URE_PLA_USB_CFG		0xe952
109 
110 #define	URE_USB_USB2PHY		0xb41e
111 #define	URE_USB_SSPHYLINK1	0xb426
112 #define	URE_USB_SSPHYLINK2	0xb428
113 #define	URE_USB_U2P3_CTRL	0xb460
114 #define	URE_USB_CSR_DUMMY1	0xb464
115 #define	URE_USB_CSR_DUMMY2	0xb466
116 #define	URE_USB_DEV_STAT	0xb808
117 #define	URE_USB_CONNECT_TIMER	0xcbf8
118 #define	URE_USB_MSC_TIMER	0xcbfc
119 #define	URE_USB_BURST_SIZE	0xcfc0
120 #define	URE_USB_LPM_CONFIG	0xcfd8
121 #define	URE_USB_ECM_OPTION	0xcfee
122 #define	URE_USB_MISC_2		0xcfff
123 #define	URE_USB_ECM_OP		0xd26b
124 #define	URE_USB_GPHY_CTRL	0xd284
125 #define	URE_USB_SPEED_OPTION	0xd32a
126 #define	URE_USB_FW_CTRL		0xd334
127 #define	URE_USB_FC_TIMER	0xd340
128 #define	URE_USB_USB_CTRL	0xd406
129 #define	URE_USB_PHY_CTRL	0xd408
130 #define	URE_USB_TX_AGG		0xd40a
131 #define	URE_USB_RX_BUF_TH	0xd40c
132 #define	URE_USB_LPM_CTRL	0xd41a
133 #define	URE_USB_USB_TIMER	0xd428
134 #define	URE_USB_RX_EARLY_AGG	0xd42c
135 #define	URE_USB_RX_EARLY_SIZE	0xd42e
136 #define	URE_USB_PM_CTRL_STATUS	0xd432
137 #define	URE_USB_TX_DMA		0xd434
138 #define	URE_USB_UPT_RXDMA_OWN	0xd437
139 #define	URE_USB_TOLERANCE	0xd490
140 #define	URE_USB_BMU_RESET	0xd4b0
141 #define	URE_USB_BMU_CONFIG	0xd4b4
142 #define	URE_USB_U1U2_TIMER	0xd4da
143 #define	URE_USB_FW_TASK		0xd4e8
144 #define	URE_USB_RX_AGGR_NUM	0xd4ee
145 #define	URE_USB_UPS_CTRL	0xd800
146 #define	URE_USB_POWER_CUT	0xd80a
147 #define	URE_USB_MISC_0		0xd81a
148 #define	URE_USB_POWER_CUT	0xd80a
149 #define	URE_USB_AFE_CTRL2	0xd824
150 #define	URE_USB_UPS_FLAGS	0xd848
151 #define	URE_USB_WDT11_CTRL	0xe43c
152 
153 /* OCP Registers. */
154 #define	URE_OCP_ALDPS_CONFIG	0x2010
155 #define	URE_OCP_EEE_CONFIG1	0x2080
156 #define	URE_OCP_EEE_CONFIG2	0x2092
157 #define	URE_OCP_EEE_CONFIG3	0x2094
158 #define	URE_OCP_BASE_MII	0xa400
159 #define	URE_OCP_EEE_AR		0xa41a
160 #define	URE_OCP_EEE_DATA	0xa41c
161 #define	URE_OCP_PHY_STATUS	0xa420
162 #define	URE_OCP_POWER_CFG	0xa430
163 #define	URE_OCP_EEE_CFG		0xa432
164 #define	URE_OCP_SRAM_ADDR	0xa436
165 #define	URE_OCP_SRAM_DATA	0xa438
166 #define	URE_OCP_DOWN_SPEED	0xa442
167 #define	URE_OCP_EEE_ABLE	0xa5c4
168 #define	URE_OCP_EEE_ADV		0xa5d0
169 #define	URE_OCP_EEE_LPABLE	0xa5d2
170 #define	URE_OCP_10GBT_CTRL	0xa5d4
171 #define	URE_OCP_PHY_STATE	0xa708
172 #define	URE_OCP_ADC_CFG		0xbc06
173 
174 /* SRAM Register. */
175 #define	URE_SRAM_LPF_CFG	0x8012
176 #define	URE_SRAM_10M_AMP1	0x8080
177 #define	URE_SRAM_10M_AMP2	0x8082
178 #define	URE_SRAM_IMPEDANCE	0x8084
179 
180 /* URE_PLA_RCR */
181 #define	URE_RCR_AAP		0x00000001
182 #define	URE_RCR_APM		0x00000002
183 #define	URE_RCR_AM		0x00000004
184 #define	URE_RCR_AB		0x00000008
185 #define	URE_RCR_ACPT_ALL	\
186 	(URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB)
187 #define	URE_SLOT_EN		0x00000800
188 
189 /* URE_PLA_RCR1 */
190 #define	URE_INNER_VLAN		0x0040
191 #define	URE_OUTER_VLAN		0x0080
192 
193 /* URE_PLA_RXFIFO_CTRL0 */
194 #define	URE_RXFIFO_THR1_NORMAL	0x00080002
195 #define	URE_RXFIFO_THR1_OOB	0x01800003
196 
197 /* URE_PLA_RXFIFO_FULL */
198 #define URE_RXFIFO_FULL_MASK	0x0fff
199 
200 /* URE_PLA_RXFIFO_CTRL1 */
201 #define	URE_RXFIFO_THR2_FULL	0x00000060
202 #define	URE_RXFIFO_THR2_HIGH	0x00000038
203 #define	URE_RXFIFO_THR2_OOB	0x0000004a
204 #define	URE_RXFIFO_THR2_NORMAL	0x00a0
205 
206 /* URE_PLA_RXFIFO_CTRL2 */
207 #define	URE_RXFIFO_THR3_FULL	0x00000078
208 #define	URE_RXFIFO_THR3_HIGH	0x00000048
209 #define	URE_RXFIFO_THR3_OOB	0x0000005a
210 #define	URE_RXFIFO_THR3_NORMAL	0x0110
211 
212 /* URE_PLA_TXFIFO_CTRL */
213 #define	URE_TXFIFO_THR_NORMAL	0x00400008
214 #define	URE_TXFIFO_THR_NORMAL2	0x01000008
215 
216 /* URE_PLA_DMY_REG0 */
217 #define	URE_ECM_ALDPS		0x0002
218 
219 /* URE_PLA_FMC */
220 #define	URE_FMC_FCR_MCU_EN	0x0001
221 
222 /* URE_PLA_EEEP_CR */
223 #define	URE_EEEP_CR_EEEP_TX	0x0002
224 
225 /* URE_PLA_WDT6_CTRL */
226 #define	URE_WDT6_SET_MODE	0x0010
227 
228 /* URE_PLA_TCR0 */
229 #define	URE_TCR0_AUTO_FIFO	0x0080
230 #define	URE_TCR0_TX_EMPTY	0x0800
231 
232 /* URE_PLA_TCR1 */
233 #define	URE_VERSION_MASK	0x7cf0
234 
235 /* URE_PLA_MTPS */
236 #define	MTPS_DEFAULT		96
237 #define	MTPS_JUMBO		192
238 
239 /* URE_PLA_RSTTALLY */
240 #define	URE_TALLY_RESET		0x0001
241 
242 /* URE_PLA_CR */
243 #define	URE_CR_RST		0x10
244 #define	URE_CR_RE		0x08
245 #define	URE_CR_TE		0x04
246 
247 /* URE_PLA_CRWECR */
248 #define	URE_CRWECR_NORAML	0x00
249 #define	URE_CRWECR_CONFIG	0xc0
250 
251 /* URE_PLA_OOB_CTRL */
252 #define	URE_DIS_MCU_CLROOB	0x01
253 #define	URE_LINK_LIST_READY	0x02
254 #define	URE_RXFIFO_EMPTY	0x10
255 #define	URE_TXFIFO_EMPTY	0x20
256 #define	URE_NOW_IS_OOB		0x80
257 #define	URE_FIFO_EMPTY		(URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY)
258 
259 /* URE_PLA_MISC_1 */
260 #define	URE_RXDY_GATED_EN	0x0008
261 
262 /* URE_PLA_SFF_STS_7 */
263 #define	URE_MCU_BORW_EN		0x4000
264 #define	URE_RE_INIT_LL		0x8000
265 
266 /* URE_PLA_CPCR */
267 #define	URE_FLOW_CTRL_EN	0x0001
268 #define	URE_CPCR_RX_VLAN	0x0040
269 
270 /* URE_PLA_TEREDO_CFG */
271 #define	URE_TEREDO_SEL			0x8000
272 #define	URE_TEREDO_WAKE_MASK		0x7f00
273 #define	URE_TEREDO_RS_EVENT_MASK	0x00fe
274 #define	URE_OOB_TEREDO_EN		0x0001
275 
276 /* URE_PLA_BDC_CR */
277 #define	URE_ALDPS_PROXY_MODE	0x0001
278 
279 /* URE_PLA_CONFIG34 */
280 #define	URE_LINK_OFF_WAKE_EN	0x0008
281 #define	URE_LINK_ON_WAKE_EN	0x0010
282 
283 /* URE_PLA_CONFIG5 */
284 #define	URE_LAN_WAKE_EN		0x0002
285 
286 /* URE_PLA_LED_FEATURE */
287 #define	URE_LED_MODE_MASK	0x0700
288 
289 /* URE_PLA_PHY_PWR */
290 #define	URE_TX_10M_IDLE_EN	0x0080
291 #define	URE_PFM_PWM_SWITCH	0x0040
292 
293 /* URE_PLA_MAC_PWR_CTRL */
294 #define	URE_D3_CLK_GATED_EN	0x00004000
295 #define	URE_MCU_CLK_RATIO	0x07010f07
296 #define	URE_MCU_CLK_RATIO_MASK	0x0f0f0f0f
297 #define	URE_ALDPS_SPDWN_RATIO	0x0f87
298 
299 /* URE_PLA_MAC_PWR_CTRL2 */
300 #define	URE_MAC_CLK_SPDWN_EN		0x8000
301 #define	URE_EEE_SPDWN_RATIO		0x8007
302 #define	URE_EEE_SPDWN_RATIO_MASK	0x00ff
303 
304 /* URE_PLA_MAC_PWR_CTRL3 */
305 #define	URE_L1_SPDWN_EN		0x0001
306 #define	URE_U1U2_SPDWN_EN	0x0002
307 #define	URE_SUSPEND_SPDWN_EN	0x0004
308 #define	URE_PKT_AVAIL_SPDWN_EN	0x0100
309 #define	URE_PLA_MCU_SPDWN_EN	0x4000
310 
311 /* URE_PLA_MAC_PWR_CTRL4 */
312 #define	URE_EEE_SPDWN_EN	0x0001
313 #define	URE_TP1000_SPDWN_EN	0x0008
314 #define	URE_TP500_SPDWN_EN	0x0010
315 #define	URE_TP100_SPDWN_EN	0x0020
316 #define	URE_IDLE_SPDWN_EN	0x0040
317 #define	URE_TX10MIDLE_EN	0x0100
318 #define	URE_RXDV_SPDWN_EN	0x0800
319 #define	URE_PWRSAVE_SPDWN_EN	0x1000
320 
321 /* URE_PLA_GPHY_INTR_IMR */
322 #define	URE_GPHY_STS_MSK	0x0001
323 #define	URE_SPEED_DOWN_MSK	0x0002
324 #define	URE_SPDWN_RXDV_MSK	0x0004
325 #define	URE_SPDWN_LINKCHG_MSK	0x0008
326 
327 /* URE_PLA_PHYAR */
328 #define	URE_PHYAR_PHYDATA	0x0000ffff
329 #define	URE_PHYAR_BUSY		0x80000000
330 
331 /* URE_PLA_EEE_CR */
332 #define	URE_EEE_RX_EN		0x0001
333 #define	URE_EEE_TX_EN		0x0002
334 
335 /* URE_PLA_BOOT_CTRL */
336 #define	URE_AUTOLOAD_DONE	0x0002
337 
338 /* URE_PLA_LWAKE_CTRL_REG */
339 #define URE_LANWAKE_PIN		0x80
340 
341 /* URE_PLA_SUSPEND_FLAG */
342 #define	URE_LINK_CHG_EVENT	0x01
343 
344 /* URE_PLA_INDICATE_FALG */
345 #define	URE_UPCOMING_RUNTIME_D3	0x01
346 
347 /* URE_PLA_EXTRA_STATUS */
348 #define	URE_POLL_LINK_CHG	0x0001
349 #define	URE_LINK_CHANGE_FLAG	0x0100
350 #define	URE_CUR_LINK_OK		0x8000
351 
352 /* URE_PLA_GPHY_CTRL */
353 #define	URE_GPHY_FLASH		0x0002
354 
355 /* URE_PLA_POL_GPIO_CTRL */
356 #define	URE_DACK_DET_EN		0x8000
357 
358 /* URE_PLA_PHYSTATUS */
359 #define URE_PHYSTATUS_FDX	0x0001
360 #define URE_PHYSTATUS_LINK	0x0002
361 #define URE_PHYSTATUS_10MBPS	0x0004
362 #define URE_PHYSTATUS_100MBPS	0x0008
363 #define URE_PHYSTATUS_1000MBPS	0x0010
364 #define URE_PHYSTATUS_2500MBPS	0x0400
365 
366 /* URE_PLA_CONFIG6 */
367 #define	URE_LANWAKE_CLR_EN	0x01
368 
369 /* URE_USB_USB2PHY */
370 #define	URE_USB2PHY_SUSPEND	0x0001
371 #define	URE_USB2PHY_L1		0x0002
372 
373 /* URE_USB_SSPHYLINK1 */
374 #define	URE_DELAY_PHY_PWR_CHG	0x0002
375 
376 /* URE_USB_SSPHYLINK2 */
377 #define	URE_PWD_DN_SCALE_MASK	0x3ffe
378 #define	URE_PWD_DN_SCALE(x)	((x) << 1)
379 
380 /* URE_USB_CSR_DUMMY1 */
381 #define	URE_DYNAMIC_BURST	0x0001
382 
383 /* URE_USB_CSR_DUMMY2 */
384 #define	URE_EP4_FULL_FC		0x0001
385 
386 /* URE_USB_DEV_STAT */
387 #define	URE_STAT_SPEED_HIGH	0x0000
388 #define	URE_STAT_SPEED_FULL	0x0001
389 #define	URE_STAT_SPEED_MASK	0x0006
390 
391 /* URE_USB_LPM_CONFIG */
392 #define LPM_U1U2_EN		0x0001
393 
394 /* URE_USB_MISC_2 */
395 #define	URE_UPS_FORCE_PWR_DOWN	0x01
396 #define	URE_UPS_NO_UPS		0x80
397 
398 /* URE_USB_ECM_OPTION */
399 #define	URE_BYPASS_MAC_RESET	0x0020
400 
401 /* URE_USB_GPHY_CTRL */
402 #define	URE_GPHY_PATCH_DONE	0x0004
403 #define	URE_BYPASS_FLASH	0x0020
404 
405 /* URE_USB_SPEED_OPTION */
406 #define	URE_RG_PWRDN_EN		0x0100
407 #define	URE_ALL_SPEED_OFF	0x0200
408 
409 /* URE_USB_FW_CTRL */
410 #define	URE_FLOW_CTRL_PATCH_OPT	0x0002
411 #define	URE_AUTO_SPEEDUP	0x0008
412 #define	URE_FLOW_CTRL_PATCH_2	0x0100
413 
414 /* URE_URE_USB_FC_TIMER */
415 #define	URE_CTRL_TIMER_EN	0x8000
416 
417 /* URE_USB_USB_ECM_OP */
418 #define	URE_EN_ALL_SPEED	0x0001
419 
420 /* URE_USB_TX_AGG */
421 #define	URE_TX_AGG_MAX_THRESHOLD	0x03
422 
423 /* URE_USB_RX_BUF_TH */
424 #define	URE_RX_THR_SUPER	0x0c350180
425 #define	URE_RX_THR_HIGH		0x7a120180
426 #define	URE_RX_THR_SLOW		0xffff0180
427 #define	URE_RX_THR_B		0x00010001
428 
429 /* URE_USB_TX_DMA */
430 #define	URE_TEST_MODE_DISABLE	0x00000001
431 #define	URE_TX_SIZE_ADJUST1	0x00000100
432 
433 /* URE_USB_UPT_RXDMA_OWN */
434 #define	URE_OWN_UPDATE		0x01
435 #define	URE_OWN_CLEAR		0x02
436 
437 /* URE_USB_BMU_RESET */
438 #define	BMU_RESET_EP_IN		0x01
439 #define	BMU_RESET_EP_OUT	0x02
440 
441 /* URE_USB_BMU_CONFIG */
442 #define	URE_ACT_ODMA		0x02
443 
444 /* URE_USB_FW_TASK */
445 #define	URE_FC_PATCH_TASK	0x0002
446 
447 /* URE_USB_RX_AGGR_NUM */
448 #define	URE_RX_AGGR_NUM_MASK	0x1ff
449 
450 /* URE_USB_UPS_CTRL */
451 #define	URE_POWER_CUT		0x0100
452 
453 /* URE_USB_PM_CTRL_STATUS */
454 #define	URE_RESUME_INDICATE	0x0001
455 
456 /* URE_USB_USB_CTRL */
457 #define	URE_CDC_ECM_EN		0x0008
458 #define	URE_RX_AGG_DISABLE	0x0010
459 #define	URE_RX_ZERO_EN		0x0080
460 
461 /* URE_USB_U2P3_CTRL */
462 #define	URE_U2P3_ENABLE		0x0001
463 #define	URE_RX_DETECT8		0x0008
464 
465 /* URE_USB_POWER_CUT */
466 #define	URE_PWR_EN		0x0001
467 #define	URE_PHASE2_EN		0x0008
468 #define	URE_UPS_EN		0x0010
469 #define	URE_USP_PREWAKE		0x0020
470 
471 /* URE_USB_MISC_0 */
472 #define	URE_PCUT_STATUS		0x0001
473 
474 /* URE_USB_RX_EARLY_AGG */
475 #define	URE_COALESCE_SUPER	85000U
476 #define	URE_COALESCE_HIGH	250000U
477 #define	URE_COALESCE_SLOW	524280U
478 
479 /* URE_USB_WDT11_CTRL */
480 #define	URE_TIMER11_EN		0x0001
481 
482 /* URE_USB_LPM_CTRL */
483 #define	URE_FIFO_EMPTY_1FB	0x30
484 #define	URE_LPM_TIMER_MASK	0x0c
485 #define	URE_LPM_TIMER_500MS	0x04
486 #define	URE_LPM_TIMER_500US	0x0c
487 #define	URE_ROK_EXIT_LPM	0x02
488 
489 /* URE_USB_AFE_CTRL2 */
490 #define	URE_SEN_VAL_MASK	0xf800
491 #define	URE_SEN_VAL_NORMAL	0xa000
492 #define	URE_SEL_RXIDLE		0x0100
493 
494 /* URE_USB_UPS_FLAGS */
495 #define	URE_UPS_FLAGS_EN_ALDPS	0x00000008
496 #define URE_UPS_FLAGS_MASK	0xffffffff
497 
498 /* URE_OCP_ALDPS_CONFIG */
499 #define	URE_ENPWRSAVE		0x8000
500 #define	URE_ENPDNPS		0x0200
501 #define	URE_LINKENA		0x0100
502 #define	URE_DIS_SDSAVE		0x0010
503 
504 /* URE_OCP_PHY_STATUS */
505 #define	URE_PHY_STAT_MASK	0x0007
506 #define	URE_PHY_STAT_EXT_INIT	2
507 #define	URE_PHY_STAT_LAN_ON	3
508 #define	URE_PHY_STAT_PWRDN	5
509 
510 /* URE_OCP_POWER_CFG */
511 #define	URE_EEE_CLKDIV_EN	0x8000
512 #define	URE_EN_ALDPS		0x0004
513 #define	URE_EN_10M_PLLOFF	0x0001
514 
515 /* URE_OCP_EEE_CFG */
516 #define	URE_CTAP_SHORT_EN	0x0040
517 #define	URE_EEE10_EN		0x0010
518 
519 /* URE_OCP_DOWN_SPEED */
520 #define	URE_EN_10M_BGOFF	0x0080
521 
522 /* URE_OCP_PHY_STATE */
523 #define	URE_TXDIS_STATE		0x01
524 #define	URE_ABD_STATE		0x02
525 
526 /* URE_OCP_ADC_CFG */
527 #define	URE_EN_EMI_L		0x0040
528 #define	URE_ADC_EN		0x0080
529 #define	URE_CKADSEL_L		0x0100
530 
531 #define URE_ADV_2500TFDX	0x0080
532 
533 #define	URE_MCU_TYPE_PLA	0x0100
534 #define	URE_MCU_TYPE_USB	0x0000
535 
536 #define	GET_MII(sc)		uether_getmii(&(sc)->sc_ue)
537 
538 struct ure_intrpkt {
539 	uint8_t	ure_tsr;
540 	uint8_t	ure_rsr;
541 	uint8_t	ure_gep_msr;
542 	uint8_t	ure_waksr;
543 	uint8_t	ure_txok_cnt;
544 	uint8_t	ure_rxlost_cnt;
545 	uint8_t	ure_crcerr_cnt;
546 	uint8_t	ure_col_cnt;
547 } __packed;
548 
549 struct ure_rxpkt {
550 	uint32_t ure_pktlen;
551 #define	URE_RXPKT_LEN_MASK	0x7fff
552 	uint32_t ure_vlan;
553 #define	URE_RXPKT_UDP		(1 << 23)
554 #define	URE_RXPKT_TCP		(1 << 22)
555 #define	URE_RXPKT_IPV6		(1 << 20)
556 #define	URE_RXPKT_IPV4		(1 << 19)
557 #define	URE_RXPKT_VLAN_TAG	(1 << 16)
558 #define	URE_RXPKT_VLAN_DATA	0xffff
559 	uint32_t ure_csum;
560 #define	URE_RXPKT_IPSUMBAD	(1 << 23)
561 #define	URE_RXPKT_UDPSUMBAD	(1 << 22)
562 #define	URE_RXPKT_TCPSUMBAD	(1 << 21)
563 	uint32_t ure_rsvd2;
564 	uint32_t ure_rsvd3;
565 	uint32_t ure_rsvd4;
566 } __packed;
567 
568 struct ure_txpkt {
569 	uint32_t ure_pktlen;
570 #define	URE_TXPKT_TX_FS		(1U << 31)
571 #define	URE_TXPKT_TX_LS		(1 << 30)
572 #define	URE_TXPKT_LEN_MASK	0xffff
573 	uint32_t ure_vlan;
574 #define	URE_TXPKT_UDP		(1U << 31)
575 #define	URE_TXPKT_TCP		(1 << 30)
576 #define	URE_TXPKT_IPV4		(1 << 29)
577 #define	URE_TXPKT_IPV6		(1 << 28)
578 #define	URE_TXPKT_VLAN_TAG	(1 << 16)
579 } __packed;
580 
581 #define URE_ENDPT_RX		0
582 #define URE_ENDPT_TX		1
583 #define URE_ENDPT_MAX		2
584 
585 #define	URE_TX_LIST_CNT		1
586 #define	URE_RX_LIST_CNT		1
587 #define	URE_TX_BUF_ALIGN	4
588 #define	URE_RX_BUF_ALIGN	8
589 
590 #define	URE_TX_BUFSZ		16384
591 #define	URE_8152_RX_BUFSZ	16384
592 #define	URE_8153_RX_BUFSZ	32768
593 
594 struct ure_chain {
595 	struct ure_softc	*uc_sc;
596 	struct usbd_xfer	*uc_xfer;
597 	char			*uc_buf;
598 	uint32_t		uc_cnt;
599 	uint32_t		uc_buflen;
600 	uint32_t		uc_bufmax;
601 	SLIST_ENTRY(ure_chain)  uc_list;
602 	uint8_t			uc_idx;
603 };
604 
605 struct ure_cdata {
606 	struct ure_chain	ure_rx_chain[URE_RX_LIST_CNT];
607 	struct ure_chain	ure_tx_chain[URE_TX_LIST_CNT];
608 	SLIST_HEAD(ure_list_head, ure_chain)    ure_tx_free;
609 };
610 
611 struct ure_softc {
612 	struct device		ure_dev;
613 	struct usbd_device	*ure_udev;
614 
615 	/* usb */
616 	struct usbd_interface	*ure_iface;
617 	struct usb_task		ure_tick_task;
618 	int			ure_ed[URE_ENDPT_MAX];
619 	struct usbd_pipe	*ure_ep[URE_ENDPT_MAX];
620 
621 	/* ethernet */
622 	struct arpcom		ure_ac;
623 	struct mii_data		ure_mii;
624 	struct ifmedia		ure_ifmedia;
625 	struct rwlock		ure_mii_lock;
626 	int			ure_refcnt;
627 
628 	struct ure_cdata	ure_cdata;
629 	struct timeout		ure_stat_ch;
630 
631 	struct timeval		ure_rx_notice;
632 	int			ure_rxbufsz;
633 	int			ure_txbufsz;
634 
635 	int			ure_phyno;
636 
637 	u_int			ure_flags;
638 #define	URE_FLAG_LINK		0x0001
639 #define	URE_FLAG_8152		0x1000	/* RTL8152 */
640 #define	URE_FLAG_8153B		0x2000	/* RTL8153B */
641 #define	URE_FLAG_8156		0x4000	/* RTL8156 */
642 #define	URE_FLAG_8156B		0x8000	/* RTL8156B */
643 
644 	u_int			ure_chip;
645 #define	URE_CHIP_VER_4C00	0x01
646 #define	URE_CHIP_VER_4C10	0x02
647 #define	URE_CHIP_VER_5C00	0x04
648 #define	URE_CHIP_VER_5C10	0x08
649 #define	URE_CHIP_VER_5C20	0x10
650 #define	URE_CHIP_VER_5C30	0x20
651 #define	URE_CHIP_VER_6010	0x40
652 #define	URE_CHIP_VER_7420	0x80
653 };
654