1 /* $OpenBSD: if_urtwn.c,v 1.112 2024/10/22 22:21:25 jsg Exp $ */
2
3 /*-
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188FTV/RTL8188RU/
23 * RTL8192CU/RTL8192EU.
24 */
25
26 #include "bpfilter.h"
27
28 #include <sys/param.h>
29 #include <sys/mbuf.h>
30 #include <sys/systm.h>
31 #include <sys/timeout.h>
32 #include <sys/device.h>
33 #include <sys/endian.h>
34
35 #include <machine/bus.h>
36 #include <machine/intr.h>
37
38 #if NBPFILTER > 0
39 #include <net/bpf.h>
40 #endif
41 #include <net/if.h>
42 #include <net/if_media.h>
43
44 #include <netinet/in.h>
45 #include <netinet/if_ether.h>
46
47 #include <net80211/ieee80211_var.h>
48 #include <net80211/ieee80211_amrr.h>
49 #include <net80211/ieee80211_radiotap.h>
50
51 #include <dev/usb/usb.h>
52 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usbdivar.h>
54 #include <dev/usb/usbdevs.h>
55
56 #include <dev/ic/r92creg.h>
57 #include <dev/ic/rtwnvar.h>
58
59 /* Maximum number of output pipes is 3. */
60 #define R92C_MAX_EPOUT 3
61
62 #define R92C_HQ_NPAGES 12
63 #define R92C_LQ_NPAGES 2
64 #define R92C_NQ_NPAGES 2
65 #define R92C_TXPKTBUF_COUNT 256
66 #define R92C_TX_PAGE_COUNT 248
67 #define R92C_MAX_RX_DMA_SIZE 0x2800
68
69 #define R88E_HQ_NPAGES 0
70 #define R88E_LQ_NPAGES 9
71 #define R88E_NQ_NPAGES 0
72 #define R88E_TXPKTBUF_COUNT 177
73 #define R88E_TX_PAGE_COUNT 168
74 #define R88E_MAX_RX_DMA_SIZE 0x2400
75
76 #define R88F_HQ_NPAGES 12
77 #define R88F_LQ_NPAGES 2
78 #define R88F_NQ_NPAGES 2
79 #define R88F_TXPKTBUF_COUNT 177
80 #define R88F_TX_PAGE_COUNT 247
81 #define R88F_MAX_RX_DMA_SIZE 0x3f80
82
83 #define R92E_HQ_NPAGES 16
84 #define R92E_LQ_NPAGES 16
85 #define R92E_NQ_NPAGES 16
86 #define R92E_TX_PAGE_COUNT 248
87 #define R92E_MAX_RX_DMA_SIZE 0x3fc0
88
89 #define R92C_TXDESC_SUMSIZE 32
90 #define R92C_TXDESC_SUMOFFSET 14
91
92 /* USB Requests. */
93 #define R92C_REQ_REGS 0x05
94
95 /*
96 * Driver definitions.
97 */
98 #define URTWN_RX_LIST_COUNT 1
99 #define URTWN_TX_LIST_COUNT 8
100 #define URTWN_HOST_CMD_RING_COUNT 32
101
102 #define URTWN_RXBUFSZ (16 * 1024)
103 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN)
104
105 #define URTWN_RIDX_COUNT 28
106
107 #define URTWN_TX_TIMEOUT 5000 /* ms */
108
109 #define URTWN_LED_LINK 0
110 #define URTWN_LED_DATA 1
111
112 struct urtwn_rx_radiotap_header {
113 struct ieee80211_radiotap_header wr_ihdr;
114 uint8_t wr_flags;
115 uint8_t wr_rate;
116 uint16_t wr_chan_freq;
117 uint16_t wr_chan_flags;
118 uint8_t wr_dbm_antsignal;
119 } __packed;
120
121 #define URTWN_RX_RADIOTAP_PRESENT \
122 (1 << IEEE80211_RADIOTAP_FLAGS | \
123 1 << IEEE80211_RADIOTAP_RATE | \
124 1 << IEEE80211_RADIOTAP_CHANNEL | \
125 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
126
127 struct urtwn_tx_radiotap_header {
128 struct ieee80211_radiotap_header wt_ihdr;
129 uint8_t wt_flags;
130 uint16_t wt_chan_freq;
131 uint16_t wt_chan_flags;
132 } __packed;
133
134 #define URTWN_TX_RADIOTAP_PRESENT \
135 (1 << IEEE80211_RADIOTAP_FLAGS | \
136 1 << IEEE80211_RADIOTAP_CHANNEL)
137
138 struct urtwn_softc;
139
140 struct urtwn_rx_data {
141 struct urtwn_softc *sc;
142 struct usbd_xfer *xfer;
143 uint8_t *buf;
144 };
145
146 struct urtwn_tx_data {
147 struct urtwn_softc *sc;
148 struct usbd_pipe *pipe;
149 struct usbd_xfer *xfer;
150 uint8_t *buf;
151 TAILQ_ENTRY(urtwn_tx_data) next;
152 };
153
154 struct urtwn_host_cmd {
155 void (*cb)(struct urtwn_softc *, void *);
156 uint8_t data[256];
157 };
158
159 struct urtwn_cmd_newstate {
160 enum ieee80211_state state;
161 int arg;
162 };
163
164 struct urtwn_cmd_key {
165 struct ieee80211_key key;
166 struct ieee80211_node *ni;
167 };
168
169 struct urtwn_host_cmd_ring {
170 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT];
171 int cur;
172 int next;
173 int queued;
174 };
175
176 struct urtwn_softc {
177 struct device sc_dev;
178 struct rtwn_softc sc_sc;
179
180 struct usbd_device *sc_udev;
181 struct usbd_interface *sc_iface;
182 struct usb_task sc_task;
183
184 struct timeout scan_to;
185 struct timeout calib_to;
186
187 int ntx;
188 struct usbd_pipe *rx_pipe;
189 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT];
190 int ac2idx[EDCA_NUM_AC];
191
192 struct urtwn_host_cmd_ring cmdq;
193 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT];
194 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT];
195 TAILQ_HEAD(, urtwn_tx_data) tx_free_list;
196
197 struct ieee80211_amrr amrr;
198 struct ieee80211_amrr_node amn;
199
200 #if NBPFILTER > 0
201 caddr_t sc_drvbpf;
202
203 union {
204 struct urtwn_rx_radiotap_header th;
205 uint8_t pad[64];
206 } sc_rxtapu;
207 #define sc_rxtap sc_rxtapu.th
208 int sc_rxtap_len;
209
210 union {
211 struct urtwn_tx_radiotap_header th;
212 uint8_t pad[64];
213 } sc_txtapu;
214 #define sc_txtap sc_txtapu.th
215 int sc_txtap_len;
216 #endif
217 int sc_key_tasks;
218 };
219
220 #ifdef URTWN_DEBUG
221 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0)
222 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0)
223 int urtwn_debug = 4;
224 #else
225 #define DPRINTF(x)
226 #define DPRINTFN(n, x)
227 #endif
228
229 /*
230 * Various supported device vendors/products.
231 */
232 #define URTWN_DEV(v, p, f) \
233 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB }
234 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C)
235 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E)
236 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E)
237 #define URTWN_DEV_8188F(v, p) URTWN_DEV(v, p, RTWN_CHIP_88F)
238 static const struct urtwn_type {
239 struct usb_devno dev;
240 uint32_t chip;
241 } urtwn_devs[] = {
242 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1),
243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2),
244 URTWN_DEV_8192CU(ABOCOM, RTL8192CU),
245 URTWN_DEV_8192CU(ASUS, RTL8192CU),
246 URTWN_DEV_8192CU(ASUS, RTL8192CU_2),
247 URTWN_DEV_8192CU(ASUS, RTL8192CU_3),
248 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1),
249 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2),
250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU),
251 URTWN_DEV_8192CU(BELKIN, F7D2102),
252 URTWN_DEV_8192CU(BELKIN, F9L1004V1),
253 URTWN_DEV_8192CU(BELKIN, RTL8188CU),
254 URTWN_DEV_8192CU(BELKIN, RTL8188CUS),
255 URTWN_DEV_8192CU(BELKIN, RTL8192CU),
256 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1),
257 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1),
258 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2),
259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3),
260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4),
261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5),
262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6),
263 URTWN_DEV_8192CU(COMPARE, RTL8192CU),
264 URTWN_DEV_8192CU(COREGA, RTL8192CU),
265 URTWN_DEV_8192CU(DLINK, DWA131B),
266 URTWN_DEV_8192CU(DLINK, RTL8188CU),
267 URTWN_DEV_8192CU(DLINK, RTL8192CU_1),
268 URTWN_DEV_8192CU(DLINK, RTL8192CU_2),
269 URTWN_DEV_8192CU(DLINK, RTL8192CU_3),
270 URTWN_DEV_8192CU(DLINK, RTL8192CU_4),
271 URTWN_DEV_8192CU(EDIMAX, EW7811UN),
272 URTWN_DEV_8192CU(EDIMAX, RTL8192CU),
273 URTWN_DEV_8192CU(FEIXUN, RTL8188CU),
274 URTWN_DEV_8192CU(FEIXUN, RTL8192CU),
275 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150),
276 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU),
277 URTWN_DEV_8192CU(HAWKING, RTL8192CU),
278 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2),
279 URTWN_DEV_8192CU(HP3, RTL8188CU),
280 URTWN_DEV_8192CU(IODATA, WNG150UM),
281 URTWN_DEV_8192CU(IODATA, RTL8192CU),
282 URTWN_DEV_8192CU(NETGEAR, N300MA),
283 URTWN_DEV_8192CU(NETGEAR, WNA1000M),
284 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2),
285 URTWN_DEV_8192CU(NETGEAR, RTL8192CU),
286 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU),
287 URTWN_DEV_8192CU(NETWEEN, RTL8192CU),
288 URTWN_DEV_8192CU(NOVATECH, RTL8188CU),
289 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1),
290 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2),
291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3),
292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4),
293 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS),
294 URTWN_DEV_8192CU(PLANEX2, RTL8192CU),
295 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0),
296 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1),
297 URTWN_DEV_8192CU(REALTEK, RTL8188CTV),
298 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0),
299 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1),
300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2),
301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3),
302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4),
303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5),
304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO),
305 URTWN_DEV_8192CU(REALTEK, RTL8188CUS),
306 URTWN_DEV_8192CU(REALTEK, RTL8188RU),
307 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2),
308 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3),
309 URTWN_DEV_8192CU(REALTEK, RTL8191CU),
310 URTWN_DEV_8192CU(REALTEK, RTL8192CE),
311 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU),
312 URTWN_DEV_8192CU(REALTEK, RTL8192CU),
313 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU),
314 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2),
315 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU),
316 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2),
317 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2),
318 URTWN_DEV_8192CU(TPLINK, RTL8192CU),
319 URTWN_DEV_8192CU(TRENDNET, RTL8188CU),
320 URTWN_DEV_8192CU(TRENDNET, RTL8192CU),
321 URTWN_DEV_8192CU(ZYXEL, RTL8192CU),
322 /* URTWN_RTL8188E */
323 URTWN_DEV_8188EU(ABOCOM, RTL8188EU),
324 URTWN_DEV_8188EU(DLINK, DWA121B1),
325 URTWN_DEV_8188EU(DLINK, DWA123D1),
326 URTWN_DEV_8188EU(DLINK, DWA125D1),
327 URTWN_DEV_8188EU(EDIMAX, EW7811UNV2),
328 URTWN_DEV_8188EU(ELECOM, WDC150SU2M),
329 URTWN_DEV_8188EU(MERCUSYS, MW150USV2),
330 URTWN_DEV_8188EU(REALTEK, RTL8188ETV),
331 URTWN_DEV_8188EU(REALTEK, RTL8188EU),
332 URTWN_DEV_8188EU(TPLINK, RTL8188EUS),
333 URTWN_DEV_8188EU(ASUS, RTL8188EUS),
334 /* URTWN_RTL8188FTV */
335 URTWN_DEV_8188F(REALTEK, RTL8188FTV),
336
337 /* URTWN_RTL8192EU */
338 URTWN_DEV_8192EU(DLINK, DWA131E1),
339 URTWN_DEV_8192EU(REALTEK, RTL8192EU),
340 URTWN_DEV_8192EU(REALTEK, RTL8192EU_2),
341 URTWN_DEV_8192EU(TPLINK, RTL8192EU),
342 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2),
343 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3)
344 };
345
346 #define urtwn_lookup(v, p) \
347 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p))
348
349 int urtwn_match(struct device *, void *, void *);
350 void urtwn_attach(struct device *, struct device *, void *);
351 int urtwn_detach(struct device *, int);
352 int urtwn_open_pipes(struct urtwn_softc *);
353 void urtwn_close_pipes(struct urtwn_softc *);
354 int urtwn_alloc_rx_list(struct urtwn_softc *);
355 void urtwn_free_rx_list(struct urtwn_softc *);
356 int urtwn_alloc_tx_list(struct urtwn_softc *);
357 void urtwn_free_tx_list(struct urtwn_softc *);
358 void urtwn_task(void *);
359 void urtwn_do_async(struct urtwn_softc *,
360 void (*)(struct urtwn_softc *, void *), void *, int);
361 void urtwn_wait_async(void *);
362 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
363 int);
364 void urtwn_write_1(void *, uint16_t, uint8_t);
365 void urtwn_write_2(void *, uint16_t, uint16_t);
366 void urtwn_write_4(void *, uint16_t, uint32_t);
367 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *,
368 int);
369 uint8_t urtwn_read_1(void *, uint16_t);
370 uint16_t urtwn_read_2(void *, uint16_t);
371 uint32_t urtwn_read_4(void *, uint16_t);
372 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t);
373 void urtwn_calib_to(void *);
374 void urtwn_calib_cb(struct urtwn_softc *, void *);
375 void urtwn_scan_to(void *);
376 void urtwn_next_scan(void *);
377 void urtwn_cancel_scan(void *);
378 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state,
379 int);
380 void urtwn_newstate_cb(struct urtwn_softc *, void *);
381 void urtwn_updateslot(struct ieee80211com *);
382 void urtwn_updateslot_cb(struct urtwn_softc *, void *);
383 void urtwn_updateedca(struct ieee80211com *);
384 void urtwn_updateedca_cb(struct urtwn_softc *, void *);
385 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *,
386 struct ieee80211_key *);
387 void urtwn_set_key_cb(struct urtwn_softc *, void *);
388 void urtwn_delete_key(struct ieee80211com *,
389 struct ieee80211_node *, struct ieee80211_key *);
390 void urtwn_delete_key_cb(struct urtwn_softc *, void *);
391 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int,
392 struct mbuf_list *);
393 void urtwn_rxeof(struct usbd_xfer *, void *,
394 usbd_status);
395 void urtwn_txeof(struct usbd_xfer *, void *,
396 usbd_status);
397 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *);
398 int urtwn_ioctl(struct ifnet *, u_long, caddr_t);
399 int urtwn_power_on(void *);
400 int urtwn_alloc_buffers(void *);
401 int urtwn_r92c_power_on(struct urtwn_softc *);
402 int urtwn_r92e_power_on(struct urtwn_softc *);
403 int urtwn_r88e_power_on(struct urtwn_softc *);
404 int urtwn_r88f_power_on(struct urtwn_softc *);
405 int urtwn_llt_init(struct urtwn_softc *, int);
406 int urtwn_fw_loadpage(void *, int, uint8_t *, int);
407 int urtwn_load_firmware(void *, u_char **, size_t *);
408 int urtwn_dma_init(void *);
409 void urtwn_aggr_init(void *);
410 void urtwn_mac_init(void *);
411 void urtwn_bb_init(void *);
412 void urtwn_burstlen_init(struct urtwn_softc *);
413 int urtwn_init(void *);
414 void urtwn_stop(void *);
415 int urtwn_is_oactive(void *);
416 void urtwn_next_calib(void *);
417 void urtwn_cancel_calib(void *);
418
419 /* Aliases. */
420 #define urtwn_bb_write urtwn_write_4
421 #define urtwn_bb_read urtwn_read_4
422
423 struct cfdriver urtwn_cd = {
424 NULL, "urtwn", DV_IFNET
425 };
426
427 const struct cfattach urtwn_ca = {
428 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach
429 };
430
431 int
urtwn_match(struct device * parent,void * match,void * aux)432 urtwn_match(struct device *parent, void *match, void *aux)
433 {
434 struct usb_attach_arg *uaa = aux;
435
436 if (uaa->iface == NULL || uaa->configno != 1)
437 return (UMATCH_NONE);
438
439 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ?
440 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE);
441 }
442
443 void
urtwn_attach(struct device * parent,struct device * self,void * aux)444 urtwn_attach(struct device *parent, struct device *self, void *aux)
445 {
446 struct urtwn_softc *sc = (struct urtwn_softc *)self;
447 struct usb_attach_arg *uaa = aux;
448 struct ifnet *ifp;
449 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
450
451 sc->sc_udev = uaa->device;
452 sc->sc_iface = uaa->iface;
453
454 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip;
455
456 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC);
457 timeout_set(&sc->scan_to, urtwn_scan_to, sc);
458 timeout_set(&sc->calib_to, urtwn_calib_to, sc);
459 if (urtwn_open_pipes(sc) != 0)
460 return;
461
462 sc->amrr.amrr_min_success_threshold = 1;
463 sc->amrr.amrr_max_success_threshold = 10;
464
465 /* Attach the bus-agnostic driver. */
466 sc->sc_sc.sc_ops.cookie = sc;
467 sc->sc_sc.sc_ops.write_1 = urtwn_write_1;
468 sc->sc_sc.sc_ops.write_2 = urtwn_write_2;
469 sc->sc_sc.sc_ops.write_4 = urtwn_write_4;
470 sc->sc_sc.sc_ops.read_1 = urtwn_read_1;
471 sc->sc_sc.sc_ops.read_2 = urtwn_read_2;
472 sc->sc_sc.sc_ops.read_4 = urtwn_read_4;
473 sc->sc_sc.sc_ops.tx = urtwn_tx;
474 sc->sc_sc.sc_ops.power_on = urtwn_power_on;
475 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init;
476 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage;
477 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware;
478 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init;
479 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init;
480 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init;
481 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers;
482 sc->sc_sc.sc_ops.init = urtwn_init;
483 sc->sc_sc.sc_ops.stop = urtwn_stop;
484 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive;
485 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib;
486 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib;
487 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan;
488 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan;
489 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async;
490 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) {
491 urtwn_close_pipes(sc);
492 return;
493 }
494
495 /* ifp is now valid */
496 ifp = &sc->sc_sc.sc_ic.ic_if;
497 ifp->if_ioctl = urtwn_ioctl;
498
499 ic->ic_updateslot = urtwn_updateslot;
500 ic->ic_updateedca = urtwn_updateedca;
501 ic->ic_set_key = urtwn_set_key;
502 ic->ic_delete_key = urtwn_delete_key;
503 /* Override state transition machine. */
504 ic->ic_newstate = urtwn_newstate;
505
506 #if NBPFILTER > 0
507 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO,
508 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN);
509
510 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
511 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
512 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT);
513
514 sc->sc_txtap_len = sizeof(sc->sc_txtapu);
515 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
516 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT);
517 #endif
518 }
519
520 int
urtwn_detach(struct device * self,int flags)521 urtwn_detach(struct device *self, int flags)
522 {
523 struct urtwn_softc *sc = (struct urtwn_softc *)self;
524 int s;
525
526 s = splusb();
527
528 if (timeout_initialized(&sc->scan_to))
529 timeout_del(&sc->scan_to);
530 if (timeout_initialized(&sc->calib_to))
531 timeout_del(&sc->calib_to);
532
533 /* Wait for all async commands to complete. */
534 usb_rem_wait_task(sc->sc_udev, &sc->sc_task);
535
536 usbd_ref_wait(sc->sc_udev);
537
538 rtwn_detach(&sc->sc_sc, flags);
539
540 /* Abort and close Tx/Rx pipes. */
541 urtwn_close_pipes(sc);
542
543 /* Free Tx/Rx buffers. */
544 urtwn_free_tx_list(sc);
545 urtwn_free_rx_list(sc);
546 splx(s);
547
548 return (0);
549 }
550
551 int
urtwn_open_pipes(struct urtwn_softc * sc)552 urtwn_open_pipes(struct urtwn_softc *sc)
553 {
554 /* Bulk-out endpoints addresses (from highest to lowest prio). */
555 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 };
556 uint8_t rx_no;
557 usb_interface_descriptor_t *id;
558 usb_endpoint_descriptor_t *ed;
559 int i, error, nrx = 0;
560
561 /* Find all bulk endpoints. */
562 id = usbd_get_interface_descriptor(sc->sc_iface);
563 for (i = 0; i < id->bNumEndpoints; i++) {
564 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i);
565 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK)
566 continue;
567
568 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) {
569 rx_no = ed->bEndpointAddress;
570 nrx++;
571 } else {
572 if (sc->ntx < R92C_MAX_EPOUT)
573 epaddr[sc->ntx] = ed->bEndpointAddress;
574 sc->ntx++;
575 }
576 }
577 if (nrx == 0) {
578 printf("%s: %d: invalid number of Rx bulk pipes\n",
579 sc->sc_dev.dv_xname, nrx);
580 return (EIO);
581 }
582 DPRINTF(("found %d bulk-out pipes\n", sc->ntx));
583 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) {
584 printf("%s: %d: invalid number of Tx bulk pipes\n",
585 sc->sc_dev.dv_xname, sc->ntx);
586 return (EIO);
587 }
588
589 /* Open bulk-in pipe. */
590 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe);
591 if (error != 0) {
592 printf("%s: could not open Rx bulk pipe\n",
593 sc->sc_dev.dv_xname);
594 goto fail;
595 }
596
597 /* Open bulk-out pipes (up to 3). */
598 for (i = 0; i < sc->ntx; i++) {
599 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0,
600 &sc->tx_pipe[i]);
601 if (error != 0) {
602 printf("%s: could not open Tx bulk pipe 0x%02x\n",
603 sc->sc_dev.dv_xname, epaddr[i]);
604 goto fail;
605 }
606 }
607
608 /* Map 802.11 access categories to USB pipes. */
609 sc->ac2idx[EDCA_AC_BK] =
610 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0);
611 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0;
612 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */
613
614 if (error != 0)
615 fail: urtwn_close_pipes(sc);
616 return (error);
617 }
618
619 void
urtwn_close_pipes(struct urtwn_softc * sc)620 urtwn_close_pipes(struct urtwn_softc *sc)
621 {
622 int i;
623
624 /* Close Rx pipe. */
625 if (sc->rx_pipe != NULL) {
626 usbd_close_pipe(sc->rx_pipe);
627 sc->rx_pipe = NULL;
628 }
629 /* Close Tx pipes. */
630 for (i = 0; i < R92C_MAX_EPOUT; i++) {
631 if (sc->tx_pipe[i] == NULL)
632 continue;
633 usbd_close_pipe(sc->tx_pipe[i]);
634 sc->tx_pipe[i] = NULL;
635 }
636 }
637
638 int
urtwn_alloc_rx_list(struct urtwn_softc * sc)639 urtwn_alloc_rx_list(struct urtwn_softc *sc)
640 {
641 struct urtwn_rx_data *data;
642 int i, error = 0;
643
644 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) {
645 data = &sc->rx_data[i];
646
647 data->sc = sc; /* Backpointer for callbacks. */
648
649 data->xfer = usbd_alloc_xfer(sc->sc_udev);
650 if (data->xfer == NULL) {
651 printf("%s: could not allocate xfer\n",
652 sc->sc_dev.dv_xname);
653 error = ENOMEM;
654 break;
655 }
656 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ);
657 if (data->buf == NULL) {
658 printf("%s: could not allocate xfer buffer\n",
659 sc->sc_dev.dv_xname);
660 error = ENOMEM;
661 break;
662 }
663 }
664 if (error != 0)
665 urtwn_free_rx_list(sc);
666 return (error);
667 }
668
669 void
urtwn_free_rx_list(struct urtwn_softc * sc)670 urtwn_free_rx_list(struct urtwn_softc *sc)
671 {
672 int i;
673
674 /* NB: Caller must abort pipe first. */
675 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) {
676 if (sc->rx_data[i].xfer != NULL)
677 usbd_free_xfer(sc->rx_data[i].xfer);
678 sc->rx_data[i].xfer = NULL;
679 }
680 }
681
682 int
urtwn_alloc_tx_list(struct urtwn_softc * sc)683 urtwn_alloc_tx_list(struct urtwn_softc *sc)
684 {
685 struct urtwn_tx_data *data;
686 int i, error = 0;
687
688 TAILQ_INIT(&sc->tx_free_list);
689 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) {
690 data = &sc->tx_data[i];
691
692 data->sc = sc; /* Backpointer for callbacks. */
693
694 data->xfer = usbd_alloc_xfer(sc->sc_udev);
695 if (data->xfer == NULL) {
696 printf("%s: could not allocate xfer\n",
697 sc->sc_dev.dv_xname);
698 error = ENOMEM;
699 break;
700 }
701 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ);
702 if (data->buf == NULL) {
703 printf("%s: could not allocate xfer buffer\n",
704 sc->sc_dev.dv_xname);
705 error = ENOMEM;
706 break;
707 }
708 /* Append this Tx buffer to our free list. */
709 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next);
710 }
711 if (error != 0)
712 urtwn_free_tx_list(sc);
713 return (error);
714 }
715
716 void
urtwn_free_tx_list(struct urtwn_softc * sc)717 urtwn_free_tx_list(struct urtwn_softc *sc)
718 {
719 int i;
720
721 /* NB: Caller must abort pipe first. */
722 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) {
723 if (sc->tx_data[i].xfer != NULL)
724 usbd_free_xfer(sc->tx_data[i].xfer);
725 sc->tx_data[i].xfer = NULL;
726 }
727 }
728
729 void
urtwn_task(void * arg)730 urtwn_task(void *arg)
731 {
732 struct urtwn_softc *sc = arg;
733 struct urtwn_host_cmd_ring *ring = &sc->cmdq;
734 struct urtwn_host_cmd *cmd;
735 int s;
736
737 /* Process host commands. */
738 s = splusb();
739 while (ring->next != ring->cur) {
740 cmd = &ring->cmd[ring->next];
741 splx(s);
742 /* Invoke callback. */
743 cmd->cb(sc, cmd->data);
744 s = splusb();
745 ring->queued--;
746 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT;
747 }
748 splx(s);
749 }
750
751 void
urtwn_do_async(struct urtwn_softc * sc,void (* cb)(struct urtwn_softc *,void *),void * arg,int len)752 urtwn_do_async(struct urtwn_softc *sc,
753 void (*cb)(struct urtwn_softc *, void *), void *arg, int len)
754 {
755 struct urtwn_host_cmd_ring *ring = &sc->cmdq;
756 struct urtwn_host_cmd *cmd;
757 int s;
758
759 s = splusb();
760 cmd = &ring->cmd[ring->cur];
761 cmd->cb = cb;
762 KASSERT(len <= sizeof(cmd->data));
763 memcpy(cmd->data, arg, len);
764 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT;
765
766 /* If there is no pending command already, schedule a task. */
767 if (++ring->queued == 1)
768 usb_add_task(sc->sc_udev, &sc->sc_task);
769 splx(s);
770 }
771
772 void
urtwn_wait_async(void * cookie)773 urtwn_wait_async(void *cookie)
774 {
775 struct urtwn_softc *sc = cookie;
776 int s;
777
778 s = splusb();
779 /* Wait for all queued asynchronous commands to complete. */
780 usb_wait_task(sc->sc_udev, &sc->sc_task);
781 splx(s);
782 }
783
784 int
urtwn_write_region_1(struct urtwn_softc * sc,uint16_t addr,uint8_t * buf,int len)785 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
786 int len)
787 {
788 usb_device_request_t req;
789
790 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
791 req.bRequest = R92C_REQ_REGS;
792 USETW(req.wValue, addr);
793 USETW(req.wIndex, 0);
794 USETW(req.wLength, len);
795 return (usbd_do_request(sc->sc_udev, &req, buf));
796 }
797
798 void
urtwn_write_1(void * cookie,uint16_t addr,uint8_t val)799 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val)
800 {
801 struct urtwn_softc *sc = cookie;
802
803 urtwn_write_region_1(sc, addr, &val, 1);
804 }
805
806 void
urtwn_write_2(void * cookie,uint16_t addr,uint16_t val)807 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val)
808 {
809 struct urtwn_softc *sc = cookie;
810
811 val = htole16(val);
812 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
813 }
814
815 void
urtwn_write_4(void * cookie,uint16_t addr,uint32_t val)816 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val)
817 {
818 struct urtwn_softc *sc = cookie;
819
820 val = htole32(val);
821 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
822 }
823
824 int
urtwn_read_region_1(struct urtwn_softc * sc,uint16_t addr,uint8_t * buf,int len)825 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
826 int len)
827 {
828 usb_device_request_t req;
829
830 req.bmRequestType = UT_READ_VENDOR_DEVICE;
831 req.bRequest = R92C_REQ_REGS;
832 USETW(req.wValue, addr);
833 USETW(req.wIndex, 0);
834 USETW(req.wLength, len);
835 return (usbd_do_request(sc->sc_udev, &req, buf));
836 }
837
838 uint8_t
urtwn_read_1(void * cookie,uint16_t addr)839 urtwn_read_1(void *cookie, uint16_t addr)
840 {
841 struct urtwn_softc *sc = cookie;
842 uint8_t val;
843
844 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
845 return (0xff);
846 return (val);
847 }
848
849 uint16_t
urtwn_read_2(void * cookie,uint16_t addr)850 urtwn_read_2(void *cookie, uint16_t addr)
851 {
852 struct urtwn_softc *sc = cookie;
853 uint16_t val;
854
855 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
856 return (0xffff);
857 return (letoh16(val));
858 }
859
860 uint32_t
urtwn_read_4(void * cookie,uint16_t addr)861 urtwn_read_4(void *cookie, uint16_t addr)
862 {
863 struct urtwn_softc *sc = cookie;
864 uint32_t val;
865
866 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
867 return (0xffffffff);
868 return (letoh32(val));
869 }
870
871 int
urtwn_llt_write(struct urtwn_softc * sc,uint32_t addr,uint32_t data)872 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
873 {
874 int ntries;
875
876 urtwn_write_4(sc, R92C_LLT_INIT,
877 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
878 SM(R92C_LLT_INIT_ADDR, addr) |
879 SM(R92C_LLT_INIT_DATA, data));
880 /* Wait for write operation to complete. */
881 for (ntries = 0; ntries < 20; ntries++) {
882 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
883 R92C_LLT_INIT_OP_NO_ACTIVE)
884 return (0);
885 DELAY(5);
886 }
887 return (ETIMEDOUT);
888 }
889
890 void
urtwn_calib_to(void * arg)891 urtwn_calib_to(void *arg)
892 {
893 struct urtwn_softc *sc = arg;
894
895 if (usbd_is_dying(sc->sc_udev))
896 return;
897
898 usbd_ref_incr(sc->sc_udev);
899
900 /* Do it in a process context. */
901 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0);
902
903 usbd_ref_decr(sc->sc_udev);
904 }
905
906 void
urtwn_calib_cb(struct urtwn_softc * sc,void * arg)907 urtwn_calib_cb(struct urtwn_softc *sc, void *arg)
908 {
909 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
910 int s;
911
912 s = splnet();
913 if (ic->ic_opmode == IEEE80211_M_STA) {
914 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn);
915 }
916 splx(s);
917
918 rtwn_calib(&sc->sc_sc);
919 }
920
921 void
urtwn_next_calib(void * cookie)922 urtwn_next_calib(void *cookie)
923 {
924 struct urtwn_softc *sc = cookie;
925
926 if (!usbd_is_dying(sc->sc_udev))
927 timeout_add_sec(&sc->calib_to, 2);
928 }
929
930 void
urtwn_cancel_calib(void * cookie)931 urtwn_cancel_calib(void *cookie)
932 {
933 struct urtwn_softc *sc = cookie;
934
935 if (timeout_initialized(&sc->calib_to))
936 timeout_del(&sc->calib_to);
937 }
938
939 void
urtwn_scan_to(void * arg)940 urtwn_scan_to(void *arg)
941 {
942 struct urtwn_softc *sc = arg;
943
944 if (usbd_is_dying(sc->sc_udev))
945 return;
946
947 usbd_ref_incr(sc->sc_udev);
948 rtwn_next_scan(&sc->sc_sc);
949 usbd_ref_decr(sc->sc_udev);
950 }
951
952 void
urtwn_next_scan(void * arg)953 urtwn_next_scan(void *arg)
954 {
955 struct urtwn_softc *sc = arg;
956
957 if (!usbd_is_dying(sc->sc_udev))
958 timeout_add_msec(&sc->scan_to, 200);
959 }
960
961 void
urtwn_cancel_scan(void * cookie)962 urtwn_cancel_scan(void *cookie)
963 {
964 struct urtwn_softc *sc = cookie;
965
966 if (timeout_initialized(&sc->scan_to))
967 timeout_del(&sc->scan_to);
968 }
969
970 int
urtwn_newstate(struct ieee80211com * ic,enum ieee80211_state nstate,int arg)971 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
972 {
973 struct rtwn_softc *sc_sc = ic->ic_softc;
974 struct device *self = sc_sc->sc_pdev;
975 struct urtwn_softc *sc = (struct urtwn_softc *)self;
976 struct urtwn_cmd_newstate cmd;
977
978 /* Do it in a process context. */
979 cmd.state = nstate;
980 cmd.arg = arg;
981 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd));
982 return (0);
983 }
984
985 void
urtwn_newstate_cb(struct urtwn_softc * sc,void * arg)986 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg)
987 {
988 struct urtwn_cmd_newstate *cmd = arg;
989 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
990
991 rtwn_newstate(ic, cmd->state, cmd->arg);
992 }
993
994 void
urtwn_updateslot(struct ieee80211com * ic)995 urtwn_updateslot(struct ieee80211com *ic)
996 {
997 struct rtwn_softc *sc_sc = ic->ic_softc;
998 struct device *self = sc_sc->sc_pdev;
999 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1000
1001 /* Do it in a process context. */
1002 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0);
1003 }
1004
1005 void
urtwn_updateslot_cb(struct urtwn_softc * sc,void * arg)1006 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg)
1007 {
1008 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1009
1010 rtwn_updateslot(ic);
1011 }
1012
1013 void
urtwn_updateedca(struct ieee80211com * ic)1014 urtwn_updateedca(struct ieee80211com *ic)
1015 {
1016 struct rtwn_softc *sc_sc = ic->ic_softc;
1017 struct device *self = sc_sc->sc_pdev;
1018 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1019
1020 /* Do it in a process context. */
1021 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0);
1022 }
1023
1024 void
urtwn_updateedca_cb(struct urtwn_softc * sc,void * arg)1025 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg)
1026 {
1027 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1028
1029 rtwn_updateedca(ic);
1030 }
1031
1032 int
urtwn_set_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)1033 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1034 struct ieee80211_key *k)
1035 {
1036 struct rtwn_softc *sc_sc = ic->ic_softc;
1037 struct device *self = sc_sc->sc_pdev;
1038 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1039 struct urtwn_cmd_key cmd;
1040
1041 /* Only handle keys for CCMP */
1042 if (k->k_cipher != IEEE80211_CIPHER_CCMP)
1043 return ieee80211_set_key(ic, ni, k);
1044
1045 /* Defer setting of WEP keys until interface is brought up. */
1046 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
1047 (IFF_UP | IFF_RUNNING))
1048 return (0);
1049
1050 /* Do it in a process context. */
1051 cmd.key = *k;
1052 cmd.ni = ni;
1053 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd));
1054 sc->sc_key_tasks++;
1055
1056 return (EBUSY);
1057 }
1058
1059 void
urtwn_set_key_cb(struct urtwn_softc * sc,void * arg)1060 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg)
1061 {
1062 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1063 struct urtwn_cmd_key *cmd = arg;
1064
1065 sc->sc_key_tasks--;
1066
1067 if (rtwn_set_key(ic, cmd->ni, &cmd->key) == 0) {
1068 if (sc->sc_key_tasks == 0) {
1069 DPRINTF(("marking port %s valid\n",
1070 ether_sprintf(cmd->ni->ni_macaddr)));
1071 cmd->ni->ni_port_valid = 1;
1072 ieee80211_set_link_state(ic, LINK_STATE_UP);
1073 }
1074 } else {
1075 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH,
1076 IEEE80211_REASON_AUTH_LEAVE);
1077 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1078 }
1079 }
1080
1081 void
urtwn_delete_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)1082 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1083 struct ieee80211_key *k)
1084 {
1085 struct rtwn_softc *sc_sc = ic->ic_softc;
1086 struct device *self = sc_sc->sc_pdev;
1087 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1088 struct urtwn_cmd_key cmd;
1089
1090 /* Only handle keys for CCMP */
1091 if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
1092 ieee80211_delete_key(ic, ni, k);
1093 return;
1094 }
1095
1096 if (!(ic->ic_if.if_flags & IFF_RUNNING) ||
1097 ic->ic_state != IEEE80211_S_RUN)
1098 return; /* Nothing to do. */
1099
1100 /* Do it in a process context. */
1101 cmd.key = *k;
1102 cmd.ni = ni;
1103 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd));
1104 }
1105
1106 void
urtwn_delete_key_cb(struct urtwn_softc * sc,void * arg)1107 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg)
1108 {
1109 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1110 struct urtwn_cmd_key *cmd = arg;
1111
1112 rtwn_delete_key(ic, cmd->ni, &cmd->key);
1113 }
1114
1115 int
urtwn_ccmp_decap(struct urtwn_softc * sc,struct mbuf * m,struct ieee80211_node * ni)1116 urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m,
1117 struct ieee80211_node *ni)
1118 {
1119 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1120 struct ieee80211_key *k;
1121 struct ieee80211_frame *wh;
1122 uint64_t pn, *prsc;
1123 uint8_t *ivp;
1124 uint8_t tid;
1125 int hdrlen, hasqos;
1126
1127 k = ieee80211_get_rxkey(ic, m, ni);
1128 if (k == NULL)
1129 return 1;
1130
1131 wh = mtod(m, struct ieee80211_frame *);
1132 hdrlen = ieee80211_get_hdrlen(wh);
1133 ivp = (uint8_t *)wh + hdrlen;
1134
1135 /* Check that ExtIV bit is set. */
1136 if (!(ivp[3] & IEEE80211_WEP_EXTIV))
1137 return 1;
1138
1139 hasqos = ieee80211_has_qos(wh);
1140 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0;
1141 prsc = &k->k_rsc[tid];
1142
1143 /* Extract the 48-bit PN from the CCMP header. */
1144 pn = (uint64_t)ivp[0] |
1145 (uint64_t)ivp[1] << 8 |
1146 (uint64_t)ivp[4] << 16 |
1147 (uint64_t)ivp[5] << 24 |
1148 (uint64_t)ivp[6] << 32 |
1149 (uint64_t)ivp[7] << 40;
1150 if (pn <= *prsc) {
1151 ic->ic_stats.is_ccmp_replays++;
1152 return 1;
1153 }
1154 /* Last seen packet number is updated in ieee80211_inputm(). */
1155
1156 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */
1157 m_adj(m, -IEEE80211_CCMP_MICLEN);
1158 return 0;
1159 }
1160
1161 void
urtwn_rx_frame(struct urtwn_softc * sc,uint8_t * buf,int pktlen,struct mbuf_list * ml)1162 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen,
1163 struct mbuf_list *ml)
1164 {
1165 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1166 struct ifnet *ifp = &ic->ic_if;
1167 struct ieee80211_rxinfo rxi;
1168 struct ieee80211_frame *wh;
1169 struct ieee80211_node *ni;
1170 struct r92c_rx_desc_usb *rxd;
1171 uint32_t rxdw0, rxdw3;
1172 struct mbuf *m;
1173 uint8_t rate;
1174 int8_t rssi = 0;
1175 int s, infosz;
1176
1177 rxd = (struct r92c_rx_desc_usb *)buf;
1178 rxdw0 = letoh32(rxd->rxdw0);
1179 rxdw3 = letoh32(rxd->rxdw3);
1180
1181 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) {
1182 /*
1183 * This should not happen since we setup our Rx filter
1184 * to not receive these frames.
1185 */
1186 ifp->if_ierrors++;
1187 return;
1188 }
1189 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) {
1190 ifp->if_ierrors++;
1191 return;
1192 }
1193
1194 rate = (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) ?
1195 MS(rxdw3, R92E_RXDW3_RATE) : MS(rxdw3, R92C_RXDW3_RATE);
1196 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
1197
1198 /* Get RSSI from PHY status descriptor if present. */
1199 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
1200 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]);
1201 /* Update our average RSSI. */
1202 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi);
1203 }
1204
1205 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n",
1206 pktlen, rate, infosz, rssi));
1207
1208 MGETHDR(m, M_DONTWAIT, MT_DATA);
1209 if (__predict_false(m == NULL)) {
1210 ifp->if_ierrors++;
1211 return;
1212 }
1213 if (pktlen > MHLEN) {
1214 MCLGET(m, M_DONTWAIT);
1215 if (__predict_false(!(m->m_flags & M_EXT))) {
1216 ifp->if_ierrors++;
1217 m_freem(m);
1218 return;
1219 }
1220 }
1221 /* Finalize mbuf. */
1222 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz);
1223 memcpy(mtod(m, uint8_t *), wh, pktlen);
1224 m->m_pkthdr.len = m->m_len = pktlen;
1225
1226 s = splnet();
1227 #if NBPFILTER > 0
1228 if (__predict_false(sc->sc_drvbpf != NULL)) {
1229 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
1230 struct mbuf mb;
1231
1232 tap->wr_flags = 0;
1233 /* Map HW rate index to 802.11 rate. */
1234 if (!(rxdw3 & R92C_RXDW3_HT)) {
1235 switch (rate) {
1236 /* CCK. */
1237 case 0: tap->wr_rate = 2; break;
1238 case 1: tap->wr_rate = 4; break;
1239 case 2: tap->wr_rate = 11; break;
1240 case 3: tap->wr_rate = 22; break;
1241 /* OFDM. */
1242 case 4: tap->wr_rate = 12; break;
1243 case 5: tap->wr_rate = 18; break;
1244 case 6: tap->wr_rate = 24; break;
1245 case 7: tap->wr_rate = 36; break;
1246 case 8: tap->wr_rate = 48; break;
1247 case 9: tap->wr_rate = 72; break;
1248 case 10: tap->wr_rate = 96; break;
1249 case 11: tap->wr_rate = 108; break;
1250 }
1251 if (rate <= 3)
1252 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1253 } else if (rate >= 12) { /* MCS0~15. */
1254 /* Bit 7 set means HT MCS instead of rate. */
1255 tap->wr_rate = 0x80 | (rate - 12);
1256 }
1257 tap->wr_dbm_antsignal = rssi;
1258 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq);
1259 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags);
1260
1261 mb.m_data = (caddr_t)tap;
1262 mb.m_len = sc->sc_rxtap_len;
1263 mb.m_next = m;
1264 mb.m_nextpkt = NULL;
1265 mb.m_type = 0;
1266 mb.m_flags = 0;
1267 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN);
1268 }
1269 #endif
1270
1271 ni = ieee80211_find_rxnode(ic, wh);
1272 memset(&rxi, 0, sizeof(rxi));
1273 rxi.rxi_rssi = rssi;
1274
1275 /* Handle hardware decryption. */
1276 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL)
1277 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) &&
1278 (ni->ni_flags & IEEE80211_NODE_RXPROT) &&
1279 ((!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1280 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) ||
1281 (IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1282 ni->ni_rsngroupcipher == IEEE80211_CIPHER_CCMP))) {
1283 if (urtwn_ccmp_decap(sc, m, ni) != 0) {
1284 ifp->if_ierrors++;
1285 m_freem(m);
1286 ieee80211_release_node(ic, ni);
1287 splx(s);
1288 return;
1289 }
1290 rxi.rxi_flags |= IEEE80211_RXI_HWDEC;
1291 }
1292
1293 ieee80211_inputm(ifp, m, ni, &rxi, ml);
1294 /* Node is no longer needed. */
1295 ieee80211_release_node(ic, ni);
1296 splx(s);
1297 }
1298
1299 void
urtwn_rxeof(struct usbd_xfer * xfer,void * priv,usbd_status status)1300 urtwn_rxeof(struct usbd_xfer *xfer, void *priv,
1301 usbd_status status)
1302 {
1303 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
1304 struct urtwn_rx_data *data = priv;
1305 struct urtwn_softc *sc = data->sc;
1306 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1307 struct r92c_rx_desc_usb *rxd;
1308 uint32_t rxdw0;
1309 uint8_t *buf;
1310 int len, totlen, pktlen, infosz, npkts, error, align;
1311
1312 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1313 DPRINTF(("RX status=%d\n", status));
1314 if (status == USBD_STALLED)
1315 usbd_clear_endpoint_stall_async(sc->rx_pipe);
1316 if (status != USBD_CANCELLED)
1317 goto resubmit;
1318 return;
1319 }
1320 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL);
1321
1322 if (__predict_false(len < sizeof(*rxd))) {
1323 DPRINTF(("xfer too short %d\n", len));
1324 goto resubmit;
1325 }
1326 buf = data->buf;
1327
1328 /* Get the number of encapsulated frames. */
1329 rxd = (struct r92c_rx_desc_usb *)buf;
1330 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT);
1331 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts));
1332
1333 if (sc->sc_sc.chip & RTWN_CHIP_88E) {
1334 int ntries, type;
1335 struct r88e_tx_rpt_ccx *rxstat;
1336
1337 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT);
1338
1339 if (type == R88E_RXDW3_RPT_TX1) {
1340 buf += sizeof(struct r92c_rx_desc_usb);
1341 rxstat = (struct r88e_tx_rpt_ccx *)buf;
1342 ntries = MS(letoh32(rxstat->rptb2),
1343 R88E_RPTB2_RETRY_CNT);
1344
1345 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK)
1346 sc->amn.amn_txcnt++;
1347 if (ntries > 0)
1348 sc->amn.amn_retrycnt++;
1349
1350 goto resubmit;
1351 }
1352 } else if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) {
1353 int type;
1354 struct r92e_c2h_tx_rpt *txrpt;
1355
1356 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) {
1357 if (len < sizeof(struct r92c_rx_desc_usb) + 2)
1358 goto resubmit;
1359
1360 type = buf[sizeof(struct r92c_rx_desc_usb)];
1361 switch (type) {
1362 case R92C_C2HEVT_TX_REPORT:
1363 buf += sizeof(struct r92c_rx_desc_usb) + 2;
1364 txrpt = (struct r92e_c2h_tx_rpt *)buf;
1365 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0)
1366 sc->amn.amn_retrycnt++;
1367 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER |
1368 R92E_RPTB0_LIFE_EXPIRE)) == 0)
1369 sc->amn.amn_txcnt++;
1370 break;
1371 default:
1372 break;
1373 }
1374 goto resubmit;
1375 }
1376 }
1377
1378 align = ((sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) ? 7 : 127);
1379
1380 /* Process all of them. */
1381 while (npkts-- > 0) {
1382 if (__predict_false(len < sizeof(*rxd)))
1383 break;
1384 rxd = (struct r92c_rx_desc_usb *)buf;
1385 rxdw0 = letoh32(rxd->rxdw0);
1386
1387 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
1388 if (__predict_false(pktlen == 0))
1389 break;
1390
1391 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
1392
1393 /* Make sure everything fits in xfer. */
1394 totlen = sizeof(*rxd) + infosz + pktlen;
1395 if (__predict_false(totlen > len))
1396 break;
1397
1398 /* Process 802.11 frame. */
1399 urtwn_rx_frame(sc, buf, pktlen, &ml);
1400
1401 /* Handle chunk alignment. */
1402 totlen = (totlen + align) & ~align;
1403 buf += totlen;
1404 len -= totlen;
1405 }
1406 if_input(&ic->ic_if, &ml);
1407
1408 resubmit:
1409 /* Setup a new transfer. */
1410 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ,
1411 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof);
1412 error = usbd_transfer(data->xfer);
1413 if (error != 0 && error != USBD_IN_PROGRESS)
1414 DPRINTF(("could not set up new transfer: %d\n", error));
1415 }
1416
1417 void
urtwn_txeof(struct usbd_xfer * xfer,void * priv,usbd_status status)1418 urtwn_txeof(struct usbd_xfer *xfer, void *priv,
1419 usbd_status status)
1420 {
1421 struct urtwn_tx_data *data = priv;
1422 struct urtwn_softc *sc = data->sc;
1423 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if;
1424 int s;
1425
1426 s = splnet();
1427 /* Put this Tx buffer back to our free list. */
1428 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next);
1429
1430 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1431 DPRINTF(("TX status=%d\n", status));
1432 if (status == USBD_STALLED)
1433 usbd_clear_endpoint_stall_async(data->pipe);
1434 ifp->if_oerrors++;
1435 splx(s);
1436 return;
1437 }
1438 sc->sc_sc.sc_tx_timer = 0;
1439
1440 /* We just released a Tx buffer, notify Tx. */
1441 if (ifq_is_oactive(&ifp->if_snd)) {
1442 ifq_clr_oactive(&ifp->if_snd);
1443 rtwn_start(ifp);
1444 }
1445 splx(s);
1446 }
1447
1448 void
urtwn_tx_fill_desc(struct urtwn_softc * sc,uint8_t ** txdp,struct mbuf * m,struct ieee80211_frame * wh,struct ieee80211_key * k,struct ieee80211_node * ni)1449 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m,
1450 struct ieee80211_frame *wh, struct ieee80211_key *k,
1451 struct ieee80211_node *ni)
1452 {
1453 struct r92c_tx_desc_usb *txd;
1454 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1455 uint8_t raid, type, rtsrate;
1456 uint32_t pktlen;
1457
1458 txd = (struct r92c_tx_desc_usb *)*txdp;
1459 (*txdp) += sizeof(*txd);
1460 memset(txd, 0, sizeof(*txd));
1461
1462 pktlen = m->m_pkthdr.len;
1463 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
1464 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER,
1465 R92C_TXDW1_CIPHER_AES));
1466 pktlen += IEEE80211_CCMP_HDRLEN;
1467 }
1468
1469 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1470
1471 txd->txdw0 |= htole32(
1472 SM(R92C_TXDW0_PKTLEN, pktlen) |
1473 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1474 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1475 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1476 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1477
1478 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1479 type == IEEE80211_FC0_TYPE_DATA) {
1480 if (ic->ic_curmode == IEEE80211_MODE_11B ||
1481 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B))
1482 raid = R92C_RAID_11B;
1483 else
1484 raid = R92C_RAID_11BG;
1485 if (sc->sc_sc.chip & RTWN_CHIP_88E) {
1486 txd->txdw1 |= htole32(
1487 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) |
1488 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1489 SM(R92C_TXDW1_RAID, raid));
1490 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK);
1491 /* Request TX status report for AMRR */
1492 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT);
1493 } else {
1494 txd->txdw1 |= htole32(
1495 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) |
1496 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1497 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK);
1498 }
1499
1500 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) {
1501 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1502 R92C_TXDW4_HWRTSEN);
1503 } else if (ic->ic_flags & IEEE80211_F_USEPROT) {
1504 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1505 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1506 R92C_TXDW4_HWRTSEN);
1507 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1508 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1509 R92C_TXDW4_HWRTSEN);
1510 }
1511 }
1512 txd->txdw5 |= htole32(0x0001ff00);
1513
1514 if (ic->ic_curmode == IEEE80211_MODE_11B)
1515 rtsrate = 0; /* CCK1 */
1516 else
1517 rtsrate = 8; /* OFDM24 */
1518
1519 if (sc->sc_sc.chip & RTWN_CHIP_88E) {
1520 /* Use AMRR */
1521 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1522 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate));
1523 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE,
1524 ni->ni_txrate));
1525 } else {
1526 /* Send data at OFDM54. */
1527 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate));
1528 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
1529 }
1530 } else {
1531 txd->txdw1 |= htole32(
1532 SM(R92C_TXDW1_MACID, 0) |
1533 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1534 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1535
1536 /* Force CCK1. */
1537 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1538 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1539 }
1540 /* Set sequence number (already little endian). */
1541 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT;
1542
1543 if (!ieee80211_has_qos(wh)) {
1544 /* Use HW sequence numbering for non-QoS frames. */
1545 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
1546 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN);
1547 } else
1548 txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1549 }
1550
1551 void
urtwn_tx_fill_desc_gen2(struct urtwn_softc * sc,uint8_t ** txdp,struct mbuf * m,struct ieee80211_frame * wh,struct ieee80211_key * k,struct ieee80211_node * ni)1552 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m,
1553 struct ieee80211_frame *wh, struct ieee80211_key *k,
1554 struct ieee80211_node *ni)
1555 {
1556 struct r92e_tx_desc_usb *txd;
1557 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1558 uint8_t raid, type;
1559 uint32_t pktlen;
1560
1561 txd = (struct r92e_tx_desc_usb *)*txdp;
1562 (*txdp) += sizeof(*txd);
1563 memset(txd, 0, sizeof(*txd));
1564
1565 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1566
1567 pktlen = m->m_pkthdr.len;
1568 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
1569 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER,
1570 R92C_TXDW1_CIPHER_AES));
1571 pktlen += IEEE80211_CCMP_HDRLEN;
1572 }
1573
1574 txd->txdw0 |= htole32(
1575 SM(R92C_TXDW0_PKTLEN, pktlen) |
1576 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1577 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1578 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1579 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1580
1581 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1582 type == IEEE80211_FC0_TYPE_DATA) {
1583 if (ic->ic_curmode == IEEE80211_MODE_11B ||
1584 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B))
1585 raid = R92E_RAID_11B;
1586 else
1587 raid = R92E_RAID_11BG;
1588 txd->txdw1 |= htole32(
1589 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) |
1590 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1591 SM(R92C_TXDW1_RAID, raid));
1592 /* Request TX status report for AMRR */
1593 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK);
1594
1595 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) {
1596 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1597 R92C_TXDW4_HWRTSEN);
1598 } else if (ic->ic_flags & IEEE80211_F_USEPROT) {
1599 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1600 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1601 R92C_TXDW4_HWRTSEN);
1602 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1603 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1604 R92C_TXDW4_HWRTSEN);
1605 }
1606 }
1607 txd->txdw5 |= htole32(0x0001ff00);
1608
1609 /* Use AMRR */
1610 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE);
1611 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, 8));
1612 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate));
1613 } else {
1614 txd->txdw1 |= htole32(
1615 SM(R92E_TXDW1_MACID, 0) |
1616 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1617 SM(R92C_TXDW1_RAID, R92E_RAID_11B));
1618
1619 /* Force CCK1. */
1620 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE);
1621 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0));
1622 }
1623 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f));
1624
1625 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq));
1626
1627 if (!ieee80211_has_qos(wh)) {
1628 /* Use HW sequence numbering for non-QoS frames. */
1629 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN);
1630 }
1631 }
1632
1633 int
urtwn_tx(void * cookie,struct mbuf * m,struct ieee80211_node * ni)1634 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni)
1635 {
1636 struct urtwn_softc *sc = cookie;
1637 struct ieee80211com *ic = &sc->sc_sc.sc_ic;
1638 struct ieee80211_frame *wh;
1639 struct ieee80211_key *k = NULL;
1640 struct urtwn_tx_data *data;
1641 struct usbd_pipe *pipe;
1642 uint16_t qos, sum;
1643 uint8_t tid, qid;
1644 int i, xferlen, error, headerlen;
1645 uint8_t *txdp;
1646
1647 wh = mtod(m, struct ieee80211_frame *);
1648
1649 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1650 k = ieee80211_get_txkey(ic, wh, ni);
1651 if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
1652 if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
1653 return (ENOBUFS);
1654 wh = mtod(m, struct ieee80211_frame *);
1655 }
1656 }
1657
1658 if (ieee80211_has_qos(wh)) {
1659 qos = ieee80211_get_qos(wh);
1660 tid = qos & IEEE80211_QOS_TID;
1661 qid = ieee80211_up_to_ac(ic, tid);
1662 } else if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK)
1663 != IEEE80211_FC0_TYPE_DATA) {
1664 /* Use AC VO for management frames. */
1665 qid = EDCA_AC_VO;
1666 } else
1667 qid = EDCA_AC_BE;
1668
1669 /* Get the USB pipe to use for this AC. */
1670 pipe = sc->tx_pipe[sc->ac2idx[qid]];
1671
1672 /* Grab a Tx buffer from our free list. */
1673 data = TAILQ_FIRST(&sc->tx_free_list);
1674 TAILQ_REMOVE(&sc->tx_free_list, data, next);
1675
1676 /* Fill Tx descriptor. */
1677 txdp = data->buf;
1678 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))
1679 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni);
1680 else
1681 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni);
1682
1683 /* Compute Tx descriptor checksum. */
1684 sum = 0;
1685 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++)
1686 sum ^= ((uint16_t *)data->buf)[i];
1687 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum;
1688
1689 #if NBPFILTER > 0
1690 if (__predict_false(sc->sc_drvbpf != NULL)) {
1691 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1692 struct mbuf mb;
1693
1694 tap->wt_flags = 0;
1695 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
1696 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
1697
1698 mb.m_data = (caddr_t)tap;
1699 mb.m_len = sc->sc_txtap_len;
1700 mb.m_next = m;
1701 mb.m_nextpkt = NULL;
1702 mb.m_type = 0;
1703 mb.m_flags = 0;
1704 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT);
1705 }
1706 #endif
1707
1708 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
1709 xferlen = (txdp - data->buf) + m->m_pkthdr.len +
1710 IEEE80211_CCMP_HDRLEN;
1711 headerlen = ieee80211_get_hdrlen(wh);
1712
1713 m_copydata(m, 0, headerlen, txdp);
1714 txdp += headerlen;
1715
1716 k->k_tsc++;
1717 txdp[0] = k->k_tsc;
1718 txdp[1] = k->k_tsc >> 8;
1719 txdp[2] = 0;
1720 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV;
1721 txdp[4] = k->k_tsc >> 16;
1722 txdp[5] = k->k_tsc >> 24;
1723 txdp[6] = k->k_tsc >> 32;
1724 txdp[7] = k->k_tsc >> 40;
1725 txdp += IEEE80211_CCMP_HDRLEN;
1726
1727 m_copydata(m, headerlen, m->m_pkthdr.len - headerlen, txdp);
1728 m_freem(m);
1729 } else {
1730 xferlen = (txdp - data->buf) + m->m_pkthdr.len;
1731 m_copydata(m, 0, m->m_pkthdr.len, txdp);
1732 m_freem(m);
1733 }
1734
1735 data->pipe = pipe;
1736 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen,
1737 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT,
1738 urtwn_txeof);
1739 error = usbd_transfer(data->xfer);
1740 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) {
1741 /* Put this Tx buffer back to our free list. */
1742 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next);
1743 return (error);
1744 }
1745 ieee80211_release_node(ic, ni);
1746 return (0);
1747 }
1748
1749 int
urtwn_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1750 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1751 {
1752 struct rtwn_softc *sc_sc = ifp->if_softc;
1753 struct device *self = sc_sc->sc_pdev;
1754 struct urtwn_softc *sc = (struct urtwn_softc *)self;
1755 int error;
1756
1757 if (usbd_is_dying(sc->sc_udev))
1758 return ENXIO;
1759
1760 usbd_ref_incr(sc->sc_udev);
1761 error = rtwn_ioctl(ifp, cmd, data);
1762 usbd_ref_decr(sc->sc_udev);
1763
1764 return (error);
1765 }
1766
1767 int
urtwn_r92c_power_on(struct urtwn_softc * sc)1768 urtwn_r92c_power_on(struct urtwn_softc *sc)
1769 {
1770 uint32_t reg;
1771 int ntries;
1772
1773 /* Wait for autoload done bit. */
1774 for (ntries = 0; ntries < 1000; ntries++) {
1775 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
1776 break;
1777 DELAY(5);
1778 }
1779 if (ntries == 1000) {
1780 printf("%s: timeout waiting for chip autoload\n",
1781 sc->sc_dev.dv_xname);
1782 return (ETIMEDOUT);
1783 }
1784
1785 /* Unlock ISO/CLK/Power control register. */
1786 urtwn_write_1(sc, R92C_RSV_CTRL, 0);
1787 /* Move SPS into PWM mode. */
1788 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
1789 DELAY(100);
1790
1791 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
1792 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
1793 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
1794 reg | R92C_LDOV12D_CTRL_LDV12_EN);
1795 DELAY(100);
1796 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
1797 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
1798 ~R92C_SYS_ISO_CTRL_MD2PP);
1799 }
1800
1801 /* Auto enable WLAN. */
1802 urtwn_write_2(sc, R92C_APS_FSMCO,
1803 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
1804 for (ntries = 0; ntries < 1000; ntries++) {
1805 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
1806 R92C_APS_FSMCO_APFM_ONMAC))
1807 break;
1808 DELAY(5);
1809 }
1810 if (ntries == 1000) {
1811 printf("%s: timeout waiting for MAC auto ON\n",
1812 sc->sc_dev.dv_xname);
1813 return (ETIMEDOUT);
1814 }
1815
1816 /* Enable radio, GPIO and LED functions. */
1817 urtwn_write_2(sc, R92C_APS_FSMCO,
1818 R92C_APS_FSMCO_AFSM_HSUS |
1819 R92C_APS_FSMCO_PDN_EN |
1820 R92C_APS_FSMCO_PFM_ALDN);
1821 /* Release RF digital isolation. */
1822 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1823 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
1824
1825 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1826 reg = urtwn_read_2(sc, R92C_CR);
1827 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
1828 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
1829 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
1830 R92C_CR_ENSEC;
1831 urtwn_write_2(sc, R92C_CR, reg);
1832
1833 urtwn_write_1(sc, 0xfe10, 0x19);
1834 return (0);
1835 }
1836
1837 int
urtwn_r92e_power_on(struct urtwn_softc * sc)1838 urtwn_r92e_power_on(struct urtwn_softc *sc)
1839 {
1840 uint32_t reg;
1841 int ntries;
1842
1843 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) {
1844 /* LDO. */
1845 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3);
1846 } else {
1847 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2);
1848 reg &= 0xff0fffff;
1849 reg |= 0x00500000;
1850 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg);
1851 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83);
1852 }
1853
1854 /* 40MHz crystal source */
1855 urtwn_write_1(sc, R92C_AFE_PLL_CTRL,
1856 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb);
1857 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT,
1858 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f);
1859
1860 urtwn_write_1(sc, R92C_AFE_PLL_CTRL,
1861 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf);
1862 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT,
1863 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff);
1864
1865 /* Disable HWPDN. */
1866 urtwn_write_2(sc, R92C_APS_FSMCO,
1867 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
1868 for (ntries = 0; ntries < 5000; ntries++) {
1869 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
1870 break;
1871 DELAY(10);
1872 }
1873 if (ntries == 5000) {
1874 printf("%s: timeout waiting for chip power up\n",
1875 sc->sc_dev.dv_xname);
1876 return (ETIMEDOUT);
1877 }
1878
1879 /* Disable WL suspend. */
1880 urtwn_write_2(sc, R92C_APS_FSMCO,
1881 urtwn_read_2(sc, R92C_APS_FSMCO) &
1882 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
1883
1884 /* Auto enable WLAN. */
1885 urtwn_write_4(sc, R92C_APS_FSMCO,
1886 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON);
1887 urtwn_write_2(sc, R92C_APS_FSMCO,
1888 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
1889 for (ntries = 0; ntries < 5000; ntries++) {
1890 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
1891 R92C_APS_FSMCO_APFM_ONMAC))
1892 break;
1893 DELAY(10);
1894 }
1895 if (ntries == 5000) {
1896 printf("%s: timeout waiting for MAC auto ON\n",
1897 sc->sc_dev.dv_xname);
1898 return (ETIMEDOUT);
1899 }
1900
1901 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1902 urtwn_write_2(sc, R92C_CR, 0);
1903 reg = urtwn_read_2(sc, R92C_CR);
1904 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
1905 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
1906 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
1907 urtwn_write_2(sc, R92C_CR, reg);
1908 return (0);
1909 }
1910
1911 int
urtwn_r88e_power_on(struct urtwn_softc * sc)1912 urtwn_r88e_power_on(struct urtwn_softc *sc)
1913 {
1914 uint32_t reg;
1915 int ntries;
1916
1917 /* Wait for power ready bit. */
1918 for (ntries = 0; ntries < 5000; ntries++) {
1919 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
1920 break;
1921 DELAY(10);
1922 }
1923 if (ntries == 5000) {
1924 printf("%s: timeout waiting for chip power up\n",
1925 sc->sc_dev.dv_xname);
1926 return (ETIMEDOUT);
1927 }
1928
1929 /* Reset BB. */
1930 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
1931 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
1932 R92C_SYS_FUNC_EN_BB_GLB_RST));
1933
1934 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
1935 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
1936
1937 /* Disable HWPDN. */
1938 urtwn_write_2(sc, R92C_APS_FSMCO,
1939 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
1940 /* Disable WL suspend. */
1941 urtwn_write_2(sc, R92C_APS_FSMCO,
1942 urtwn_read_2(sc, R92C_APS_FSMCO) &
1943 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
1944
1945 /* Auto enable WLAN. */
1946 urtwn_write_2(sc, R92C_APS_FSMCO,
1947 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
1948 for (ntries = 0; ntries < 5000; ntries++) {
1949 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
1950 R92C_APS_FSMCO_APFM_ONMAC))
1951 break;
1952 DELAY(10);
1953 }
1954 if (ntries == 5000) {
1955 printf("%s: timeout waiting for MAC auto ON\n",
1956 sc->sc_dev.dv_xname);
1957 return (ETIMEDOUT);
1958 }
1959
1960 /* Enable LDO normal mode. */
1961 urtwn_write_1(sc, R92C_LPLDO_CTRL,
1962 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10);
1963
1964 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1965 urtwn_write_2(sc, R92C_CR, 0);
1966 reg = urtwn_read_2(sc, R92C_CR);
1967 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
1968 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
1969 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
1970 urtwn_write_2(sc, R92C_CR, reg);
1971 return (0);
1972 }
1973
1974 int
urtwn_r88f_power_on(struct urtwn_softc * sc)1975 urtwn_r88f_power_on(struct urtwn_softc *sc)
1976 {
1977 uint32_t reg;
1978 int ntries;
1979
1980 /* Enable WL suspend. */
1981 urtwn_write_2(sc, R92C_APS_FSMCO,
1982 urtwn_read_2(sc, R92C_APS_FSMCO) &
1983 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
1984 /* Turn off USB APHY LDO under suspend mode. */
1985 urtwn_write_1(sc, 0xc4, urtwn_read_1(sc, 0xc4) & ~0x10);
1986
1987 /* Disable SW LPS. */
1988 urtwn_write_2(sc, R92C_APS_FSMCO,
1989 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APFM_RSM);
1990 /* Wait for power ready bit. */
1991 for (ntries = 0; ntries < 5000; ntries++) {
1992 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
1993 break;
1994 DELAY(10);
1995 }
1996 if (ntries == 5000) {
1997 printf("%s: timeout waiting for chip power up\n",
1998 sc->sc_dev.dv_xname);
1999 return (ETIMEDOUT);
2000 }
2001 /* Disable HWPDN. */
2002 urtwn_write_2(sc, R92C_APS_FSMCO,
2003 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
2004 /* Disable WL suspend. */
2005 urtwn_write_2(sc, R92C_APS_FSMCO,
2006 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_AFSM_HSUS);
2007 /* Auto enable WLAN. */
2008 urtwn_write_2(sc, R92C_APS_FSMCO,
2009 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
2010 for (ntries = 0; ntries < 5000; ntries++) {
2011 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
2012 R92C_APS_FSMCO_APFM_ONMAC))
2013 break;
2014 DELAY(10);
2015 }
2016 if (ntries == 5000) {
2017 printf("%s: timeout waiting for MAC auto ON\n",
2018 sc->sc_dev.dv_xname);
2019 return (ETIMEDOUT);
2020 }
2021 /* Reduce RF noise. */
2022 urtwn_write_1(sc, R92C_AFE_LDO_CTRL, 0x35);
2023
2024 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2025 urtwn_write_2(sc, R92C_CR, 0);
2026 reg = urtwn_read_2(sc, R92C_CR);
2027 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2028 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2029 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
2030 urtwn_write_2(sc, R92C_CR, reg);
2031 return (0);
2032 }
2033
2034 int
urtwn_llt_init(struct urtwn_softc * sc,int page_count)2035 urtwn_llt_init(struct urtwn_softc *sc, int page_count)
2036 {
2037 int i, error, pktbuf_count;
2038
2039 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ?
2040 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT;
2041
2042 /* Reserve pages [0; page_count]. */
2043 for (i = 0; i < page_count; i++) {
2044 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
2045 return (error);
2046 }
2047 /* NB: 0xff indicates end-of-list. */
2048 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
2049 return (error);
2050 /*
2051 * Use pages [page_count + 1; pktbuf_count - 1]
2052 * as ring buffer.
2053 */
2054 for (++i; i < pktbuf_count - 1; i++) {
2055 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
2056 return (error);
2057 }
2058 /* Make the last page point to the beginning of the ring buffer. */
2059 error = urtwn_llt_write(sc, i, page_count + 1);
2060 return (error);
2061 }
2062
2063 int
urtwn_auto_llt_init(struct urtwn_softc * sc)2064 urtwn_auto_llt_init(struct urtwn_softc *sc)
2065 {
2066 int ntries;
2067
2068 urtwn_write_4(sc, R92E_AUTO_LLT,
2069 urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN);
2070 for (ntries = 0; ntries < 1000; ntries++) {
2071 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN))
2072 return (0);
2073 DELAY(2);
2074 }
2075
2076 return (ETIMEDOUT);
2077 }
2078
2079 int
urtwn_fw_loadpage(void * cookie,int page,uint8_t * buf,int len)2080 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len)
2081 {
2082 struct urtwn_softc *sc = cookie;
2083 uint32_t reg;
2084 int maxblksz, off, mlen, error = 0;
2085
2086 reg = urtwn_read_4(sc, R92C_MCUFWDL);
2087 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
2088 urtwn_write_4(sc, R92C_MCUFWDL, reg);
2089
2090 maxblksz = (sc->sc_sc.chip & RTWN_CHIP_92E) ? 254 : 196;
2091
2092 off = R92C_FW_START_ADDR;
2093 while (len > 0) {
2094 if (len > maxblksz)
2095 mlen = maxblksz;
2096 else if (len > 4)
2097 mlen = 4;
2098 else
2099 mlen = 1;
2100 error = urtwn_write_region_1(sc, off, buf, mlen);
2101 if (error != 0)
2102 break;
2103 off += mlen;
2104 buf += mlen;
2105 len -= mlen;
2106 }
2107 return (error);
2108 }
2109
2110 int
urtwn_load_firmware(void * cookie,u_char ** fw,size_t * len)2111 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len)
2112 {
2113 struct urtwn_softc *sc = cookie;
2114 const char *name;
2115 int error;
2116
2117 if (sc->sc_sc.chip & RTWN_CHIP_92E)
2118 name = "urtwn-rtl8192eu";
2119 else if (sc->sc_sc.chip & RTWN_CHIP_88E)
2120 name = "urtwn-rtl8188eu";
2121 else if (sc->sc_sc.chip & RTWN_CHIP_88F)
2122 name = "urtwn-rtl8188ftv";
2123 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) ==
2124 RTWN_CHIP_UMC_A_CUT)
2125 name = "urtwn-rtl8192cU";
2126 else
2127 name = "urtwn-rtl8192cT";
2128
2129 error = loadfirmware(name, fw, len);
2130 if (error)
2131 printf("%s: could not read firmware %s (error %d)\n",
2132 sc->sc_dev.dv_xname, name, error);
2133 return (error);
2134 }
2135
2136 int
urtwn_dma_init(void * cookie)2137 urtwn_dma_init(void *cookie)
2138 {
2139 struct urtwn_softc *sc = cookie;
2140 uint32_t reg;
2141 uint16_t dmasize;
2142 int hqpages, lqpages, nqpages, pagecnt, boundary;
2143 int error, hashq, haslq, hasnq;
2144
2145 /* Default initialization of chipset values. */
2146 if (sc->sc_sc.chip & RTWN_CHIP_88E) {
2147 hqpages = R88E_HQ_NPAGES;
2148 lqpages = R88E_LQ_NPAGES;
2149 nqpages = R88E_NQ_NPAGES;
2150 pagecnt = R88E_TX_PAGE_COUNT;
2151 dmasize = R88E_MAX_RX_DMA_SIZE;
2152 } else if (sc->sc_sc.chip & RTWN_CHIP_88F) {
2153 hqpages = R88F_HQ_NPAGES;
2154 lqpages = R88F_LQ_NPAGES;
2155 nqpages = R88F_NQ_NPAGES;
2156 pagecnt = R88F_TX_PAGE_COUNT;
2157 dmasize = R88F_MAX_RX_DMA_SIZE;
2158 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) {
2159 hqpages = R92E_HQ_NPAGES;
2160 lqpages = R92E_LQ_NPAGES;
2161 nqpages = R92E_NQ_NPAGES;
2162 pagecnt = R92E_TX_PAGE_COUNT;
2163 dmasize = R92E_MAX_RX_DMA_SIZE;
2164 } else {
2165 hqpages = R92C_HQ_NPAGES;
2166 lqpages = R92C_LQ_NPAGES;
2167 nqpages = R92C_NQ_NPAGES;
2168 pagecnt = R92C_TX_PAGE_COUNT;
2169 dmasize = R92C_MAX_RX_DMA_SIZE;
2170 }
2171 boundary = pagecnt + 1;
2172
2173 /* Initialize LLT table. */
2174 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))
2175 error = urtwn_auto_llt_init(sc);
2176 else
2177 error = urtwn_llt_init(sc, pagecnt);
2178 if (error != 0)
2179 return (error);
2180
2181 /* Get Tx queues to USB endpoints mapping. */
2182 hashq = hasnq = haslq = 0;
2183 switch (sc->ntx) {
2184 case 3:
2185 haslq = 1;
2186 pagecnt -= lqpages;
2187 /* FALLTHROUGH */
2188 case 2:
2189 hasnq = 1;
2190 pagecnt -= nqpages;
2191 /* FALLTHROUGH */
2192 case 1:
2193 hashq = 1;
2194 pagecnt -= hqpages;
2195 break;
2196 }
2197
2198 /* Set number of pages for normal priority queue. */
2199 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
2200 urtwn_write_4(sc, R92C_RQPN,
2201 /* Set number of pages for public queue. */
2202 SM(R92C_RQPN_PUBQ, pagecnt) |
2203 /* Set number of pages for high priority queue. */
2204 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) |
2205 /* Set number of pages for low priority queue. */
2206 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) |
2207 /* Load values. */
2208 R92C_RQPN_LD);
2209
2210 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary);
2211 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary);
2212 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary);
2213 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary);
2214 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary);
2215
2216 /* Set queue to USB pipe mapping. */
2217 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2218 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2219 if (haslq)
2220 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2221 else if (hashq) {
2222 if (!hasnq)
2223 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
2224 else
2225 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2226 }
2227 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2228
2229 /* Set Tx/Rx transfer page boundary. */
2230 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1);
2231
2232 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) {
2233 /* Set Tx/Rx transfer page size. */
2234 if (sc->sc_sc.chip & RTWN_CHIP_88F) {
2235 urtwn_write_1(sc, R92C_PBP,
2236 SM(R92C_PBP_PSRX, R92C_PBP_256) |
2237 SM(R92C_PBP_PSTX, R92C_PBP_256));
2238 } else {
2239 urtwn_write_1(sc, R92C_PBP,
2240 SM(R92C_PBP_PSRX, R92C_PBP_128) |
2241 SM(R92C_PBP_PSTX, R92C_PBP_128));
2242 }
2243 }
2244 return (error);
2245 }
2246
2247 void
urtwn_aggr_init(void * cookie)2248 urtwn_aggr_init(void *cookie)
2249 {
2250 struct urtwn_softc *sc = cookie;
2251 uint32_t reg = 0;
2252 int dmasize, dmatiming, ndesc;
2253
2254 /* Set burst packet length. */
2255 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))
2256 urtwn_burstlen_init(sc);
2257
2258 if (sc->sc_sc.chip & RTWN_CHIP_88F) {
2259 dmasize = 5;
2260 dmatiming = 32;
2261 ndesc = 6;
2262 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) {
2263 dmasize = 6;
2264 dmatiming = 32;
2265 ndesc = 3;
2266 } else {
2267 dmasize = 48;
2268 dmatiming = 4;
2269 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6;
2270 }
2271
2272 /* Tx aggregation setting. */
2273 reg = urtwn_read_4(sc, R92C_TDECTRL);
2274 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc);
2275 urtwn_write_4(sc, R92C_TDECTRL, reg);
2276 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))
2277 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1);
2278
2279 /* Rx aggregation setting. */
2280 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
2281 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
2282
2283 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize);
2284 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))
2285 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming);
2286 else
2287 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming);
2288
2289 if (sc->sc_sc.chip & RTWN_CHIP_88F) {
2290 urtwn_write_1(sc, R92E_RXDMA_PRO,
2291 urtwn_read_1(sc, R92E_RXDMA_PRO) | R92E_RXDMA_PRO_DMA_MODE);
2292 }
2293
2294 /* Drop incorrect bulk out. */
2295 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK,
2296 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) |
2297 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN);
2298 }
2299
2300 void
urtwn_mac_init(void * cookie)2301 urtwn_mac_init(void *cookie)
2302 {
2303 struct urtwn_softc *sc = cookie;
2304 int i;
2305
2306 /* Write MAC initialization values. */
2307 if (sc->sc_sc.chip & RTWN_CHIP_88E) {
2308 for (i = 0; i < nitems(rtl8188eu_mac); i++) {
2309 urtwn_write_1(sc, rtl8188eu_mac[i].reg,
2310 rtl8188eu_mac[i].val);
2311 }
2312 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07);
2313 } else if (sc->sc_sc.chip & RTWN_CHIP_88F) {
2314 for (i = 0; i < nitems(rtl8188ftv_mac); i++) {
2315 urtwn_write_1(sc, rtl8188ftv_mac[i].reg,
2316 rtl8188ftv_mac[i].val);
2317 }
2318 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) {
2319 for (i = 0; i < nitems(rtl8192eu_mac); i++) {
2320 urtwn_write_1(sc, rtl8192eu_mac[i].reg,
2321 rtl8192eu_mac[i].val);
2322 }
2323 } else {
2324 for (i = 0; i < nitems(rtl8192cu_mac); i++)
2325 urtwn_write_1(sc, rtl8192cu_mac[i].reg,
2326 rtl8192cu_mac[i].val);
2327 }
2328 }
2329
2330 void
urtwn_bb_init(void * cookie)2331 urtwn_bb_init(void *cookie)
2332 {
2333 struct urtwn_softc *sc = cookie;
2334 const struct r92c_bb_prog *prog;
2335 uint32_t reg;
2336 uint8_t xtal;
2337 int i;
2338
2339 /* Enable BB and RF. */
2340 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2341 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2342 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2343 R92C_SYS_FUNC_EN_DIO_RF);
2344
2345 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)))
2346 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
2347
2348 urtwn_write_1(sc, R92C_RF_CTRL,
2349 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2350 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2351 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
2352 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
2353
2354 if (!(sc->sc_sc.chip &
2355 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) {
2356 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
2357 urtwn_write_1(sc, 0x15, 0xe9);
2358 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2359 }
2360
2361 /* Select BB programming based on board type. */
2362 if (sc->sc_sc.chip & RTWN_CHIP_88E)
2363 prog = &rtl8188eu_bb_prog;
2364 else if (sc->sc_sc.chip & RTWN_CHIP_88F)
2365 prog = &rtl8188ftv_bb_prog;
2366 else if (sc->sc_sc.chip & RTWN_CHIP_92E)
2367 prog = &rtl8192eu_bb_prog;
2368 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) {
2369 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD)
2370 prog = &rtl8188ce_bb_prog;
2371 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA)
2372 prog = &rtl8188ru_bb_prog;
2373 else
2374 prog = &rtl8188cu_bb_prog;
2375 } else {
2376 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD)
2377 prog = &rtl8192ce_bb_prog;
2378 else
2379 prog = &rtl8192cu_bb_prog;
2380 }
2381 /* Write BB initialization values. */
2382 for (i = 0; i < prog->count; i++) {
2383 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
2384 DELAY(1);
2385 }
2386
2387 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) {
2388 /* 8192C 1T only configuration. */
2389 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2390 reg = (reg & ~0x00000003) | 0x2;
2391 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2392
2393 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2394 reg = (reg & ~0x00300033) | 0x00200022;
2395 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2396
2397 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2398 reg = (reg & ~0xff000000) | 0x45 << 24;
2399 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2400
2401 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2402 reg = (reg & ~0x000000ff) | 0x23;
2403 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2404
2405 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2406 reg = (reg & ~0x00000030) | 1 << 4;
2407 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2408
2409 reg = urtwn_bb_read(sc, 0xe74);
2410 reg = (reg & ~0x0c000000) | 2 << 26;
2411 urtwn_bb_write(sc, 0xe74, reg);
2412 reg = urtwn_bb_read(sc, 0xe78);
2413 reg = (reg & ~0x0c000000) | 2 << 26;
2414 urtwn_bb_write(sc, 0xe78, reg);
2415 reg = urtwn_bb_read(sc, 0xe7c);
2416 reg = (reg & ~0x0c000000) | 2 << 26;
2417 urtwn_bb_write(sc, 0xe7c, reg);
2418 reg = urtwn_bb_read(sc, 0xe80);
2419 reg = (reg & ~0x0c000000) | 2 << 26;
2420 urtwn_bb_write(sc, 0xe80, reg);
2421 reg = urtwn_bb_read(sc, 0xe88);
2422 reg = (reg & ~0x0c000000) | 2 << 26;
2423 urtwn_bb_write(sc, 0xe88, reg);
2424 }
2425
2426 /* Write AGC values. */
2427 for (i = 0; i < prog->agccount; i++) {
2428 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2429 prog->agcvals[i]);
2430 DELAY(1);
2431 }
2432
2433 if (sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_88F)) {
2434 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
2435 DELAY(1);
2436 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
2437 DELAY(1);
2438 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) {
2439 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022);
2440 DELAY(1);
2441 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020);
2442 DELAY(1);
2443 }
2444
2445 if (sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_88F)) {
2446 xtal = sc->sc_sc.crystal_cap & 0x3f;
2447 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
2448 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
2449 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6));
2450 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) {
2451 xtal = sc->sc_sc.crystal_cap & 0x3f;
2452 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3);
2453 urtwn_bb_write(sc, R92C_AFE_CTRL3,
2454 RW(reg, R92C_AFE_CTRL3_ADDR, xtal | xtal << 6));
2455 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb);
2456 }
2457
2458 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)
2459 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR;
2460 }
2461
2462 void
urtwn_burstlen_init(struct urtwn_softc * sc)2463 urtwn_burstlen_init(struct urtwn_softc *sc)
2464 {
2465 uint8_t reg;
2466
2467 reg = urtwn_read_1(sc, R92E_RXDMA_PRO);
2468 reg &= ~0x30;
2469 switch (sc->sc_udev->speed) {
2470 case USB_SPEED_HIGH:
2471 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e);
2472 break;
2473 default:
2474 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e);
2475 break;
2476 }
2477
2478 if (sc->sc_sc.chip & RTWN_CHIP_88F) {
2479 /* Setup AMPDU aggregation. */
2480 urtwn_write_1(sc, R88F_HT_SINGLE_AMPDU,
2481 urtwn_read_1(sc, R88F_HT_SINGLE_AMPDU) |
2482 R88F_HT_SINGLE_AMPDU_EN);
2483 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0c14);
2484 urtwn_write_1(sc, R88F_AMPDU_MAX_TIME, 0x70);
2485 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0xffffffff);
2486
2487 /* For VHT packet length 11K */
2488 urtwn_write_1(sc, R88F_RX_PKT_LIMIT, 0x18);
2489
2490 urtwn_write_1(sc, R92C_PIFS, 0);
2491 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 0x80);
2492 urtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x03086666);
2493 urtwn_write_1(sc, R92C_USTIME_TSF, 0x28);
2494 urtwn_write_1(sc, R88F_USTIME_EDCA, 0x28);
2495
2496 /* To prevent bus resetting the mac. */
2497 urtwn_write_1(sc, R92C_RSV_CTRL,
2498 urtwn_read_1(sc, R92C_RSV_CTRL) |
2499 R92C_RSV_CTRL_R_DIS_PRST_0 | R92C_RSV_CTRL_R_DIS_PRST_1);
2500 }
2501 }
2502
2503 int
urtwn_power_on(void * cookie)2504 urtwn_power_on(void *cookie)
2505 {
2506 struct urtwn_softc *sc = cookie;
2507
2508 if (sc->sc_sc.chip & RTWN_CHIP_88E)
2509 return (urtwn_r88e_power_on(sc));
2510 else if (sc->sc_sc.chip & RTWN_CHIP_88F)
2511 return (urtwn_r88f_power_on(sc));
2512 else if (sc->sc_sc.chip & RTWN_CHIP_92E)
2513 return (urtwn_r92e_power_on(sc));
2514
2515 return (urtwn_r92c_power_on(sc));
2516 }
2517
2518 int
urtwn_alloc_buffers(void * cookie)2519 urtwn_alloc_buffers(void *cookie)
2520 {
2521 struct urtwn_softc *sc = cookie;
2522 int error;
2523
2524 /* Init host async commands ring. */
2525 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0;
2526
2527 /* Allocate Tx/Rx buffers. */
2528 error = urtwn_alloc_rx_list(sc);
2529 if (error != 0) {
2530 printf("%s: could not allocate Rx buffers\n",
2531 sc->sc_dev.dv_xname);
2532 return (error);
2533 }
2534 error = urtwn_alloc_tx_list(sc);
2535 if (error != 0) {
2536 printf("%s: could not allocate Tx buffers\n",
2537 sc->sc_dev.dv_xname);
2538 return (error);
2539 }
2540
2541 return (0);
2542 }
2543
2544 int
urtwn_init(void * cookie)2545 urtwn_init(void *cookie)
2546 {
2547 struct urtwn_softc *sc = cookie;
2548 int i, error;
2549
2550 /* Reset USB mode switch setting. */
2551 if (sc->sc_sc.chip & RTWN_CHIP_92E)
2552 urtwn_write_1(sc, R92C_ACLK_MON, 0);
2553
2554 /* Queue Rx xfers. */
2555 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) {
2556 struct urtwn_rx_data *data = &sc->rx_data[i];
2557
2558 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf,
2559 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY,
2560 USBD_NO_TIMEOUT, urtwn_rxeof);
2561 error = usbd_transfer(data->xfer);
2562 if (error != 0 && error != USBD_IN_PROGRESS)
2563 return (error);
2564 }
2565
2566 ieee80211_amrr_node_init(&sc->amrr, &sc->amn);
2567
2568 /*
2569 * Enable TX reports for AMRR.
2570 * In order to get reports we need to explicitly reset the register.
2571 */
2572 if (sc->sc_sc.chip & RTWN_CHIP_88E)
2573 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc,
2574 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN);
2575
2576 return (0);
2577 }
2578
2579 void
urtwn_stop(void * cookie)2580 urtwn_stop(void *cookie)
2581 {
2582 struct urtwn_softc *sc = cookie;
2583 int i;
2584
2585 /* Abort Tx. */
2586 for (i = 0; i < R92C_MAX_EPOUT; i++) {
2587 if (sc->tx_pipe[i] != NULL)
2588 usbd_abort_pipe(sc->tx_pipe[i]);
2589 }
2590 /* Stop Rx pipe. */
2591 usbd_abort_pipe(sc->rx_pipe);
2592 /* Free Tx/Rx buffers. */
2593 urtwn_free_tx_list(sc);
2594 urtwn_free_rx_list(sc);
2595 }
2596
2597 int
urtwn_is_oactive(void * cookie)2598 urtwn_is_oactive(void *cookie)
2599 {
2600 struct urtwn_softc *sc = cookie;
2601
2602 return (TAILQ_EMPTY(&sc->tx_free_list));
2603 }
2604