1 /****************************************************************************** 2 3 Copyright (c) 2001-2019, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP 0x10A0 90 #define E1000_DEV_ID_82572EI_COPPER 0x107D 91 #define E1000_DEV_ID_82572EI_FIBER 0x107E 92 #define E1000_DEV_ID_82572EI_SERDES 0x107F 93 #define E1000_DEV_ID_82572EI 0x10B9 94 #define E1000_DEV_ID_82573E 0x108B 95 #define E1000_DEV_ID_82573E_IAMT 0x108C 96 #define E1000_DEV_ID_82573L 0x109A 97 #define E1000_DEV_ID_82574L 0x10D3 98 #define E1000_DEV_ID_82574LA 0x10F6 99 #define E1000_DEV_ID_82583V 0x150C 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 104 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 105 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 106 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 107 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 108 #define E1000_DEV_ID_ICH8_IFE 0x104C 109 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 110 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 111 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 112 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 113 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 114 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 115 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 116 #define E1000_DEV_ID_ICH9_BM 0x10E5 117 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 118 #define E1000_DEV_ID_ICH9_IFE 0x10C0 119 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 120 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 121 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 122 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 123 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 128 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 129 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 130 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 131 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 132 #define E1000_DEV_ID_PCH2_LV_V 0x1503 133 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 134 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 135 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 136 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 137 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 138 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 139 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 140 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 141 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 142 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 143 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 144 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 145 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 146 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 147 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 148 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 149 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 150 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 151 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 152 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 153 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 154 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 155 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 156 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 157 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 158 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 159 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 160 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 161 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 162 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 163 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 164 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 165 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 166 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 167 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 168 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 169 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 170 #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E 171 #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F 172 #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C 173 #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D 174 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 175 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 176 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 177 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 178 #define E1000_DEV_ID_82576 0x10C9 179 #define E1000_DEV_ID_82576_FIBER 0x10E6 180 #define E1000_DEV_ID_82576_SERDES 0x10E7 181 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 182 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 183 #define E1000_DEV_ID_82576_NS 0x150A 184 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 185 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 186 #define E1000_DEV_ID_82576_VF 0x10CA 187 #define E1000_DEV_ID_82576_VF_HV 0x152D 188 #define E1000_DEV_ID_I350_VF 0x1520 189 #define E1000_DEV_ID_I350_VF_HV 0x152F 190 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 191 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 192 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 193 #define E1000_DEV_ID_82580_COPPER 0x150E 194 #define E1000_DEV_ID_82580_FIBER 0x150F 195 #define E1000_DEV_ID_82580_SERDES 0x1510 196 #define E1000_DEV_ID_82580_SGMII 0x1511 197 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 198 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 199 #define E1000_DEV_ID_I350_COPPER 0x1521 200 #define E1000_DEV_ID_I350_FIBER 0x1522 201 #define E1000_DEV_ID_I350_SERDES 0x1523 202 #define E1000_DEV_ID_I350_SGMII 0x1524 203 #define E1000_DEV_ID_I350_DA4 0x1546 204 #define E1000_DEV_ID_I210_COPPER 0x1533 205 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 206 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 207 #define E1000_DEV_ID_I210_FIBER 0x1536 208 #define E1000_DEV_ID_I210_SERDES 0x1537 209 #define E1000_DEV_ID_I210_SGMII 0x1538 210 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 211 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 212 #define E1000_DEV_ID_I211_COPPER 0x1539 213 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 214 #define E1000_DEV_ID_I354_SGMII 0x1F41 215 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 216 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 217 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 218 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 219 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 220 221 #define E1000_REVISION_0 0 222 #define E1000_REVISION_1 1 223 #define E1000_REVISION_2 2 224 #define E1000_REVISION_3 3 225 #define E1000_REVISION_4 4 226 227 #define E1000_FUNC_0 0 228 #define E1000_FUNC_1 1 229 #define E1000_FUNC_2 2 230 #define E1000_FUNC_3 3 231 232 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 233 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 234 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 235 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 236 237 enum e1000_mac_type { 238 e1000_undefined = 0, 239 e1000_82542, 240 e1000_82543, 241 e1000_82544, 242 e1000_82540, 243 e1000_82545, 244 e1000_82545_rev_3, 245 e1000_82546, 246 e1000_82546_rev_3, 247 e1000_82541, 248 e1000_82541_rev_2, 249 e1000_82547, 250 e1000_82547_rev_2, 251 e1000_82571, 252 e1000_82572, 253 e1000_82573, 254 e1000_82574, 255 e1000_82583, 256 e1000_80003es2lan, 257 e1000_ich8lan, 258 e1000_ich9lan, 259 e1000_ich10lan, 260 e1000_pchlan, 261 e1000_pch2lan, 262 e1000_pch_lpt, 263 e1000_pch_spt, 264 e1000_pch_cnp, 265 e1000_82575, 266 e1000_82576, 267 e1000_82580, 268 e1000_i350, 269 e1000_i354, 270 e1000_i210, 271 e1000_i211, 272 e1000_vfadapt, 273 e1000_vfadapt_i350, 274 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 275 }; 276 277 enum e1000_media_type { 278 e1000_media_type_unknown = 0, 279 e1000_media_type_copper = 1, 280 e1000_media_type_fiber = 2, 281 e1000_media_type_internal_serdes = 3, 282 e1000_num_media_types 283 }; 284 285 enum e1000_nvm_type { 286 e1000_nvm_unknown = 0, 287 e1000_nvm_none, 288 e1000_nvm_eeprom_spi, 289 e1000_nvm_eeprom_microwire, 290 e1000_nvm_flash_hw, 291 e1000_nvm_invm, 292 e1000_nvm_flash_sw 293 }; 294 295 enum e1000_nvm_override { 296 e1000_nvm_override_none = 0, 297 e1000_nvm_override_spi_small, 298 e1000_nvm_override_spi_large, 299 e1000_nvm_override_microwire_small, 300 e1000_nvm_override_microwire_large 301 }; 302 303 enum e1000_phy_type { 304 e1000_phy_unknown = 0, 305 e1000_phy_none, 306 e1000_phy_m88, 307 e1000_phy_igp, 308 e1000_phy_igp_2, 309 e1000_phy_gg82563, 310 e1000_phy_igp_3, 311 e1000_phy_ife, 312 e1000_phy_bm, 313 e1000_phy_82578, 314 e1000_phy_82577, 315 e1000_phy_82579, 316 e1000_phy_i217, 317 e1000_phy_82580, 318 e1000_phy_vf, 319 e1000_phy_i210, 320 }; 321 322 enum e1000_bus_type { 323 e1000_bus_type_unknown = 0, 324 e1000_bus_type_pci, 325 e1000_bus_type_pcix, 326 e1000_bus_type_pci_express, 327 e1000_bus_type_reserved 328 }; 329 330 enum e1000_bus_speed { 331 e1000_bus_speed_unknown = 0, 332 e1000_bus_speed_33, 333 e1000_bus_speed_66, 334 e1000_bus_speed_100, 335 e1000_bus_speed_120, 336 e1000_bus_speed_133, 337 e1000_bus_speed_2500, 338 e1000_bus_speed_5000, 339 e1000_bus_speed_reserved 340 }; 341 342 enum e1000_bus_width { 343 e1000_bus_width_unknown = 0, 344 e1000_bus_width_pcie_x1, 345 e1000_bus_width_pcie_x2, 346 e1000_bus_width_pcie_x4 = 4, 347 e1000_bus_width_pcie_x8 = 8, 348 e1000_bus_width_32, 349 e1000_bus_width_64, 350 e1000_bus_width_reserved 351 }; 352 353 enum e1000_1000t_rx_status { 354 e1000_1000t_rx_status_not_ok = 0, 355 e1000_1000t_rx_status_ok, 356 e1000_1000t_rx_status_undefined = 0xFF 357 }; 358 359 enum e1000_rev_polarity { 360 e1000_rev_polarity_normal = 0, 361 e1000_rev_polarity_reversed, 362 e1000_rev_polarity_undefined = 0xFF 363 }; 364 365 enum e1000_fc_mode { 366 e1000_fc_none = 0, 367 e1000_fc_rx_pause, 368 e1000_fc_tx_pause, 369 e1000_fc_full, 370 e1000_fc_default = 0xFF 371 }; 372 373 enum e1000_ffe_config { 374 e1000_ffe_config_enabled = 0, 375 e1000_ffe_config_active, 376 e1000_ffe_config_blocked 377 }; 378 379 enum e1000_dsp_config { 380 e1000_dsp_config_disabled = 0, 381 e1000_dsp_config_enabled, 382 e1000_dsp_config_activated, 383 e1000_dsp_config_undefined = 0xFF 384 }; 385 386 enum e1000_ms_type { 387 e1000_ms_hw_default = 0, 388 e1000_ms_force_master, 389 e1000_ms_force_slave, 390 e1000_ms_auto 391 }; 392 393 enum e1000_smart_speed { 394 e1000_smart_speed_default = 0, 395 e1000_smart_speed_on, 396 e1000_smart_speed_off 397 }; 398 399 enum e1000_serdes_link_state { 400 e1000_serdes_link_down = 0, 401 e1000_serdes_link_autoneg_progress, 402 e1000_serdes_link_autoneg_complete, 403 e1000_serdes_link_forced_up 404 }; 405 406 #define __le16 u16 407 #define __le32 u32 408 #define __le64 u64 409 /* Receive Descriptor */ 410 struct e1000_rx_desc { 411 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 412 __le16 length; /* Length of data DMAed into data buffer */ 413 __le16 csum; /* Packet checksum */ 414 u8 status; /* Descriptor status */ 415 u8 errors; /* Descriptor Errors */ 416 __le16 special; 417 }; 418 419 /* Receive Descriptor - Extended */ 420 union e1000_rx_desc_extended { 421 struct { 422 __le64 buffer_addr; 423 __le64 reserved; 424 } read; 425 struct { 426 struct { 427 __le32 mrq; /* Multiple Rx Queues */ 428 union { 429 __le32 rss; /* RSS Hash */ 430 struct { 431 __le16 ip_id; /* IP id */ 432 __le16 csum; /* Packet Checksum */ 433 } csum_ip; 434 } hi_dword; 435 } lower; 436 struct { 437 __le32 status_error; /* ext status/error */ 438 __le16 length; 439 __le16 vlan; /* VLAN tag */ 440 } upper; 441 } wb; /* writeback */ 442 }; 443 444 #define MAX_PS_BUFFERS 4 445 446 /* Number of packet split data buffers (not including the header buffer) */ 447 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 448 449 /* Receive Descriptor - Packet Split */ 450 union e1000_rx_desc_packet_split { 451 struct { 452 /* one buffer for protocol header(s), three data buffers */ 453 __le64 buffer_addr[MAX_PS_BUFFERS]; 454 } read; 455 struct { 456 struct { 457 __le32 mrq; /* Multiple Rx Queues */ 458 union { 459 __le32 rss; /* RSS Hash */ 460 struct { 461 __le16 ip_id; /* IP id */ 462 __le16 csum; /* Packet Checksum */ 463 } csum_ip; 464 } hi_dword; 465 } lower; 466 struct { 467 __le32 status_error; /* ext status/error */ 468 __le16 length0; /* length of buffer 0 */ 469 __le16 vlan; /* VLAN tag */ 470 } middle; 471 struct { 472 __le16 header_status; 473 /* length of buffers 1-3 */ 474 __le16 length[PS_PAGE_BUFFERS]; 475 } upper; 476 __le64 reserved; 477 } wb; /* writeback */ 478 }; 479 480 /* Transmit Descriptor */ 481 struct e1000_tx_desc { 482 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 483 union { 484 __le32 data; 485 struct { 486 __le16 length; /* Data buffer length */ 487 u8 cso; /* Checksum offset */ 488 u8 cmd; /* Descriptor control */ 489 } flags; 490 } lower; 491 union { 492 __le32 data; 493 struct { 494 u8 status; /* Descriptor status */ 495 u8 css; /* Checksum start */ 496 __le16 special; 497 } fields; 498 } upper; 499 }; 500 501 /* Offload Context Descriptor */ 502 struct e1000_context_desc { 503 union { 504 __le32 ip_config; 505 struct { 506 u8 ipcss; /* IP checksum start */ 507 u8 ipcso; /* IP checksum offset */ 508 __le16 ipcse; /* IP checksum end */ 509 } ip_fields; 510 } lower_setup; 511 union { 512 __le32 tcp_config; 513 struct { 514 u8 tucss; /* TCP checksum start */ 515 u8 tucso; /* TCP checksum offset */ 516 __le16 tucse; /* TCP checksum end */ 517 } tcp_fields; 518 } upper_setup; 519 __le32 cmd_and_length; 520 union { 521 __le32 data; 522 struct { 523 u8 status; /* Descriptor status */ 524 u8 hdr_len; /* Header length */ 525 __le16 mss; /* Maximum segment size */ 526 } fields; 527 } tcp_seg_setup; 528 }; 529 530 /* Offload data descriptor */ 531 struct e1000_data_desc { 532 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 533 union { 534 __le32 data; 535 struct { 536 __le16 length; /* Data buffer length */ 537 u8 typ_len_ext; 538 u8 cmd; 539 } flags; 540 } lower; 541 union { 542 __le32 data; 543 struct { 544 u8 status; /* Descriptor status */ 545 u8 popts; /* Packet Options */ 546 __le16 special; 547 } fields; 548 } upper; 549 }; 550 551 /* Statistics counters collected by the MAC */ 552 struct e1000_hw_stats { 553 u64 crcerrs; 554 u64 algnerrc; 555 u64 symerrs; 556 u64 rxerrc; 557 u64 mpc; 558 u64 scc; 559 u64 ecol; 560 u64 mcc; 561 u64 latecol; 562 u64 colc; 563 u64 dc; 564 u64 tncrs; 565 u64 sec; 566 u64 cexterr; 567 u64 rlec; 568 u64 xonrxc; 569 u64 xontxc; 570 u64 xoffrxc; 571 u64 xofftxc; 572 u64 fcruc; 573 u64 prc64; 574 u64 prc127; 575 u64 prc255; 576 u64 prc511; 577 u64 prc1023; 578 u64 prc1522; 579 u64 gprc; 580 u64 bprc; 581 u64 mprc; 582 u64 gptc; 583 u64 gorc; 584 u64 gotc; 585 u64 rnbc; 586 u64 ruc; 587 u64 rfc; 588 u64 roc; 589 u64 rjc; 590 u64 mgprc; 591 u64 mgpdc; 592 u64 mgptc; 593 u64 tor; 594 u64 tot; 595 u64 tpr; 596 u64 tpt; 597 u64 ptc64; 598 u64 ptc127; 599 u64 ptc255; 600 u64 ptc511; 601 u64 ptc1023; 602 u64 ptc1522; 603 u64 mptc; 604 u64 bptc; 605 u64 tsctc; 606 u64 tsctfc; 607 u64 iac; 608 u64 icrxptc; 609 u64 icrxatc; 610 u64 ictxptc; 611 u64 ictxatc; 612 u64 ictxqec; 613 u64 ictxqmtc; 614 u64 icrxdmtc; 615 u64 icrxoc; 616 u64 cbtmpc; 617 u64 htdpmc; 618 u64 cbrdpc; 619 u64 cbrmpc; 620 u64 rpthc; 621 u64 hgptc; 622 u64 htcbdpc; 623 u64 hgorc; 624 u64 hgotc; 625 u64 lenerrs; 626 u64 scvpc; 627 u64 hrmpc; 628 u64 doosync; 629 u64 o2bgptc; 630 u64 o2bspc; 631 u64 b2ospc; 632 u64 b2ogprc; 633 }; 634 635 struct e1000_vf_stats { 636 u64 base_gprc; 637 u64 base_gptc; 638 u64 base_gorc; 639 u64 base_gotc; 640 u64 base_mprc; 641 u64 base_gotlbc; 642 u64 base_gptlbc; 643 u64 base_gorlbc; 644 u64 base_gprlbc; 645 646 u32 last_gprc; 647 u32 last_gptc; 648 u32 last_gorc; 649 u32 last_gotc; 650 u32 last_mprc; 651 u32 last_gotlbc; 652 u32 last_gptlbc; 653 u32 last_gorlbc; 654 u32 last_gprlbc; 655 656 u64 gprc; 657 u64 gptc; 658 u64 gorc; 659 u64 gotc; 660 u64 mprc; 661 u64 gotlbc; 662 u64 gptlbc; 663 u64 gorlbc; 664 u64 gprlbc; 665 }; 666 667 668 struct e1000_phy_stats { 669 u32 idle_errors; 670 u32 receive_errors; 671 }; 672 673 struct e1000_host_mng_dhcp_cookie { 674 u32 signature; 675 u8 status; 676 u8 reserved0; 677 u16 vlan_id; 678 u32 reserved1; 679 u16 reserved2; 680 u8 reserved3; 681 u8 checksum; 682 }; 683 684 /* Host Interface "Rev 1" */ 685 struct e1000_host_command_header { 686 u8 command_id; 687 u8 command_length; 688 u8 command_options; 689 u8 checksum; 690 }; 691 692 #define E1000_HI_MAX_DATA_LENGTH 252 693 struct e1000_host_command_info { 694 struct e1000_host_command_header command_header; 695 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 696 }; 697 698 /* Host Interface "Rev 2" */ 699 struct e1000_host_mng_command_header { 700 u8 command_id; 701 u8 checksum; 702 u16 reserved1; 703 u16 reserved2; 704 u16 command_length; 705 }; 706 707 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 708 struct e1000_host_mng_command_info { 709 struct e1000_host_mng_command_header command_header; 710 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 711 }; 712 713 #include "e1000_mac.h" 714 #include "e1000_phy.h" 715 #include "e1000_nvm.h" 716 #include "e1000_manage.h" 717 #include "e1000_mbx.h" 718 719 /* Function pointers for the MAC. */ 720 struct e1000_mac_operations { 721 s32 (*init_params)(struct e1000_hw *); 722 s32 (*id_led_init)(struct e1000_hw *); 723 s32 (*blink_led)(struct e1000_hw *); 724 bool (*check_mng_mode)(struct e1000_hw *); 725 s32 (*check_for_link)(struct e1000_hw *); 726 s32 (*cleanup_led)(struct e1000_hw *); 727 void (*clear_hw_cntrs)(struct e1000_hw *); 728 void (*clear_vfta)(struct e1000_hw *); 729 s32 (*get_bus_info)(struct e1000_hw *); 730 void (*set_lan_id)(struct e1000_hw *); 731 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 732 s32 (*led_on)(struct e1000_hw *); 733 s32 (*led_off)(struct e1000_hw *); 734 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 735 s32 (*reset_hw)(struct e1000_hw *); 736 s32 (*init_hw)(struct e1000_hw *); 737 void (*shutdown_serdes)(struct e1000_hw *); 738 void (*power_up_serdes)(struct e1000_hw *); 739 s32 (*setup_link)(struct e1000_hw *); 740 s32 (*setup_physical_interface)(struct e1000_hw *); 741 s32 (*setup_led)(struct e1000_hw *); 742 void (*write_vfta)(struct e1000_hw *, u32, u32); 743 void (*config_collision_dist)(struct e1000_hw *); 744 int (*rar_set)(struct e1000_hw *, u8*, u32); 745 s32 (*read_mac_addr)(struct e1000_hw *); 746 s32 (*validate_mdi_setting)(struct e1000_hw *); 747 s32 (*set_obff_timer)(struct e1000_hw *, u32); 748 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 749 void (*release_swfw_sync)(struct e1000_hw *, u16); 750 }; 751 752 /* When to use various PHY register access functions: 753 * 754 * Func Caller 755 * Function Does Does When to use 756 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 757 * X_reg L,P,A n/a for simple PHY reg accesses 758 * X_reg_locked P,A L for multiple accesses of different regs 759 * on different pages 760 * X_reg_page A L,P for multiple accesses of different regs 761 * on the same page 762 * 763 * Where X=[read|write], L=locking, P=sets page, A=register access 764 * 765 */ 766 struct e1000_phy_operations { 767 s32 (*init_params)(struct e1000_hw *); 768 s32 (*acquire)(struct e1000_hw *); 769 s32 (*cfg_on_link_up)(struct e1000_hw *); 770 s32 (*check_polarity)(struct e1000_hw *); 771 s32 (*check_reset_block)(struct e1000_hw *); 772 s32 (*commit)(struct e1000_hw *); 773 s32 (*force_speed_duplex)(struct e1000_hw *); 774 s32 (*get_cfg_done)(struct e1000_hw *hw); 775 s32 (*get_cable_length)(struct e1000_hw *); 776 s32 (*get_info)(struct e1000_hw *); 777 s32 (*set_page)(struct e1000_hw *, u16); 778 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 779 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 780 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 781 void (*release)(struct e1000_hw *); 782 s32 (*reset)(struct e1000_hw *); 783 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 784 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 785 s32 (*write_reg)(struct e1000_hw *, u32, u16); 786 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 787 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 788 void (*power_up)(struct e1000_hw *); 789 void (*power_down)(struct e1000_hw *); 790 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 791 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 792 }; 793 794 /* Function pointers for the NVM. */ 795 struct e1000_nvm_operations { 796 s32 (*init_params)(struct e1000_hw *); 797 s32 (*acquire)(struct e1000_hw *); 798 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 799 void (*release)(struct e1000_hw *); 800 void (*reload)(struct e1000_hw *); 801 s32 (*update)(struct e1000_hw *); 802 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 803 s32 (*validate)(struct e1000_hw *); 804 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 805 }; 806 807 struct e1000_mac_info { 808 struct e1000_mac_operations ops; 809 u8 addr[ETH_ADDR_LEN]; 810 u8 perm_addr[ETH_ADDR_LEN]; 811 812 enum e1000_mac_type type; 813 814 u32 collision_delta; 815 u32 ledctl_default; 816 u32 ledctl_mode1; 817 u32 ledctl_mode2; 818 u32 mc_filter_type; 819 u32 tx_packet_delta; 820 u32 txcw; 821 822 u16 current_ifs_val; 823 u16 ifs_max_val; 824 u16 ifs_min_val; 825 u16 ifs_ratio; 826 u16 ifs_step_size; 827 u16 mta_reg_count; 828 u16 uta_reg_count; 829 830 /* Maximum size of the MTA register table in all supported adapters */ 831 #define MAX_MTA_REG 128 832 u32 mta_shadow[MAX_MTA_REG]; 833 u16 rar_entry_count; 834 835 u8 forced_speed_duplex; 836 837 bool adaptive_ifs; 838 bool has_fwsm; 839 bool arc_subsystem_valid; 840 bool asf_firmware_present; 841 bool autoneg; 842 bool autoneg_failed; 843 bool get_link_status; 844 bool in_ifs_mode; 845 bool report_tx_early; 846 enum e1000_serdes_link_state serdes_link_state; 847 bool serdes_has_link; 848 bool tx_pkt_filtering; 849 u32 max_frame_size; 850 }; 851 852 struct e1000_phy_info { 853 struct e1000_phy_operations ops; 854 enum e1000_phy_type type; 855 856 enum e1000_1000t_rx_status local_rx; 857 enum e1000_1000t_rx_status remote_rx; 858 enum e1000_ms_type ms_type; 859 enum e1000_ms_type original_ms_type; 860 enum e1000_rev_polarity cable_polarity; 861 enum e1000_smart_speed smart_speed; 862 863 u32 addr; 864 u32 id; 865 u32 reset_delay_us; /* in usec */ 866 u32 revision; 867 868 enum e1000_media_type media_type; 869 870 u16 autoneg_advertised; 871 u16 autoneg_mask; 872 u16 cable_length; 873 u16 max_cable_length; 874 u16 min_cable_length; 875 876 u8 mdix; 877 878 bool disable_polarity_correction; 879 bool is_mdix; 880 bool polarity_correction; 881 bool speed_downgraded; 882 bool autoneg_wait_to_complete; 883 }; 884 885 struct e1000_nvm_info { 886 struct e1000_nvm_operations ops; 887 enum e1000_nvm_type type; 888 enum e1000_nvm_override override; 889 890 u32 flash_bank_size; 891 u32 flash_base_addr; 892 893 u16 word_size; 894 u16 delay_usec; 895 u16 address_bits; 896 u16 opcode_bits; 897 u16 page_size; 898 }; 899 900 struct e1000_bus_info { 901 enum e1000_bus_type type; 902 enum e1000_bus_speed speed; 903 enum e1000_bus_width width; 904 905 u16 func; 906 u16 pci_cmd_word; 907 }; 908 909 struct e1000_fc_info { 910 u32 high_water; /* Flow control high-water mark */ 911 u32 low_water; /* Flow control low-water mark */ 912 u16 pause_time; /* Flow control pause timer */ 913 u16 refresh_time; /* Flow control refresh timer */ 914 bool send_xon; /* Flow control send XON */ 915 bool strict_ieee; /* Strict IEEE mode */ 916 enum e1000_fc_mode current_mode; /* FC mode in effect */ 917 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 918 }; 919 920 struct e1000_dev_spec_82541 { 921 enum e1000_dsp_config dsp_config; 922 enum e1000_ffe_config ffe_config; 923 u16 spd_default; 924 bool phy_init_script; 925 }; 926 927 struct e1000_dev_spec_82542 { 928 bool dma_fairness; 929 }; 930 931 struct e1000_dev_spec_82543 { 932 u32 tbi_compatibility; 933 bool dma_fairness; 934 bool init_phy_disabled; 935 }; 936 937 struct e1000_dev_spec_82571 { 938 bool laa_is_present; 939 u32 smb_counter; 940 }; 941 942 struct e1000_dev_spec_80003es2lan { 943 bool mdic_wa_enable; 944 }; 945 946 struct e1000_shadow_ram { 947 u16 value; 948 bool modified; 949 }; 950 951 #define E1000_SHADOW_RAM_WORDS 2048 952 953 /* I218 PHY Ultra Low Power (ULP) states */ 954 enum e1000_ulp_state { 955 e1000_ulp_state_unknown, 956 e1000_ulp_state_off, 957 e1000_ulp_state_on, 958 }; 959 960 struct e1000_mbx_operations { 961 s32 (*init_params)(struct e1000_hw *hw); 962 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 963 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 964 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 965 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 966 s32 (*check_for_msg)(struct e1000_hw *, u16); 967 s32 (*check_for_ack)(struct e1000_hw *, u16); 968 s32 (*check_for_rst)(struct e1000_hw *, u16); 969 }; 970 971 struct e1000_mbx_stats { 972 u32 msgs_tx; 973 u32 msgs_rx; 974 975 u32 acks; 976 u32 reqs; 977 u32 rsts; 978 }; 979 980 struct e1000_mbx_info { 981 struct e1000_mbx_operations ops; 982 struct e1000_mbx_stats stats; 983 u32 timeout; 984 u32 usec_delay; 985 u16 size; 986 }; 987 988 struct e1000_dev_spec_82575 { 989 bool sgmii_active; 990 bool global_device_reset; 991 bool eee_disable; 992 bool module_plugged; 993 bool clear_semaphore_once; 994 u32 mtu; 995 struct sfp_e1000_flags eth_flags; 996 u8 media_port; 997 bool media_changed; 998 }; 999 1000 struct e1000_dev_spec_vf { 1001 u32 vf_number; 1002 u32 v2p_mailbox; 1003 }; 1004 1005 struct e1000_dev_spec_ich8lan { 1006 bool kmrn_lock_loss_workaround_enabled; 1007 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 1008 bool nvm_k1_enabled; 1009 bool disable_k1_off; 1010 bool eee_disable; 1011 u16 eee_lp_ability; 1012 enum e1000_ulp_state ulp_state; 1013 bool ulp_capability_disabled; 1014 bool during_suspend_flow; 1015 bool during_dpg_exit; 1016 }; 1017 1018 struct e1000_hw { 1019 void *back; 1020 1021 u8 *hw_addr; 1022 u8 *flash_address; 1023 unsigned long io_base; 1024 1025 struct e1000_mac_info mac; 1026 struct e1000_fc_info fc; 1027 struct e1000_phy_info phy; 1028 struct e1000_nvm_info nvm; 1029 struct e1000_bus_info bus; 1030 struct e1000_mbx_info mbx; 1031 struct e1000_host_mng_dhcp_cookie mng_cookie; 1032 1033 union { 1034 struct e1000_dev_spec_82541 _82541; 1035 struct e1000_dev_spec_82542 _82542; 1036 struct e1000_dev_spec_82543 _82543; 1037 struct e1000_dev_spec_82571 _82571; 1038 struct e1000_dev_spec_80003es2lan _80003es2lan; 1039 struct e1000_dev_spec_ich8lan ich8lan; 1040 struct e1000_dev_spec_82575 _82575; 1041 struct e1000_dev_spec_vf vf; 1042 } dev_spec; 1043 1044 u16 device_id; 1045 u16 subsystem_vendor_id; 1046 u16 subsystem_device_id; 1047 u16 vendor_id; 1048 1049 u8 revision_id; 1050 }; 1051 1052 #include "e1000_82541.h" 1053 #include "e1000_82543.h" 1054 #include "e1000_82571.h" 1055 #include "e1000_80003es2lan.h" 1056 #include "e1000_ich8lan.h" 1057 #include "e1000_82575.h" 1058 #include "e1000_i210.h" 1059 1060 /* These functions must be implemented by drivers */ 1061 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1062 void e1000_pci_set_mwi(struct e1000_hw *hw); 1063 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1064 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1065 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1066 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1067 1068 #endif 1069