| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | cvita_hdr_encoder.v | 14 input [63:0] vita_time, port
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| H A D | cvita_hdr_decoder.v | 14 output [63:0] vita_time port
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| H A D | cvita_hdr_modify.v | 20 input use_vita_time, input [63:0] vita_time port
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| H A D | cvita_hdr_parser.v | 19 output [63:0] vita_time, port
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| H A D | axi_async_stream.v | 95 wire [63:0] vita_time; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/timing/ |
| H A D | time_transfer_tb.v | 40 reg [63:0] vita_time = 0; register
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| H A D | time_sender.v | 22 input [63:0] vita_time, port
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| H A D | time_receiver.v | 21 output reg [63:0] vita_time, port
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| H A D | time_64bit.v | 26 output reg [63:0] vita_time, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/ |
| H A D | context_packet_gen.v | 14 input [63:0] vita_time, port
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| H A D | new_rx_tb.v | 29 reg [63:0] vita_time; register
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| H A D | tx_responder.v | 17 input [63:0] vita_time, port
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| H A D | new_tx_control_tb.v | 103 reg [63:0] vita_time; register
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| H A D | new_tx_control.v | 14 input [63:0] vita_time, port
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| H A D | new_rx_control.v | 20 input [63:0] vita_time, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/timing/ |
| H A D | timekeeper_legacy.v | 16 output reg [63:0] vita_time, output reg [63:0] vita_time_lastpps, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control_200/ |
| H A D | radio_ctrl_proc_tb.v | 26 reg [63:0] vita_time = 64'd0; register
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| H A D | radio_ctrl_proc.v | 28 input [63:0] vita_time, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/vrt/ |
| H A D | gen_context_pkt.v | 26 input [63:0] vita_time, port
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| H A D | vita_rx_tb.v | 40 wire [63:0] vita_time; net
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| H A D | vita_rx_chain.v | 28 input [63:0] vita_time, port
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| H A D | vita_tx_control.v | 25 input [63:0] vita_time, port
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| H A D | vita_tx_tb.v | 43 wire [63:0] vita_time; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | settings_bus_timed_2clk.v | 26 input [63:0] vita_time, // Current timebase time port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/tools/uhd_dump/ |
| H A D | uhd_dump.h | 198 struct vita_time { struct
199 u64 time;
|