1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4 */
5
6 #include "enic.h"
7 #include "vnic_dev.h"
8 #include "vnic_wq.h"
9
vnic_wq_init_start(struct vnic_wq * wq,unsigned int cq_index,unsigned int fetch_index,unsigned int posted_index,unsigned int error_interrupt_enable,unsigned int error_interrupt_offset)10 void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
11 unsigned int fetch_index, unsigned int posted_index,
12 unsigned int error_interrupt_enable,
13 unsigned int error_interrupt_offset)
14 {
15 u64 paddr;
16 unsigned int count = wq->ring.desc_count;
17
18 paddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET;
19 ENIC_BUS_WRITE_8(wq->ctrl, TX_RING_BASE, paddr);
20 ENIC_BUS_WRITE_4(wq->ctrl, TX_RING_SIZE, count);
21 ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, fetch_index);
22 ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, posted_index);
23 ENIC_BUS_WRITE_4(wq->ctrl, TX_CQ_INDEX, cq_index);
24 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_ENABLE, error_interrupt_enable);
25 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_OFFSET, error_interrupt_offset);
26 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0);
27
28 wq->head_idx = fetch_index;
29 wq->tail_idx = wq->head_idx;
30 }
31
vnic_wq_init(struct vnic_wq * wq,unsigned int cq_index,unsigned int error_interrupt_enable,unsigned int error_interrupt_offset)32 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
33 unsigned int error_interrupt_enable,
34 unsigned int error_interrupt_offset)
35 {
36 vnic_wq_init_start(wq, cq_index, 0, 0,
37 error_interrupt_enable,
38 error_interrupt_offset);
39 wq->cq_pend = 0;
40 wq->last_completed_index = 0;
41 }
42
vnic_wq_error_status(struct vnic_wq * wq)43 unsigned int vnic_wq_error_status(struct vnic_wq *wq)
44 {
45 return ENIC_BUS_READ_4(wq->ctrl, TX_ERROR_STATUS);
46 }
47
vnic_wq_enable(struct vnic_wq * wq)48 void vnic_wq_enable(struct vnic_wq *wq)
49 {
50 ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 1);
51 }
52
vnic_wq_disable(struct vnic_wq * wq)53 int vnic_wq_disable(struct vnic_wq *wq)
54 {
55 unsigned int wait;
56
57 ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 0);
58
59 /* Wait for HW to ACK disable request */
60 for (wait = 0; wait < 1000; wait++) {
61 if (!(ENIC_BUS_READ_4(wq->ctrl, TX_RUNNING)))
62 return 0;
63 udelay(10);
64 }
65
66 pr_err("Failed to disable WQ[%d]\n", wq->index);
67
68 return -ETIMEDOUT;
69 }
70
vnic_wq_clean(struct vnic_wq * wq)71 void vnic_wq_clean(struct vnic_wq *wq)
72 {
73 unsigned int to_clean = wq->tail_idx;
74
75 while (vnic_wq_desc_used(wq) > 0) {
76 to_clean = buf_idx_incr(wq->ring.desc_count, to_clean);
77 wq->ring.desc_avail++;
78 }
79
80 wq->head_idx = 0;
81 wq->tail_idx = 0;
82 wq->last_completed_index = 0;
83
84 ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, 0);
85 ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, 0);
86 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0);
87
88 vnic_dev_clear_desc_ring(&wq->ring);
89 }
90