xref: /linux/drivers/hwmon/nct6775.h (revision 22558934)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef __HWMON_NCT6775_H__
3 #define __HWMON_NCT6775_H__
4 
5 #include <linux/types.h>
6 
7 enum kinds { nct6106, nct6116, nct6775, nct6776, nct6779, nct6791, nct6792,
8 	     nct6793, nct6795, nct6796, nct6797, nct6798, nct6799 };
9 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
10 
11 #define NUM_TEMP	12	/* Max number of temp attribute sets w/ limits*/
12 #define NUM_TEMP_FIXED	6	/* Max number of fixed temp attribute sets */
13 #define NUM_TSI_TEMP	8	/* Max number of TSI temp register pairs */
14 
15 #define NUM_REG_ALARM	7	/* Max number of alarm registers */
16 #define NUM_REG_BEEP	5	/* Max number of beep registers */
17 
18 #define NUM_FAN		7
19 #define NUM_IN		18
20 
21 struct nct6775_data {
22 	int addr;	/* IO base of hw monitor block */
23 	int sioreg;	/* SIO register address */
24 	enum kinds kind;
25 	const char *name;
26 
27 	const struct attribute_group *groups[7];
28 	u8 num_groups;
29 
30 	u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
31 				    * 3=temp_crit, 4=temp_lcrit
32 				    */
33 	u8 temp_src[NUM_TEMP];
34 	u16 reg_temp_config[NUM_TEMP];
35 	const char * const *temp_label;
36 	u32 temp_mask;
37 	u32 virt_temp_mask;
38 
39 	u16 REG_CONFIG;
40 	u16 REG_VBAT;
41 	u16 REG_DIODE;
42 	u8 DIODE_MASK;
43 
44 	const s8 *ALARM_BITS;
45 	const s8 *BEEP_BITS;
46 
47 	const u16 *REG_VIN;
48 	const u16 *REG_IN_MINMAX[2];
49 
50 	const u16 *REG_TARGET;
51 	const u16 *REG_FAN;
52 	const u16 *REG_FAN_MODE;
53 	const u16 *REG_FAN_MIN;
54 	const u16 *REG_FAN_PULSES;
55 	const u16 *FAN_PULSE_SHIFT;
56 	const u16 *REG_FAN_TIME[3];
57 
58 	const u16 *REG_TOLERANCE_H;
59 
60 	const u8 *REG_PWM_MODE;
61 	const u8 *PWM_MODE_MASK;
62 
63 	const u16 *REG_PWM[7];	/* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
64 				 * [3]=pwm_max, [4]=pwm_step,
65 				 * [5]=weight_duty_step, [6]=weight_duty_base
66 				 */
67 	const u16 *REG_PWM_READ;
68 
69 	const u16 *REG_CRITICAL_PWM_ENABLE;
70 	u8 CRITICAL_PWM_ENABLE_MASK;
71 	const u16 *REG_CRITICAL_PWM;
72 
73 	const u16 *REG_AUTO_TEMP;
74 	const u16 *REG_AUTO_PWM;
75 
76 	const u16 *REG_CRITICAL_TEMP;
77 	const u16 *REG_CRITICAL_TEMP_TOLERANCE;
78 
79 	const u16 *REG_TEMP_SOURCE;	/* temp register sources */
80 	const u16 *REG_TEMP_SEL;
81 	const u16 *REG_WEIGHT_TEMP_SEL;
82 	const u16 *REG_WEIGHT_TEMP[3];	/* 0=base, 1=tolerance, 2=step */
83 
84 	const u16 *REG_TEMP_OFFSET;
85 
86 	const u16 *REG_ALARM;
87 	const u16 *REG_BEEP;
88 
89 	const u16 *REG_TSI_TEMP;
90 
91 	unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
92 	unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
93 
94 	struct mutex update_lock;
95 	bool valid;		/* true if following fields are valid */
96 	unsigned long last_updated;	/* In jiffies */
97 
98 	/* Register values */
99 	u8 bank;		/* current register bank */
100 	u8 in_num;		/* number of in inputs we have */
101 	u8 in[NUM_IN][3];	/* [0]=in, [1]=in_max, [2]=in_min */
102 	const u16 *scale_in;	/* internal scaling factors */
103 	unsigned int rpm[NUM_FAN];
104 	u16 fan_min[NUM_FAN];
105 	u8 fan_pulses[NUM_FAN];
106 	u8 fan_div[NUM_FAN];
107 	u8 has_pwm;
108 	u8 has_fan;		/* some fan inputs can be disabled */
109 	u8 has_fan_min;		/* some fans don't have min register */
110 	bool has_fan_div;
111 
112 	u8 num_temp_alarms;	/* 2, 3, or 6 */
113 	u8 num_temp_beeps;	/* 2, 3, or 6 */
114 	u8 temp_fixed_num;	/* 3 or 6 */
115 	u8 temp_type[NUM_TEMP_FIXED];
116 	s8 temp_offset[NUM_TEMP_FIXED];
117 	s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
118 				* 3=temp_crit, 4=temp_lcrit
119 				*/
120 	s16 tsi_temp[NUM_TSI_TEMP];
121 	u64 alarms;
122 	u64 beeps;
123 
124 	u8 pwm_num;	/* number of pwm */
125 	u8 pwm_mode[NUM_FAN];	/* 0->DC variable voltage,
126 				 * 1->PWM variable duty cycle
127 				 */
128 	enum pwm_enable pwm_enable[NUM_FAN];
129 			/* 0->off
130 			 * 1->manual
131 			 * 2->thermal cruise mode (also called SmartFan I)
132 			 * 3->fan speed cruise mode
133 			 * 4->SmartFan III
134 			 * 5->enhanced variable thermal cruise (SmartFan IV)
135 			 */
136 	u8 pwm[7][NUM_FAN];	/* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
137 				 * [3]=pwm_max, [4]=pwm_step,
138 				 * [5]=weight_duty_step, [6]=weight_duty_base
139 				 */
140 
141 	u8 target_temp[NUM_FAN];
142 	u8 target_temp_mask;
143 	u32 target_speed[NUM_FAN];
144 	u32 target_speed_tolerance[NUM_FAN];
145 	u8 speed_tolerance_limit;
146 
147 	u8 temp_tolerance[2][NUM_FAN];
148 	u8 tolerance_mask;
149 
150 	u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
151 
152 	/* Automatic fan speed control registers */
153 	int auto_pwm_num;
154 	u8 auto_pwm[NUM_FAN][7];
155 	u8 auto_temp[NUM_FAN][7];
156 	u8 pwm_temp_sel[NUM_FAN];
157 	u8 pwm_weight_temp_sel[NUM_FAN];
158 	u8 weight_temp[3][NUM_FAN];	/* 0->temp_step, 1->temp_step_tol,
159 					 * 2->temp_base
160 					 */
161 
162 	u8 vid;
163 	u8 vrm;
164 
165 	bool have_vid;
166 
167 	u16 have_temp;
168 	u16 have_temp_fixed;
169 	u16 have_tsi_temp;
170 	u32 have_in;
171 
172 	/* Remember extra register values over suspend/resume */
173 	u8 vbat;
174 	u8 fandiv1;
175 	u8 fandiv2;
176 	u8 sio_reg_enable;
177 
178 	struct regmap *regmap;
179 	bool read_only;
180 
181 	/* driver-specific (platform, i2c) initialization hook and data */
182 	int (*driver_init)(struct nct6775_data *data);
183 	void *driver_data;
184 };
185 
nct6775_read_value(struct nct6775_data * data,u16 reg,u16 * value)186 static inline int nct6775_read_value(struct nct6775_data *data, u16 reg, u16 *value)
187 {
188 	unsigned int tmp;
189 	int ret = regmap_read(data->regmap, reg, &tmp);
190 
191 	if (!ret)
192 		*value = tmp;
193 	return ret;
194 }
195 
nct6775_write_value(struct nct6775_data * data,u16 reg,u16 value)196 static inline int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
197 {
198 	return regmap_write(data->regmap, reg, value);
199 }
200 
201 struct nct6775_data *nct6775_update_device(struct device *dev);
202 
203 bool nct6775_reg_is_word_sized(struct nct6775_data *data, u16 reg);
204 int nct6775_probe(struct device *dev, struct nct6775_data *data,
205 		  const struct regmap_config *regmapcfg);
206 
207 ssize_t nct6775_show_alarm(struct device *dev, struct device_attribute *attr, char *buf);
208 ssize_t nct6775_show_beep(struct device *dev, struct device_attribute *attr, char *buf);
209 ssize_t nct6775_store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
210 			   size_t count);
211 
nct6775_write_temp(struct nct6775_data * data,u16 reg,u16 value)212 static inline int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
213 {
214 	if (!nct6775_reg_is_word_sized(data, reg))
215 		value >>= 8;
216 	return nct6775_write_value(data, reg, value);
217 }
218 
nct6775_attr_mode(struct nct6775_data * data,struct attribute * attr)219 static inline umode_t nct6775_attr_mode(struct nct6775_data *data, struct attribute *attr)
220 {
221 	return data->read_only ? (attr->mode & ~0222) : attr->mode;
222 }
223 
224 static inline int
nct6775_add_attr_group(struct nct6775_data * data,const struct attribute_group * group)225 nct6775_add_attr_group(struct nct6775_data *data, const struct attribute_group *group)
226 {
227 	/* Need to leave a NULL terminator at the end of data->groups */
228 	if (data->num_groups == ARRAY_SIZE(data->groups) - 1)
229 		return -ENOBUFS;
230 
231 	data->groups[data->num_groups++] = group;
232 	return 0;
233 }
234 
235 #define NCT6775_REG_BANK	0x4E
236 #define NCT6775_REG_CONFIG	0x40
237 
238 #define NCT6775_REG_FANDIV1		0x506
239 #define NCT6775_REG_FANDIV2		0x507
240 
241 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE	0x28
242 
243 /*
244  * ALARM_BITS and BEEP_BITS store bit-index for the mask of the registers
245  * loaded into data->alarm and data->beep.
246  *
247  * Every input register (IN/TEMP/FAN) must have a corresponding
248  *   ALARM/BEEP bit at the same index BITS[BASE + index]
249  * Set value to -1 to disable the visibility of that '*_alarm' attribute and
250  * to pad the bits until the next BASE
251  *
252  * Beep has an additional GLOBAL_BEEP_ENABLE bit
253  */
254 #define VIN_ALARM_BASE		 0
255 #define FAN_ALARM_BASE		24
256 #define TEMP_ALARM_BASE		36
257 #define INTRUSION_ALARM_BASE	48
258 #define BEEP_ENABLE_BASE	50
259 
260 #define NUM_ALARM_BITS		(INTRUSION_ALARM_BASE + 4)
261 #define NUM_BEEP_BITS		(BEEP_ENABLE_BASE + 1)
262 
263 /*
264  * Not currently used:
265  * REG_MAN_ID has the value 0x5ca3 for all supported chips.
266  * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
267  * REG_MAN_ID is at port 0x4f
268  * REG_CHIP_ID is at port 0x58
269  */
270 
271 #endif /* __HWMON_NCT6775_H__ */
272