1 /*
2 * Copyright (c) 2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_hcp_cmdpar.h
24 //! \brief MHW command parameters
25 //! \details
26 //!
27
28 #ifndef __MHW_VDBOX_HCP_CMDPAR_H__
29 #define __MHW_VDBOX_HCP_CMDPAR_H__
30
31 #include <functional>
32 #include "codec_def_decode_hevc.h"
33 #include "codec_def_encode_hevc.h"
34 #include "mhw_vdbox.h"
35 #include "mhw_vdbox_cmdpar.h"
36
37 #ifdef IGFX_HCP_INTERFACE_EXT_SUPPORT
38 #include "mhw_vdbox_hcp_cmdpar_ext.h"
39 #define __MHW_VDBOX_HCP_WRAPPER(STUFF)
40 #define __MHW_VDBOX_HCP_WRAPPER_EXT(STUFF) STUFF
41 #else
42 #define __MHW_VDBOX_HCP_WRAPPER(STUFF) STUFF
43 #define __MHW_VDBOX_HCP_WRAPPER_EXT(STUFF)
44 #endif
45
46 namespace mhw
47 {
48 namespace vdbox
49 {
50 namespace hcp
51 {
52 enum class SURFACE_FORMAT
53 {
54 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details
55 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details
56 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details
57 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details
58 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details
59 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details
60 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details
61 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details
62 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210
63 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details
64 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details
65 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details
66 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details
67 SURFACE_FORMAT_P010 = 13, //!< No additional details
68 SURFACE_FORMAT_P016 = 14, //!< No additional details
69 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details
70 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details
71 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
72 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
73 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
74 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma.
75 };
76
77 enum class HCP_INTERNAL_BUFFER_TYPE
78 {
79 DBLK_LINE = 0x0,
80 DBLK_TILE_LINE,
81 DBLK_TILE_COL,
82 MV_UP_RT_COL,
83 META_LINE,
84 META_TILE_LINE,
85 META_TILE_COL,
86 TR_NBR,
87 SAO_LINE,
88 SAO_TILE_LINE,
89 SAO_TILE_COL,
90 HSSE_RS,
91 HSAO_RS,
92 CURR_MV_TEMPORAL,
93 COLL_MV_TEMPORAL,
94 SLC_STATE_STREAMOUT,
95 CABAC_STREAMOUT,
96 MV_UP_RIGHT_COL,
97 INTRA_PRED_UP_RIGHT_COL,
98 INTRA_PRED_LFT_RECON_COL,
99 SEGMENT_ID,
100 HVD_LINE,
101 HVD_TILE
102 };
103
104 struct HcpMmioRegisters
105 {
106 uint32_t watchdogCountCtrlOffset;
107 uint32_t watchdogCountThresholdOffset;
108 uint32_t hcpDebugFEStreamOutSizeRegOffset;
109 uint32_t hcpEncImageStatusMaskRegOffset;
110 uint32_t hcpEncImageStatusCtrlRegOffset;
111 uint32_t hcpEncBitstreamBytecountFrameRegOffset;
112 uint32_t hcpEncBitstreamSeBitcountFrameRegOffset;
113 uint32_t hcpEncBitstreamBytecountFrameNoHeaderRegOffset;
114 uint32_t hcpEncQpStatusCountRegOffset;
115 uint32_t hcpEncSliceCountRegOffset;
116 uint32_t hcpEncVdencModeTimerRegOffset;
117 uint32_t hcpVp9EncBitstreamBytecountFrameRegOffset;
118 uint32_t hcpVp9EncBitstreamBytecountFrameNoHeaderRegOffset;
119 uint32_t hcpVp9EncImageStatusMaskRegOffset;
120 uint32_t hcpVp9EncImageStatusCtrlRegOffset;
121 uint32_t csEngineIdOffset;
122 uint32_t hcpDecStatusRegOffset;
123 uint32_t hcpCabacStatusRegOffset;
124 uint32_t hcpFrameCrcRegOffset;
125 };
126
127 struct HcpBufferSizePar
128 {
129 HCP_INTERNAL_BUFFER_TYPE bufferType;
130 uint8_t ucMaxBitDepth;
131 uint8_t ucChromaFormat;
132 uint32_t dwCtbLog2SizeY;
133 uint32_t dwPicWidth;
134 uint32_t dwPicHeight;
135 uint32_t dwMaxFrameSize;
136 };
137
138 struct HcpVdboxRowStorePar
139 {
140 uint32_t Mode;
141 uint32_t dwPicWidth;
142 uint32_t bMbaff;
143 bool bIsFrame;
144 uint8_t ucBitDepthMinus8;
145 uint8_t ucChromaFormat;
146 uint8_t ucLCUSize;
147 };
148
149 static constexpr uint32_t MAX_REF_FRAME_NUM = 15;
150
_MHW_PAR_T(HCP_PIC_STATE)151 struct _MHW_PAR_T(HCP_PIC_STATE)
152 {
153 uint16_t framewidthinmincbminus1 = 0;
154 bool transformSkipEnabled = false;
155 uint16_t frameheightinmincbminus1 = 0;
156 uint8_t mincusize = 0;
157 uint8_t ctbsizeLcusize = 0;
158 uint8_t maxtusize = 0;
159 uint8_t mintusize = 0;
160 bool sampleAdaptiveOffsetEnabled = false;
161 bool cuQpDeltaEnabledFlag = false;
162 uint8_t diffCuQpDeltaDepth = 0;
163 bool pcmLoopFilterDisableFlag = false;
164 bool weightedPredFlag = false;
165 bool weightedBipredFlag = false;
166 bool ampEnabledFlag = false;
167 bool transquantBypassEnableFlag = false;
168 bool strongIntraSmoothingEnableFlag = false;
169 uint8_t picCbQpOffset = 0;
170 uint8_t picCrQpOffset = 0;
171 uint8_t maxTransformHierarchyDepthIntra = 0;
172 uint8_t maxTransformHierarchyDepthInter = 0;
173 uint8_t pcmSampleBitDepthChromaMinus1 = 0;
174 uint8_t pcmSampleBitDepthLumaMinus1 = 0;
175 uint8_t bitDepthChromaMinus8 = 0;
176 uint8_t bitDepthLumaMinus8 = 0;
177 uint16_t lcuMaxBitsizeAllowed = 0;
178 uint8_t lcuMaxBitSizeAllowedMsb2its = 0;
179 bool rdoqEnable = false;
180 bool sseEnable = true;
181 bool rhodomainRateControlEnable = true;
182 uint8_t rhodomainframelevelqp = 0;
183 bool fractionalQpAdjustmentEnable = true;
184 bool pakDynamicSliceModeEnable = false;
185 uint8_t slicePicParameterSetId = false;
186 bool nalunittypeflag = false;
187 bool noOutputOfPriorPicsFlag = false;
188 uint32_t sliceSizeThresholdInBytes = 0;
189 uint32_t targetSliceSizeInBytes = 0;
190 bool tilesEnabledFlag = false;
191 uint8_t chromaSubsampling = 0;
192 bool loopFilterAcrossTilesEnabled = false;
193 bool intratucountbasedrdoqdisable = false;
194 uint16_t rdoqintratuthreshold = 0;
195 bool intraBoundaryFilteringDisabledFlag = false;
196 uint8_t motionVectorResolutionControlIdc = 0;
197 bool ppsCurrPicRefEnabledFlag = false;
198 uint8_t ibcMotionCompensationBufferReferenceIdc = 0;
199 uint8_t ibcConfiguration = 0;
200 bool paletteModeEnabledFlag = 0;
201 uint8_t paletteMaxSize = 0;
202 uint8_t deltaPaletteMaxPredictorSize = 0;
203 uint8_t lumaBitDepthEntryMinus8 = 0;
204 uint8_t chromaBitDepthEntryMinus8 = 0;
205 bool partialFrameUpdateMode = false;
206 bool temporalMvPredDisable = false;
207 uint16_t minframesize = 0;
208 uint8_t minframesizeunits = 0;
209 __MHW_VDBOX_HCP_WRAPPER_EXT(HCP_PIC_STATE_CMDPAR_EXT);
210 };
211
_MHW_PAR_T(HCP_SURFACE_STATE)212 struct _MHW_PAR_T(HCP_SURFACE_STATE)
213 {
214 uint8_t surfaceStateId = 0;
215 uint32_t surfacePitchMinus1 = 0;
216 SURFACE_FORMAT surfaceFormat = SURFACE_FORMAT::SURFACE_FORMAT_PLANAR4208;
217 uint16_t yOffsetForUCbInPixel = 0;
218 uint16_t yOffsetForVCr = 0;
219 MOS_MEMCOMP_STATE mmcState = MOS_MEMCOMP_DISABLED;
220 uint8_t mmcSkipMask = 0;
221 uint32_t dwCompressionFormat = 0;
222 };
223
_MHW_PAR_T(HCP_PIPE_MODE_SELECT)224 struct _MHW_PAR_T(HCP_PIPE_MODE_SELECT)
225 {
226 std::function<MOS_STATUS(uint32_t *cmdData)> setProtectionSettings;
227
228 uint8_t codecStandardSelect = 0;
229 bool bAdvancedRateControlEnable = false;
230 bool bStreamOutEnabled = false;
231 bool bBRCEnabled = false;
232 bool pakPiplnStrmoutEnabled = false;
233 bool bDeblockerStreamOutEnable = false;
234 bool bVdencEnabled = false;
235 bool bRdoqEnable = false;
236 bool pakFrmLvlStrmoutEnable = false;
237 bool bTileBasedReplayMode = false;
238 bool bDynamicScalingEnabled = false;
239 uint8_t codecSelect = 1;
240 uint8_t ucPhaseIndicator = 0;
241 bool bHEVCSeparateTileProgramming = false;
242 bool prefetchDisable = false;
243
244 MHW_VDBOX_HCP_PIPE_WORK_MODE pipeWorkMode = MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY;
245 MHW_VDBOX_HCP_MULTI_ENGINE_MODE multiEngineMode = MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY;
246 };
247
_MHW_PAR_T(HCP_SLICE_STATE)248 struct _MHW_PAR_T(HCP_SLICE_STATE)
249 {
250 uint32_t slicestartctbxOrSliceStartLcuXEncoder = 0;
251 uint32_t slicestartctbyOrSliceStartLcuYEncoder = 0;
252 uint32_t nextslicestartctbxOrNextSliceStartLcuXEncoder = 0;
253 uint32_t nextslicestartctbyOrNextSliceStartLcuYEncoder = 0;
254 uint8_t sliceType = 0;
255 bool lastsliceofpic = false;
256 bool sliceqpSignFlag = false;
257 bool dependentSliceFlag = false;
258 bool sliceTemporalMvpEnableFlag = false;
259 uint8_t sliceqp = 0;
260 uint8_t sliceCbQpOffset = 0;
261 uint8_t sliceCrQpOffset = 0;
262 bool intrareffetchdisable = false;
263 bool deblockingFilterDisable = false;
264 char tcOffsetDiv2 = 0;
265 char betaOffsetDiv2 = 0;
266 bool loopFilterAcrossSlicesEnabled = false;
267 bool saoLumaFlag = false;
268 bool saoChromaFlag = false;
269 bool mvdL1ZeroFlag = false;
270 bool isLowDelay = false;
271 bool collocatedFromL0Flag = false;
272 uint8_t chromalog2Weightdenom = 0;
273 uint8_t lumaLog2WeightDenom = 0;
274 bool cabacInitFlag = false;
275 uint8_t maxmergeidx = 0;
276 uint8_t collocatedrefidx = 0;
277 uint16_t sliceheaderlength = 0;
278 bool cabaczerowordinsertionenable = false;
279 bool emulationbytesliceinsertenable = false;
280 bool tailInsertionEnable = false;
281 bool slicedataEnable = false;
282 bool headerInsertionEnable = false;
283 uint32_t indirectPakBseDataStartOffsetWrite = 0;
284 uint16_t transformskiplambda = 0;
285 uint8_t transformskipNumzerocoeffsFactor0 = 0;
286 uint8_t transformskipNumnonzerocoeffsFactor0 = 0;
287 uint8_t transformskipNumzerocoeffsFactor1 = 0;
288 uint8_t transformskipNumnonzerocoeffsFactor1 = 0;
289 bool lastSliceInTile = false;
290 bool lastSliceInTileColumn = false;
291 uint8_t roundinter = 0;
292 uint8_t roundintra = 0;
293 };
294
_MHW_PAR_T(HCP_IND_OBJ_BASE_ADDR_STATE)295 struct _MHW_PAR_T(HCP_IND_OBJ_BASE_ADDR_STATE)
296 {
297 PMOS_RESOURCE presDataBuffer = nullptr;
298 uint32_t dwDataSize = 0;
299 uint32_t dwDataOffset = 0;
300 PMOS_RESOURCE presMvObjectBuffer = nullptr;
301 uint32_t dwMvObjectSize = 0;
302 uint32_t dwMvObjectOffset = 0;
303 PMOS_RESOURCE presPakBaseObjectBuffer = nullptr;
304 uint32_t dwPakBaseObjectSize = 0;
305 uint32_t dwPakBaseObjectOffset = 0;
306 PMOS_RESOURCE presPakTileSizeStasBuffer = nullptr;
307 uint32_t dwPakTileSizeStasBufferSize = 0;
308 uint32_t dwPakTileSizeRecordOffset = 0;
309 PMOS_RESOURCE presCompressedHeaderBuffer = nullptr;
310 uint32_t dwCompressedHeaderSize = 0;
311 PMOS_RESOURCE presProbabilityDeltaBuffer = nullptr;
312 uint32_t dwProbabilityDeltaSize = 0;
313 PMOS_RESOURCE presProbabilityCounterBuffer = nullptr;
314 uint32_t dwProbabilityCounterOffset = 0;
315 uint32_t dwProbabilityCounterSize = 0;
316 PMOS_RESOURCE presTileRecordBuffer = nullptr;
317 uint32_t dwTileRecordSize = 0;
318 PMOS_RESOURCE presCuStatsBuffer = nullptr;
319 uint32_t dwCuStatsSize = 0;
320 PMOS_RESOURCE presStreamOutObjectBuffer = nullptr;
321 uint32_t dwStreamOutObjectSize = 0;
322 uint32_t dwStreamOutObjectOffset = 0;
323 };
324
_MHW_PAR_T(HCP_QM_STATE)325 struct _MHW_PAR_T(HCP_QM_STATE)
326 {
327 uint8_t predictionType = 0;
328 uint8_t sizeid = 0;
329 uint8_t colorComponent = 0;
330 uint8_t dcCoefficient = 0;
331 uint32_t quantizermatrix[16] = {};
332 };
333
_MHW_PAR_T(HCP_FQM_STATE)334 struct _MHW_PAR_T(HCP_FQM_STATE)
335 {
336 uint8_t intraInter = 0;
337 uint8_t sizeid = 0;
338 uint8_t colorComponent = 0;
339 uint16_t fqmDcValue1Dc = 0;
340 uint32_t quantizermatrix[32] = {};
341 };
342
_MHW_PAR_T(HCP_BSD_OBJECT)343 struct _MHW_PAR_T(HCP_BSD_OBJECT)
344 {
345 };
346
_MHW_PAR_T(HCP_TILE_STATE)347 struct _MHW_PAR_T(HCP_TILE_STATE)
348 {
349 };
350
_MHW_PAR_T(HCP_REF_IDX_STATE)351 struct _MHW_PAR_T(HCP_REF_IDX_STATE)
352 {
353 uint8_t ucList = 0;
354 uint8_t numRefIdxLRefpiclistnumActiveMinus1 = 0;
355 uint8_t listEntryLxReferencePictureFrameIdRefaddr07[MAX_REF_FRAME_NUM + 1] = {};
356 uint8_t referencePictureTbValue[MAX_REF_FRAME_NUM + 1] = {};
357 bool longtermreference[MAX_REF_FRAME_NUM + 1] = {};
358 bool fieldPicFlag[MAX_REF_FRAME_NUM + 1] = {};
359 bool bottomFieldFlag[MAX_REF_FRAME_NUM + 1] = {};
360 };
361
_MHW_PAR_T(HCP_WEIGHTOFFSET_STATE)362 struct _MHW_PAR_T(HCP_WEIGHTOFFSET_STATE)
363 {
364 uint8_t ucList = 0;
365 char LumaWeights[2][15] = {};
366 char LumaOffsets[2][15] = {};
367 char ChromaWeights[2][15][2] = {};
368 char ChromaOffsets[2][15][2] = {};
369 };
370
_MHW_PAR_T(HCP_PIPE_BUF_ADDR_STATE)371 struct _MHW_PAR_T(HCP_PIPE_BUF_ADDR_STATE)
372 {
373 uint32_t Mode = 0;
374 PMOS_SURFACE psPreDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface
375 MOS_MEMCOMP_STATE PreDeblockSurfMmcState = MOS_MEMCOMP_DISABLED;
376 PMOS_SURFACE psPostDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface
377 MOS_MEMCOMP_STATE PostDeblockSurfMmcState = MOS_MEMCOMP_DISABLED;
378 PMOS_SURFACE psRawSurface = nullptr; // Pointer to MOS_SURFACE of raw surface
379 MOS_MEMCOMP_STATE RawSurfMmcState = MOS_MEMCOMP_DISABLED;
380 PMOS_SURFACE ps4xDsSurface = nullptr;
381 MOS_MEMCOMP_STATE Ps4xDsSurfMmcState = MOS_MEMCOMP_DISABLED;
382 PMOS_SURFACE ps8xDsSurface = nullptr;
383 MOS_MEMCOMP_STATE Ps8xDsSurfMmcState = MOS_MEMCOMP_DISABLED;
384 PMOS_RESOURCE presDataBuffer = nullptr; // Handle of residual difference surface
385 PMOS_RESOURCE presReferences[CODEC_MAX_NUM_REF_FRAME] = {};
386 PMOS_RESOURCE presMfdIntraRowStoreScratchBuffer = nullptr; // Handle of MFD Intra Row Store Scratch data surface
387 PMOS_RESOURCE presMfdDeblockingFilterRowStoreScratchBuffer = nullptr; // Handle of MFD Deblocking Filter Row Store Scratch data surface
388 PMOS_RESOURCE presStreamOutBuffer = nullptr;
389 MOS_MEMCOMP_STATE StreamOutBufMmcState = MOS_MEMCOMP_DISABLED;
390 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer1 = nullptr;
391 PMOS_RESOURCE presMacroblockIldbStreamOutBuffer2 = nullptr;
392 PMOS_RESOURCE presSliceSizeStreamOutBuffer = nullptr;
393 PMOS_SURFACE psFwdRefSurface0 = nullptr;
394 PMOS_SURFACE psFwdRefSurface1 = nullptr;
395 PMOS_SURFACE psFwdRefSurface2 = nullptr;
396 bool bDynamicScalingEnable = false;
397
398 PMOS_RESOURCE presVdencIntraRowStoreScratchBuffer = nullptr; // For VDEnc, Handle of VDEnc Intra Row Store Scratch data surface
399 PMOS_RESOURCE presVdencTileRowStoreBuffer = nullptr;
400 PMOS_RESOURCE presVdencStreamOutBuffer = nullptr;
401 PMOS_RESOURCE presVdencCuObjStreamOutBuffer = nullptr;
402 PMOS_RESOURCE presVdencPakObjCmdStreamOutBuffer = nullptr;
403 PMOS_RESOURCE presVdencStreamInBuffer = nullptr;
404 PMOS_RESOURCE presVdencReferences[CODEC_MAX_NUM_REF_FRAME] = {};
405 PMOS_RESOURCE presVdenc4xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {};
406 PMOS_RESOURCE presVdenc8xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {};
407
408 PMOS_RESOURCE presVdencColocatedMVWriteBuffer = nullptr; // For AVC only
409 PMOS_RESOURCE presVdencColocatedMVReadBuffer = nullptr; // For AVC only
410 PMOS_RESOURCE presDeblockingFilterTileRowStoreScratchBuffer = nullptr; // For HEVC, VP9
411 PMOS_RESOURCE presDeblockingFilterColumnRowStoreScratchBuffer = nullptr; // For HEVC, VP9
412 PMOS_RESOURCE presMetadataLineBuffer = nullptr; // For HEVC, VP9
413 PMOS_RESOURCE presMetadataTileLineBuffer = nullptr; // For HEVC, VP9
414 PMOS_RESOURCE presMetadataTileColumnBuffer = nullptr; // For HEVC, VP9
415 PMOS_RESOURCE presSaoLineBuffer = nullptr; // For HEVC only
416 PMOS_RESOURCE presSaoTileLineBuffer = nullptr; // For HEVC only
417 PMOS_RESOURCE presSaoTileColumnBuffer = nullptr; // For HEVC only
418 PMOS_RESOURCE presCurMvTempBuffer = nullptr; // For HEVC, VP9
419 PMOS_RESOURCE presColMvTempBuffer[CODEC_MAX_NUM_REF_FRAME] = {}; // For HEVC, VP9
420 PMOS_RESOURCE presLcuBaseAddressBuffer = nullptr; // For HEVC only
421 PMOS_RESOURCE presLcuILDBStreamOutBuffer = nullptr; // For HEVC only
422 PMOS_RESOURCE presVp9ProbBuffer = nullptr; // For VP9 only
423 PMOS_RESOURCE presVp9SegmentIdBuffer = nullptr; // For VP9 only
424 PMOS_RESOURCE presHvdLineRowStoreBuffer = nullptr; // For VP9 only
425 PMOS_RESOURCE presHvdTileRowStoreBuffer = nullptr; // For VP9 only
426 PMOS_RESOURCE presSaoStreamOutBuffer = nullptr; // For HEVC only
427 PMOS_RESOURCE presSaoRowStoreBuffer = nullptr; // For HEVC only
428 PMOS_SURFACE presP010RTSurface = nullptr; // For HEVC only
429 PMOS_RESOURCE presFrameStatStreamOutBuffer = nullptr;
430 PMOS_RESOURCE presSseSrcPixelRowStoreBuffer = nullptr;
431 PMOS_RESOURCE presSegmentMapStreamIn = nullptr;
432 PMOS_RESOURCE presSegmentMapStreamOut = nullptr;
433 PMOS_RESOURCE presPakCuLevelStreamoutBuffer = nullptr;
434 PMHW_VDBOX_SURFACE_PARAMS pRawSurfParam = nullptr;
435 PMHW_VDBOX_SURFACE_PARAMS pDecodedReconParam = nullptr;
436 bool bVdencEnabled = false;
437 bool bRawIs10Bit = false;
438 bool bDecodecReconIs10Bit = false;
439 uint32_t dwNumRefIdxL0ActiveMinus1 = 0;
440 uint32_t dwNumRefIdxL1ActiveMinus1 = 0;
441 uint32_t dwLcuStreamOutOffset = 0;
442 uint32_t dwFrameStatStreamOutOffset = 0;
443 uint32_t dwVdencStatsStreamOutOffset = 0;
444 bool oneOnOneMapping = false; // Flag for indicating using 1:1 ref index mapping for vdenc
445 bool isLowDelayB = true; // Flag to indicate if it is LDB
446 bool isIFrame = false; // Flag to indicate if it is I frame
447 bool isPFrame = false; // Flag to indicate if it is P frame
448 bool bIBCEnabled = false;
449 uint8_t IBCRefIdxMask = 0;
450 PMOS_RESOURCE presVdencCumulativeCuCountStreamoutSurface = nullptr;
451
452 //Scalable
453 PMOS_RESOURCE presSliceStateStreamOutBuffer = nullptr;
454 PMOS_RESOURCE presMvUpRightColStoreBuffer = nullptr;
455 PMOS_RESOURCE presIntraPredUpRightColStoreBuffer = nullptr;
456 PMOS_RESOURCE presIntraPredLeftReconColStoreBuffer = nullptr;
457 PMOS_RESOURCE presCABACSyntaxStreamOutBuffer = nullptr;
458 PMOS_RESOURCE presCABACSyntaxStreamOutMaxAddr = nullptr;
459 };
460
_MHW_PAR_T(HCP_PAK_INSERT_OBJECT)461 struct _MHW_PAR_T(HCP_PAK_INSERT_OBJECT)
462 {
463 PBSBuffer pBsBuffer = nullptr;
464 uint32_t dwBitSize = 0;
465 uint32_t dwOffset = 0;
466 uint32_t uiSkipEmulationCheckCount = 0;
467 bool bLastPicInSeq = false;
468 bool bLastPicInStream = false;
469 bool bLastHeader = false;
470 bool bEmulationByteBitsInsert = false;
471 bool bSetLastPicInStreamData = false;
472 bool bSliceHeaderIndicator = false;
473 bool bHeaderLengthExcludeFrmSize = false;
474 uint32_t * pdwMpeg2PicHeaderTotalBufferSize = nullptr;
475 uint32_t * pdwMpeg2PicHeaderDataStartOffset = nullptr;
476 bool bResetBitstreamStartingPos = false;
477 bool bEndOfSlice = false;
478 uint32_t dwLastPicInSeqData = 0;
479 uint32_t dwLastPicInStreamData = 0;
480 PMHW_BATCH_BUFFER pBatchBufferForPakSlices = nullptr;
481 bool bVdencInUse = false;
482 uint32_t dataBitsInLastDw = 0;
483 uint8_t databyteoffset = 0;
484 uint32_t dwPadding = 0;
485 bool bIndirectPayloadEnable = false;
486 };
487
_MHW_PAR_T(HCP_VP9_PIC_STATE)488 struct _MHW_PAR_T(HCP_VP9_PIC_STATE)
489 {
490 uint32_t frameWidthInPixelsMinus1 = 0;
491 uint32_t frameHeightInPixelsMinus1 = 0;
492 uint32_t frameType = 0;
493 uint32_t adaptProbabilitiesFlag = 0;
494 uint32_t intraOnlyFlag = 0;
495 uint32_t allowHiPrecisionMv = 0;
496 uint32_t mcompFilterType = 0;
497 uint32_t refFrameSignBias02 = 0;
498 uint32_t hybridPredictionMode = 0;
499 uint32_t selectableTxMode = 0;
500 uint32_t usePrevInFindMvReferences = 0;
501 uint32_t lastFrameType = 0;
502 uint32_t refreshFrameContext = 0;
503 uint32_t errorResilientMode = 0;
504 uint32_t frameParallelDecodingMode = 0;
505 uint32_t filterLevel = 0;
506 uint32_t sharpnessLevel = 0;
507 uint32_t segmentationEnabled = 0;
508 uint32_t segmentationUpdateMap = 0;
509 uint32_t segmentationTemporalUpdate = 0;
510 uint32_t losslessMode = 0;
511 uint32_t segmentIdStreamOutEnable = 0;
512 uint32_t segmentIdStreamInEnable = 0;
513 uint32_t log2TileColumn = 0;
514 uint32_t log2TileRow = 0;
515 uint32_t sseEnable = 0;
516 uint32_t chromaSamplingFormat = 0;
517 uint32_t bitdepthMinus8 = 0;
518 uint32_t profileLevel = 0;
519 uint32_t verticalScaleFactorForLast = 0;
520 uint32_t horizontalScaleFactorForLast = 0;
521 uint32_t verticalScaleFactorForGolden = 0;
522 uint32_t horizontalScaleFactorForGolden = 0;
523 uint32_t verticalScaleFactorForAltref = 0;
524 uint32_t horizontalScaleFactorForAltref = 0;
525 uint32_t lastFrameWidthInPixelsMinus1 = 0;
526 uint32_t lastFrameHeightInPixelsMinus1 = 0;
527 uint32_t goldenFrameWidthInPixelsMinus1 = 0;
528 uint32_t goldenFrameHeightInPixelsMinus1 = 0;
529 uint32_t altrefFrameWidthInPixelsMinus1 = 0;
530 uint32_t altrefFrameHeightInPixelsMinus1 = 0;
531 uint32_t uncompressedHeaderLengthInBytes70 = 0;
532 uint32_t firstPartitionSizeInBytes150 = 0;
533 uint32_t baseQIndexSameAsLumaAc = 0;
534 uint32_t headerInsertionEnable = 0;
535 uint32_t chromaAcQIndexDelta = 0;
536 uint32_t chromaDcQIndexDelta = 0;
537 uint32_t lumaDcQIndexDelta = 0;
538 uint32_t lfRefDelta0 = 0;
539 uint32_t lfRefDelta1 = 0;
540 uint32_t lfRefDelta2 = 0;
541 uint32_t lfRefDelta3 = 0;
542 uint32_t lfModeDelta0 = 0;
543 uint32_t lfModeDelta1 = 0;
544 uint32_t bitOffsetForLfRefDelta = 0;
545 uint32_t bitOffsetForLfModeDelta = 0;
546 uint32_t bitOffsetForQIndex = 0;
547 uint32_t bitOffsetForLfLevel = 0;
548 uint32_t vdencPakOnlyPass = 0;
549 uint32_t bitOffsetForFirstPartitionSize = 0;
550 };
551
_MHW_PAR_T(HCP_VP9_SEGMENT_STATE)552 struct _MHW_PAR_T(HCP_VP9_SEGMENT_STATE)
553 {
554 uint32_t segmentId = 0;
555 uint32_t segmentSkipped = 0;
556 uint32_t segmentReference = 0;
557 uint32_t segmentReferenceEnabled = 0;
558 uint32_t filterLevelRef0Mode0 = 0;
559 uint32_t filterLevelRef0Mode1 = 0;
560 uint32_t filterLevelRef1Mode0 = 0;
561 uint32_t filterLevelRef1Mode1 = 0;
562 uint32_t filterLevelRef2Mode0 = 0;
563 uint32_t filterLevelRef2Mode1 = 0;
564 uint32_t filterLevelRef3Mode0 = 0;
565 uint32_t filterLevelRef3Mode1 = 0;
566 uint32_t lumaDcQuantScaleDecodeModeOnly = 0;
567 uint32_t lumaAcQuantScaleDecodeModeOnly = 0;
568 uint32_t chromaDcQuantScaleDecodeModeOnly = 0;
569 uint32_t chromaAcQuantScaleDecodeModeOnly = 0;
570 uint32_t segmentQindexDeltaEncodeModeOnly = 0;
571 uint32_t segmentLfLevelDeltaEncodeModeOnly = 0;
572 };
573
_MHW_PAR_T(HEVC_VP9_RDOQ_STATE)574 struct _MHW_PAR_T(HEVC_VP9_RDOQ_STATE)
575 {
576 bool disableHtqPerformanceFix0 = false;
577 bool disableHtqPerformanceFix1 = false;
578 uint16_t lambdaTab[2][2][76] = {};
579 };
580
_MHW_PAR_T(HCP_TILE_CODING)581 struct _MHW_PAR_T(HCP_TILE_CODING)
582 {
583 uint32_t numOfTileColumnsInFrame = 0;
584 uint32_t tileStartLCUX = 0;
585 uint32_t tileStartLCUY = 0;
586 uint16_t tileHeightInMinCbMinus1 = 0;
587 uint16_t tileWidthInMinCbMinus1 = 0;
588 bool isLastTileofColumn = false;
589 bool isLastTileofRow = false;
590 uint32_t tileRowStoreSelect = 0;
591 uint32_t tileColumnStoreSelect = 0;
592 bool nonFirstPassTile = false;
593 bool bitstreamByteOffsetEnable = false;
594 uint32_t numberOfActiveBePipes = 0;
595 uint32_t bitstreamByteOffset = 0;
596 uint32_t pakTileStatisticsOffset = 0;
597 uint32_t cuLevelStreamoutOffset = 0;
598 uint32_t sliceSizeStreamoutOffset = 0;
599 uint32_t cuRecordOffset = 0;
600 uint32_t sseRowstoreOffset = 0;
601 uint32_t saoRowstoreOffset = 0;
602 uint32_t tileSizeStreamoutOffset = 0;
603 uint32_t vp9ProbabilityCounterStreamoutOffset = 0;
604 };
605
_MHW_PAR_T(HCP_PALETTE_INITIALIZER_STATE)606 struct _MHW_PAR_T(HCP_PALETTE_INITIALIZER_STATE)
607 {
608 };
609
610 } // namespace hcp
611 } // namespace vdbox
612 } // namespace mhw
613
614 #endif // __MHW_VDBOX_HCP_CMDPAR_H__
615